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Commit da2d549d authored by Andrey Filippov's avatar Andrey Filippov
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removed extra debug signals, fixed tools settings after vdt update

parent cbed019c
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.project
View file @ da2d549d
...@@ -62,42 +62,42 @@ ...@@ -62,42 +62,42 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150905203536090.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150905180655479.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150905202128057.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150905181423920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150905202638924.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ da2d549d
...@@ -2,5 +2,6 @@ FPGA_project_0_SimulationTopFile=x393_testbench02.tf ...@@ -2,5 +2,6 @@ FPGA_project_0_SimulationTopFile=x393_testbench02.tf
FPGA_project_1_SimulationTopModule=x393_testbench02 FPGA_project_1_SimulationTopModule=x393_testbench02
FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ da2d549d
...@@ -3,5 +3,6 @@ VivadoBitstream_105_force=true ...@@ -3,5 +3,6 @@ VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true VivadoBitstream_124_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@-> VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
fpga_version.vh
View file @ da2d549d
parameter FPGA_VERSION = 32'h03930015; parameter FPGA_VERSION = 32'h03930016;
\ No newline at end of file \ No newline at end of file
sensor/sens_histogram.v
View file @ da2d549d
...@@ -52,7 +52,7 @@ module sens_histogram #( ...@@ -52,7 +52,7 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware input monochrome // tie to 0 to reduce hardware
,output debug_mclk // ,output debug_mclk
`ifdef DEBUG_RING `ifdef DEBUG_RING
,output debug_do, // output to the debug ring ,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
...@@ -137,7 +137,7 @@ module sens_histogram #( ...@@ -137,7 +137,7 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps) reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
reg debug_vert_woi_r; // reg debug_vert_woi_r;
reg [15:0] debug_line_cntr; reg [15:0] debug_line_cntr;
reg [15:0] debug_lines; reg [15:0] debug_lines;
...@@ -226,7 +226,7 @@ module sens_histogram #( ...@@ -226,7 +226,7 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0; if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin; else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi; // debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active // hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
...@@ -391,7 +391,7 @@ module sens_histogram #( ...@@ -391,7 +391,7 @@ module sens_histogram #(
); );
`endif `endif
/*
pulse_cross_clock pulse_cross_clock_debug_mclk_i ( pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input .rst (prst), // input
.src_clk (pclk), // input .src_clk (pclk), // input
...@@ -402,7 +402,7 @@ module sens_histogram #( ...@@ -402,7 +402,7 @@ module sens_histogram #(
.out_pulse (debug_mclk), // output .out_pulse (debug_mclk), // output
.busy() // output .busy() // output
); );
*/
cmd_deser #( cmd_deser #(
.ADDR (HISTOGRAM_ADDR), .ADDR (HISTOGRAM_ADDR),
......
sensor/sensor_channel.v
View file @ da2d549d
...@@ -507,7 +507,7 @@ module sensor_channel#( ...@@ -507,7 +507,7 @@ module sensor_channel#(
.sda (sns_sda) // inout .sda (sns_sda) // inout
); );
wire [3:0] debug_hist_mclk; // wire [3:0] debug_hist_mclk;
wire irst; // @ posedge ipclk wire irst; // @ posedge ipclk
localparam STATUS_ALIVE_WIDTH = 8; localparam STATUS_ALIVE_WIDTH = 8;
wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive; wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
...@@ -516,9 +516,9 @@ module sensor_channel#( ...@@ -516,9 +516,9 @@ module sensor_channel#(
wire sof_mclk; wire sof_mclk;
wire eof_mclk; wire eof_mclk;
reg hist_rq0_r; reg hist_rq0_r;
/// reg hist_gr0_r; reg hist_gr0_r;
wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r; wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r;
/// wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r; wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r;
// sof_out_mclk - already exists // sof_out_mclk - already exists
reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
...@@ -526,7 +526,8 @@ module sensor_channel#( ...@@ -526,7 +526,8 @@ module sensor_channel#(
wire last_in_line_1cyc_mclk; wire last_in_line_1cyc_mclk;
// debug_hist_mclk is never active, alive_hist0_rq == 0 // debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk}; // assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk}; // assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
/* /*
sof, hact are tested to be active sof, hact are tested to be active
...@@ -543,7 +544,7 @@ module sensor_channel#( ...@@ -543,7 +544,7 @@ module sensor_channel#(
always @ (posedge mclk) begin always @ (posedge mclk) begin
hist_rq0_r <= en_mclk & (hist_rq[0] ^ hist_rq0_r); hist_rq0_r <= en_mclk & (hist_rq[0] ^ hist_rq0_r);
/// hist_gr0_r <= hist_gr[0]; hist_gr0_r <= hist_gr[0];
end end
/* /*
...@@ -840,7 +841,7 @@ module sensor_channel#( ...@@ -840,7 +841,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0] .cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input .cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input .monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[0]) // ,.debug_mclk(debug_hist_mclk[0])
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output ,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
...@@ -896,7 +897,7 @@ module sensor_channel#( ...@@ -896,7 +897,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0] .cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input .cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input .monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[1]) // ,.debug_mclk(debug_hist_mclk[1])
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output ,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
...@@ -949,7 +950,7 @@ module sensor_channel#( ...@@ -949,7 +950,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0] .cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input .cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input .monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[2]) // ,.debug_mclk(debug_hist_mclk[2])
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output ,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
...@@ -1001,7 +1002,7 @@ module sensor_channel#( ...@@ -1001,7 +1002,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0] .cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input .cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input .monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[3]) // ,.debug_mclk(debug_hist_mclk[3])
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output ,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
......
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