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Commit da24e724 authored by Andrey Filippov's avatar Andrey Filippov
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simulating image generation and debugging implementation

parent 98c7d0ea
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cocotb/socket_command.py
View file @ da24e724
......@@ -87,8 +87,8 @@ class x393Client():
self.PORT = port
self.HOST = host # Symbolic name meaning all available interfaces
self.cmd= SocketCommand()
# print("HOST=%s"%(self.HOST))
# print("PORT=%d"%(self.PORT))
# print("HOST=%s"%(self.HOST))
# print("PORT=%d"%(self.PORT))
def communicate(self, snd_str):
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
sock.connect((self.HOST, self.PORT))
......
cocotb/x393_cocotb3_server.py
View file @ da24e724
......@@ -76,9 +76,9 @@ class X393_cocotb3_server(object):
self.dut = dut
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
self._memfile=open(mempath, 'rb+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self._memfile=open(mempath, 'wb+') #create a new file if it does not exist
self.dut._log.info ("Created a new 'memory' file %s"%(mempath)) #
#Extend to full size
self._memfile.seek(self.memhigh-1)
......@@ -91,7 +91,7 @@ class X393_cocotb3_server(object):
pass
if not readOK:
self._memfile.seek(self.memhigh-1)
self._memfile.write(chr(0))
self._memfile.write(b'\x00')#chr(0))
self._memfile.flush()
self.dut._log.info("Wrote to 0x%08x to extend file to full size"%(self.memhigh-1)) #
......@@ -195,7 +195,7 @@ class X393_cocotb3_server(object):
except:
self.logErrorTerminate("Socket seems to have died :-(")
self.dut._log.debug("1.Received from socket: %s"%(line))
yield self.executeCommand(line)
yield self.executeCommand(line) ##
self.dut._log.debug("3.Received from socket: %s"%(line))
@cocotb.coroutine
......
cocotb/x393_cocotb_lwir_04.sav
View file @ da24e724
This source diff could not be displayed because it is too large. You can view the blob instead.
cocotb/x393_dut.v
View file @ da24e724
......@@ -906,7 +906,8 @@ module x393_dut#(
// reg [639:0] TEST_TITLE="abcdef"; //S uppressThisWarning VEditor May use again later
// Simulation signals
wire CLK;
reg RST;
reg RST;
wire RST_SIM_AXI; // was RST
// reg RST_CLEAN = 1;
/*
wire [NUM_INTERRUPTS-1:0] IRQ_R = {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]};
......@@ -930,6 +931,7 @@ module x393_dut#(
*/
assign reset_out = RST || x393_i.arst;
assign RST_SIM_AXI = reset_out; // was RST before 2021
x393 #(
// TODO: Are these parameters needed? They are included in x393 from the save x393_parameters.vh
.MCONTR_WR_MASK (MCONTR_WR_MASK),
......@@ -1284,7 +1286,7 @@ module x393_dut#(
.VALID_DELAY (4.0)
) simul_axi_master_rdaddr_i (
.clk (maxigp0aclk),//CLK),// input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.arid_in (dutm0_arid_w[11:0]), // input[11:0]
.araddr_in (dutm0_araddr_w[31:0]), // input[31:0]
.arlen_in (dutm0_arlen_w[3:0]), // input[3:0]
......@@ -1318,7 +1320,7 @@ module x393_dut#(
.VALID_DELAY (4.0)
) simul_axi_master_wraddr_i (
.clk (maxigp0aclk), // input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.awid_in (dutm0_awid_w[11:0]), // input[11:0]
.awaddr_in (dutm0_awaddr_w[31:0]), // input[31:0]
.awlen_in (dutm0_awlen_w[3:0]), // input[3:0]
......@@ -1352,7 +1354,7 @@ module x393_dut#(
.VALID_DELAY (3.6)
) simul_axi_master_wdata_i (
.clk (maxigp0aclk), // input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.wid_in (dutm0_wid_w[11:0]), // input[11:0]
.wdata_in (dutm0_wdata_w[31:0]), // input[31:0]
.wstrb_in (dutm0_wstb_w[3:0]), // input[3:0]
......@@ -1371,7 +1373,7 @@ module x393_dut#(
// Until then dutm0_rready and dutm0_bready are outputs, not inputs
simul_axi_slow_ready simul_axi_slow_ready_i (
.clk (maxigp0aclk), // input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.delay (dutm0_xtra_rdlag), // input[3:0]
.valid (maxigp0rvalid), // input
.ready (maxigp0rready) // output
......@@ -1379,7 +1381,7 @@ module x393_dut#(
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk (maxigp0aclk), // input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.delay (dutm0_xtra_blag), // input[3:0]
.valid (maxigp0bvalid), // input
.ready (maxigp0bready) // output
......@@ -1389,7 +1391,7 @@ module x393_dut#(
.ADDRESS_WIDTH (SIMUL_AXI_READ_WIDTH)
) simul_axi_read_i (
.clk (maxigp0aclk), // input
.reset (RST), // input
.reset (RST_SIM_AXI), // input
.last (maxigp0rlast), // input
.data_stb (maxigp0rready & maxigp0rvalid), // input
.raddr (dutm0_araddr_w[SIMUL_AXI_READ_WIDTH+1:2]), // input[9:0]
......@@ -1406,7 +1408,7 @@ module x393_dut#(
simul_axi_hp_rd #(
.HP_PORT(0)
) simul_axi_hp_rd_i (
.rst (RST), // input
.rst (RST_SIM_AXI), // input
.aclk (x393_i.ps7_i.SAXIHP0ACLK), // input
.aresetn (), // output
.araddr (x393_i.ps7_i.SAXIHP0ARADDR[31:0]), // input[31:0]
......@@ -1449,7 +1451,7 @@ simul_axi_hp_rd #(
simul_axi_hp_wr #(
.HP_PORT(0)
) simul_axi_hp_wr_i (
.rst (RST), // input
.rst (RST_SIM_AXI), // input
.aclk (x393_i.ps7_i.SAXIHP0ACLK), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIHP0AWADDR), // input[31:0]
......@@ -1496,7 +1498,7 @@ simul_axi_hp_wr #(
simul_axi_hp_wr #(
.HP_PORT(1)
) simul_axi_hp1_wr_i (
.rst (RST), // input
.rst (RST_SIM_AXI), // input
.aclk (x393_i.ps7_i.SAXIHP1ACLK), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIHP1AWADDR), // input[31:0]
......@@ -1542,7 +1544,7 @@ simul_axi_hp_wr #(
// SAXI_GP0 - histograms to system memory
simul_saxi_gp_wr simul_saxi_gp0_wr_i (
.rst (RST), // input
.rst (RST_SIM_AXI), // input
.aclk (saxi0_aclk), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIGP0AWADDR), // input[31:0]
......@@ -1579,7 +1581,7 @@ simul_axi_hp_wr #(
// SAXI_GP1 - event logger to system memory
simul_saxi_gp_wr simul_saxi_gp1_wr_i (
.rst (RST), // input
.rst (RST_SIM_AXI), // input
.aclk (saxi0_aclk), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIGP1AWADDR), // input[31:0]
......@@ -1982,7 +1984,7 @@ simul_axi_hp_wr #(
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_1_i (
.mrst (sns1_dp[7]), // input
.single (1'b0), // boson_single), // input
.single (boson_single), // input 1'b0), //
.ext_sync (sns1_ctl), // input
.pxd (boson_pxd1), // output[15:0]
.pclk (boson_pclk1), // output
......@@ -2021,7 +2023,7 @@ simul_axi_hp_wr #(
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_2_i (
.mrst (sns2_dp[7]), // input
.single (1'b0), // boson_single), // input
.single (boson_single), // input 1'b0), //
.ext_sync (sns2_ctl), // input
.pxd (boson_pxd2), // output[15:0]
.pclk (boson_pclk2), // output
......
cocotb/x393interfaces.py
View file @ da24e724
......@@ -180,9 +180,9 @@ class SAXIWrSim(BusDriver):
# self.log.debug ("SAXIWrSim.__init__(): super done")
#Open file to use as system memory
try:
self._memfile=open(mempath, 'r+') #keep old file if it exists already
self._memfile=open(mempath, 'rb+') #keep old file if it exists already
except:
self._memfile=open(mempath, 'w+') #create a new file if it does not exist
self._memfile=open(mempath, 'wb+') #create a new file if it does not exist
self.log.info ("SAXIWrSim(%s): created a new 'memory' file %s"%(name,mempath)) #
#Extend to full size
self._memfile.seek(memhigh-1)
......@@ -255,7 +255,8 @@ class SAXIWrSim(BusDriver):
bv = self.bus.wr_data.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
data = bv.integer
sdata=struct.pack(self._fmt,data).decode('iso-8859-1')
# sdata=struct.pack(self._fmt,data).decode('iso-8859-1')
sdata = data.to_bytes(self._data_bytes, byteorder='little') # byte array
bv = self.bus.wr_data.value
bv.binstr= re.sub("[^0]","1",bv.binstr) # only 0 suppresses write to this byte
while len(bv.binstr) < self._data_bytes: # very unlikely
......@@ -265,9 +266,9 @@ class SAXIWrSim(BusDriver):
else:
for i in range (self._data_bytes):
if bv.binstr[-1-i] != 0:
self._memfile.write(sdata[i])
self._memfile.write(sdata[i:i+1])
else:
self._memfile.seek(1,1)
self._memfile.seek(1,1)
if self.autoflush:
self._memfile.flush()
self.log.info ("SAXIWrSim(%s:%d) 0x%x <- 0x%x"%(self.name,self._data_bytes,address,data))
......@@ -383,7 +384,8 @@ class SAXIRdSim(BusDriver):
rs = None
if not rs is None:
try:
data = struct.unpack(self._fmt,rs)
# data = struct.unpack(self._fmt,rs)
data = int.from_bytes(rs, byteorder='little')
except:
self.log.warning ("SAXIRdSim():Can not unpack memory data @ address 0x%08x"%(address))
data=None
......
includes/x393_parameters.vh
View file @ da24e724
......@@ -687,7 +687,7 @@
// parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD
//`define TWEAKING_IOSTANDARD
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
......@@ -707,8 +707,13 @@
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`endif
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -734,7 +739,19 @@
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
`ifdef BOSON
parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", // "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", // "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
`else
parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
......@@ -746,7 +763,7 @@
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
`endif
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
......@@ -756,16 +773,16 @@
//`ifdef HISPI
parameter HISPI_MSB_FIRST = 0,
`ifdef BOSON
parameter HISPI_NUMLANES = 3,
`else
parameter HISPI_NUMLANES = 4,
`endif
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
......@@ -778,8 +795,23 @@
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v /x393/sensor line 42 Problem of the external builder
//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v /x393/sensor line 42 Problem of the external builder
`ifdef BOSON
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
`else
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
`endif
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......
py393/boson_commands.ods
View file @ da24e724
No preview for this file type
py393/x393_export_c.py
View file @ da24e724
......@@ -1909,10 +1909,10 @@ class X393ExportC(object):
dw.append(("perr", 9, 1,0, "Parity error in video stream"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked - wait after removing sensor mrst!"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("recv_prgrs", 14, 1,0, "UART packet receive in progress"))
dw.append(("recv_dav", 15, 1,0, "Byte available in received UART packet"))
dw.append(("recv_pav", 14, 1,0, "UART FIFO has at least one packet in FIFO (8-bit packet counter)"))
dw.append(("recv_eop", 15, 1,0, "End of packet - discard recv_data, apply recv_next"))
dw.append(("recv_data", 16, 8,0, "Received UART data byte"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xmit_busy", 25, 1,0, "UART transmitter busy"))
......
py393/x393_jpeg.py
View file @ da24e724
......@@ -933,13 +933,16 @@ class X393Jpeg(object):
circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_ENDS[channel] - x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
verbose = verbose)
if verbose > 2 :
if verbose > 0: # 2 :
print ("meta = ",meta)
if verbose > 1 :
for s in meta["segments"]:
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
if "@" in file_path:
fts=("%f"%(meta["timestamp"])).replace(".","_")
try:
fts=("%f"%(meta["timestamp"])).replace(".","_")
except:
fts=str(channel)
file_path=file_path[:file_path.rindex('@')]+fts+file_path[file_path.rindex('@')+1:] #replacing '@'
with open (server_root+file_path, "w+b") as bf:
bf.write(jpeg_data["header"])
......
py393/x393_sens_cmprs.py
View file @ da24e724
......@@ -823,6 +823,13 @@ class X393SensCmprs(object):
mrst = False,
mmcm_rst = False,
set_delays = False)
#Wait pclk MMCM lock!
locked_pxd_mmcm = False
print ("Waiting for PCLK MMCM lock")
while not locked_pxd_mmcm:
sensor_status = self.x393Sensor.get_new_status(num_sensor=num_sensor)
locked_pxd_mmcm = ((sensor_status >> 12) & 1) != 0
print ("PCLK MMCM locked")
self.x393Sensor.set_sensor_uart_ctl_boson (
num_sensor = num_sensor,
uart_extif_en = True,
......
py393/x393_sensor.py
View file @ da24e724
......@@ -1610,36 +1610,60 @@ class X393Sensor(object):
print ("wait_sensio_status(): Failed to get seq_num== 0x%x, current is 0x%x"%(seq_num, (stat >> 26) & 0x3f))
return stat
def uart_print_packet(self,
num_sensor,
wait_packet = True,
enable_sequencer = True):
"""
Send packet to UART
@param num_sensor - sensor port number (0..3)
@param wait packet - if False, return empty packet if none is available
@param enable_sequencer (Re)enable sequencer commands
"""
packet = self.uart_receive_packet(
num_sensor = num_sensor,
wait_packet = wait_packet,
enable_sequencer = enable_sequencer)
print ("received UART packet: ", end="")
for b in packet:
print (hex(b), end=", ")
print()
def uart_receive_packet(self,
num_sensor,
enable_sequencer=True):
wait_packet = True,
enable_sequencer = True):
"""
Send packet to UART
@param num_sensor - sensor port number (0..3)
@param wait packet - if False, return empty packet if none is available
@param enable_sequencer (Re)enable sequencer commands
"""
ready = False
while not ready: # wait full packet is in FIFO
recv_pav = False
packet = bytearray()
while not recv_pav: # wait full packet is in FIFO
sensor_status = self.get_new_status(num_sensor=num_sensor)
recv_dav = ((sensor_status >> 15) & 1) != 0
recv_prgrs = ((sensor_status >> 14) & 1) != 0
ready = recv_dav and (not recv_prgrs)
recv_pav = ((sensor_status >> 14) & 1) != 0
# recv_eop = ((sensor_status >> 15) & 1) != 0
# ready = recv_dav and (not recv_prgrs)
if not wait_packet:
break
if not recv_pav:
return packet # empty bytearray
#read byte array. TODO: improve waiting for tghe next byte?
packet = bytearray()
recv_dav = True
while recv_dav:
# packet = bytearray()
recv_eop = False
while not recv_eop:
sensor_status = self.get_new_status(num_sensor=num_sensor)
recv_dav = ((sensor_status >> 15) & 1) != 0
recv_eop = ((sensor_status >> 15) & 1) != 0
recv_data = (sensor_status >> 16) & 0xff
if recv_dav:
packet.append(recv_data)
self.set_sensor_uart_ctl_boson ( # next byte
num_sensor = num_sensor,
uart_recv_next = True)
if not recv_eop:
packet.append(recv_data)
#
return packet
......
sensor/sens_103993.v
View file @ da24e724
......@@ -148,10 +148,9 @@ module sens_103993 #(
// input trigger_mode, // running in triggered mode (0 - free running mode)
input ext_sync, // trig, // per-sensor trigger input
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input [3:0] sns_dp, // NUMLANES-1, use all with dummy for IOSTANDARD (otherwise uses default that does not match bank)
input [3:0] sns_dn, // NUMLANES-1, use all with dummy for IOSTANDARD (otherwise uses default that does not match bank)
input sns_clkp,
input sns_clkn,
......@@ -163,6 +162,8 @@ module sens_103993 #(
inout sns_gp0, // sns_dp[5] == gp[0] TDI (differs from 10353)
inout sns_gp1, // sns_dn[5] == gp[1]
inout sns_dp6, // unused, just to select IOstandard
output sns_txd, // flash_tdo, // sns_dp[4] TDO (differs from 10353)
input sns_rxd, // shutter_done,// sns_dn[4] DONE (differs from 10353)
......@@ -243,8 +244,8 @@ module sens_103993 #(
reg recv_next; // input
wire xmit_busy; // output
wire recv_prgrs; // output
wire recv_dav; // output fifo not empty
wire recv_pav; // output
wire recv_eop; // output fifo not empty
wire [7:0] recv_data; // output[7:0]
wire senspgmin; // detect sensorboard
......@@ -253,10 +254,10 @@ module sens_103993 #(
wire gp_comb = &gp[3:0];
assign status = {recv_data[7:0], // [23:16]
recv_dav, // 15
recv_prgrs, // 14
recv_eop, // 15
recv_pav, // 14
mrst ? gp_comb : hact_alive, // 13 using gp_comb to keep
locked_pclk, // 12
locked_pclk, // 12 // wait after mrst
clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
......@@ -406,8 +407,8 @@ module sens_103993 #(
.xmit_busy (xmit_busy), // output
.recv_rst (recv_rst), // input
.recv_next (recv_next), // input
.recv_prgrs (recv_prgrs), // output
.recv_dav (recv_dav), // output fifo not empty
.recv_pav (recv_pav), // output at least one received packet is in fifo
.recv_eop (recv_eop), // output end of packet (discard recv_data; apply recv_next)
.recv_data (recv_data) // output[7:0]
);
......@@ -445,8 +446,8 @@ module sens_103993 #(
.LVDS_IOSTANDARD (LVDS_IOSTANDARD) // "DIFF_SSTL18_I")
) sens_103993_l3_i (
.pclk (pclk), // output
.sns_dp (sns_dp), // input[2:0]
.sns_dn (sns_dn), // input[2:0]
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd), // output[15:0]
......@@ -455,8 +456,8 @@ module sens_103993 #(
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
// .dly_data (data_r[23:0]), // input[23:0]
.dly_data (data_r), // input[23:0]
// .dly_data (data_r[23:0]), // input[23:0]
.dly_data (data_r[23:0]), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
......@@ -557,6 +558,46 @@ module sens_103993 #(
.T (~|gp_r[7:6]) // input
);
// dummy I/O to specify IOSTANDARD
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_dp6_i (
.O (), // output
.IO (sns_dp6), // inout
.I (1'b0), // input
.T (1'b0) // input
);
// dummy I/O to specify IOSTANDARD
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_dp3_i (
.O (), // output
.IO (sns_dp[3]), // inout
.I (1'b0), // input
.T (1'b0) // input
);
// dummy I/O to specify IOSTANDARD
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_dn3_i (
.O (), // output
.IO (sns_dn[3]), // inout
.I (1'b0), // input
.T (1'b0) // input
);
// end of dummy
// READ RXD
ibuf_ibufg #(
......
sensor/sens_103993_deser10.v
View file @ da24e724
......@@ -44,10 +44,11 @@ module sens_103993_deser10(
input din,
output [9:0] dout
);
reg [9:0] sr;
// reg [9:0] sr;
reg [9:0] dout_r;
wire [9:0] pre_sr;
// wire [9:0] pre_sr;
assign dout = dout_r;
/*
assign pre_sr = {sr[8:0], din};
always @(posedge pclk10) begin
sr <= pre_sr;
......@@ -55,5 +56,26 @@ module sens_103993_deser10(
always @(posedge pclk) begin
dout_r <= pre_sr;
end
*/
reg xclk_r;
reg [2:0] copy_r;
reg [11:0] sr;
reg [ 9:0] dout_pclk10;
always @(posedge pclk or posedge copy_r[2]) begin // re_simulate!
if (copy_r[2]) xclk_r <= 0;
else xclk_r <= 1;
end
always @ (negedge pclk10) begin
copy_r <= {copy_r[1] & ~copy_r[0], copy_r[0], xclk_r};
sr <= {sr[10:0], din};
if (copy_r[2]) dout_pclk10 <= sr[11:2];
end
always @(posedge pclk) begin
dout_r <= dout_pclk10;
end
endmodule
sensor/sensor_channel.v
View file @ da24e724
......@@ -706,6 +706,8 @@ module sensor_channel#(
// TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
`ifdef LWIR
assign lens_pxd_in = pxd[15:0];
`elsif BOSON
assign lens_pxd_in = pxd[15:0];
`else
assign lens_pxd_in = {pxd[11:0],4'b0};
`endif
......@@ -1177,6 +1179,7 @@ module sensor_channel#(
`elsif BOSON
wire vsync;
wire dvalid;
wire hsync;
sens_103993 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -1254,12 +1257,12 @@ module sensor_channel#(
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start), // input
// .trigger_mode (trigger_mode), // input
// .trigger_mode (trigger_mode), // input
.ext_sync (trig), // input
// .sns_dp (sns_dp[2:0]), // input[2:0]
// .sns_dn (sns_dn[2:0]), // input[2:0]
.sns_dp (sns_dp), // input[2:0]
.sns_dn (sns_dn), // input[2:0]
// .sns_dp (sns_dp[2:0]), // input[2:0]
// .sns_dn (sns_dn[2:0]), // input[2:0]
.sns_dp (sns_dp[3:0]), // input[2:0]
.sns_dn (sns_dn[3:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.sns_gp2 (sns_dn74[6]), // inout
......@@ -1269,11 +1272,12 @@ module sensor_channel#(
.sns_gp3 (sns_dn74[7]), // output
.sns_gp0 (sns_dp74[5]), // output
.sns_gp1 (sns_dn74[5]), // output
.sns_dp6 (sns_dp74[6]), // unused, just to select IOstandard
.sns_txd (sns_dp74[4]), // input
.sns_rxd (sns_dn74[4]), // input
.pxd (pxd), // output[11:0]
.vsync (vsync), // output
.hsync (), // hsync), // output
.hsync (hsync), // output
.dvalid (dvalid), // output
// interface for uart in write-only mode for short commands
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
......@@ -1283,12 +1287,31 @@ module sensor_channel#(
.extif_ready (extif_ready), // output
.extif_rst (extif_rst) // input
);
reg vsync_d;
reg [3:0] vsync_dly_cntr;
reg vsync_late;
reg vsync_d;
reg hsync_d;
wire hsync_next;
wire pre_sof;
reg sof_r;
assign hsync_next = !hsync && hsync_d;
assign pre_sof = hsync_next && (vsync_dly_cntr==0);
// it what vsync state does it wait for ext sync?
always @(posedge pclk) begin
if (vsync) vsync_dly_cntr <= 5; // arbitrary, need to end at list 1 before active output (including telemetry - 87/88 lines)
else if (hsync_next && !vsync_late) vsync_dly_cntr <= vsync_dly_cntr - 1;
if (vsync) vsync_late <= 1;
else if (vsync_d) vsync_late <= 0;
else if (sof_r) vsync_late <= 1;
sof_r <= pre_sof;
vsync_d <= vsync;
hsync_d <= hsync;
end
assign sof = vsync && !vsync_d;
assign eof = !vsync && vsync_d;
assign sof = sof_r; // vsync && !vsync_d;
assign eof = !vsync && vsync_d; // change to first hsync after ?
assign hact = dvalid;
`elsif LWIR
sens_lepton3 #(
......
sensor/sensors393.v
View file @ da24e724
......@@ -907,10 +907,13 @@ module sensors393 #(
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
// .IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
`endif
// aLL SENSORS
// All SENSORS
`ifndef LWIR
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE),
`endif
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
......
sensor/serial_103993.v
View file @ da24e724
......@@ -48,7 +48,8 @@ module serial_103993#(
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
parameter EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
parameter RECV_CNTR_WIDTH = 8 // received packet counter width
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
......@@ -77,8 +78,10 @@ module serial_103993#(
input recv_rst, // reset read uart FIFO
input recv_next,
output recv_prgrs, // read in progress
output recv_dav, // read byte available
// output recv_prgrs, // read in progress
// output recv_dav, // read byte available
output recv_pav, // packet available
output recv_eop, // end of packet (discard recv_data, apply recv_next)
output [7:0] recv_data
);
......@@ -86,15 +89,14 @@ module serial_103993#(
wire [ 1:0] xmit_fifo_re_regen;
wire [10:0] xmit_fifo_waddr;
wire [10:0] xmit_fifo_raddr;
// wire [11:0] xmit_fifo_fill;
// reg xmit_fifo_rd;
wire xmit_fifo_nempty;
wire recv_fifo_wr;
wire fslp_rx_stb;
wire fslp_rx_done;
wire [ 1:0] recv_fifo_re_regen;
wire [10:0] recv_fifo_waddr;
wire [10:0] recv_fifo_raddr;
// wire [11:0] recv_fifo_fill;
wire [ 7:0] recv_fifo_din;
reg xmit_pend; // initiated soft xmit
......@@ -111,7 +113,12 @@ module serial_103993#(
reg xmit_over_d;
reg stuffer_busy_d;
reg xmit_busy_r;
reg fslp_stb_or_done; // used to push 9-th bit to FIFO (packet over)
reg fifo_out_stb;
reg packet_end_r;
reg [RECV_CNTR_WIDTH-1:0] recv_cntr;
reg recv_pav_r;
wire xmit_start_out_fifo;
wire xmit_start_out_seq;
wire xmit_start_out;
......@@ -128,7 +135,8 @@ module serial_103993#(
wire packet_ready_seq;
wire packet_over_seq;
// wire packet_sent;
// wire recv_end; // Discard recv_data, this is packet end
wire recv_prgrs; // packet is being received (to distinguish eop from data byte)
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
......@@ -137,12 +145,22 @@ module serial_103993#(
assign xmit_start_out_fifo = xmit_run && !xmit_run_d;
assign xmit_start_out_seq = extif_run && !extif_run_d;
assign xmit_start_out = xmit_start_out_fifo || xmit_start_out_seq;
// assign pre_tx_stb = !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
// TODO: is !xmit_stb_d needed?
assign pre_tx_stb = !xmit_stb_any && !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
assign xmit_busy = xmit_busy_r;
// assign packet_sent = xmit_over && !xmit_over_d;
assign recv_fifo_wr = fslp_stb_or_done;
assign recv_pav = recv_pav_r;
// assign recv_eop = recv_end;
always @(posedge mclk) begin
fslp_stb_or_done <= fslp_rx_stb || fslp_rx_done;
fifo_out_stb <= recv_fifo_re_regen[1];
packet_end_r <= fifo_out_stb && recv_eop;
if (mrst || recv_rst) recv_cntr <= 0;
else if ( fslp_rx_done && !packet_end_r) recv_cntr <= recv_cntr + 1;
else if (!fslp_rx_done && packet_end_r) recv_cntr <= recv_cntr - 1;
recv_pav_r <= |recv_cntr;
xmit_busy_r <= uart_tx_busy || stuffer_busy_d || xmit_pend || xmit_run || extif_run;
if (mrst || xmit_rst) xmit_pend <= 0;
......@@ -152,7 +170,6 @@ module serial_103993#(
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && !extif_run) xmit_run <= 1;
else if (xmit_done) xmit_run <= 0; // no need to condition with xmit_run
// else if (!stuffer_busy && !xmit_fifo_nempty) xmit_run <= 0; // no need to condition with xmit_run
xmit_run_d <= xmit_run && !mrst && !xmit_rst;
......@@ -177,7 +194,6 @@ module serial_103993#(
end
/* Instance template for module serial_103993_extif */
serial_103993_extif #(
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_extif_i (
......@@ -220,9 +236,10 @@ module serial_103993#(
.stuffer_busy (stuffer_busy), // output processing packet (not including UART)
.uart_tx_busy (uart_tx_busy), // output UART busy ('or' with stuffer_busy?)
.rx_byte (recv_fifo_din), // output[7:0] received byte output
.rx_stb (recv_fifo_wr), // output received byte strobe
// .rx_stb (recv_fifo_wr), // output received byte strobe
.rx_stb (fslp_rx_stb), // output received byte strobe
.rx_packet_run (recv_prgrs), // output run received packet
.rx_packet_done () // output finished receiving packet (last 2 bytes - crc16)
.rx_packet_done (fslp_rx_done) // output finished receiving packet (last 2 bytes - crc16)
);
fifo_sameclock_control #(
......@@ -267,7 +284,7 @@ module serial_103993#(
.rst (mrst || recv_rst), // input
.wr (recv_fifo_wr), // input
.rd (recv_next), // input
.nempty (recv_dav), // output
.nempty (), // recv_dav), // output
.fill_in (), // recv_fifo_fill), // output[11:0]
.mem_wa (recv_fifo_waddr), // output[10:0] reg
.mem_ra (recv_fifo_raddr), // output[10:0] reg
......@@ -277,21 +294,21 @@ module serial_103993#(
.under () //h2d_under) // output reg
);
ram18_var_w_var_r #(
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (3),
.LOG2WIDTH_RD (3)
) fifo_recv_i (
.rclk (mclk), // input
.raddr (recv_fifo_raddr), // input[10:0]
.ren (recv_fifo_re_regen[0]), // input
.regen (recv_fifo_re_regen[1]), // input
.data_out (recv_data), // output[7:0]
.wclk (mclk), // input
.waddr (recv_fifo_waddr), // input[10:0]
.we (recv_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in (recv_fifo_din) // input[7:0]
.rclk (mclk), // input
.raddr (recv_fifo_raddr), // input[10:0]
.ren (recv_fifo_re_regen[0]), // input
.regen (recv_fifo_re_regen[1]), // input
.data_out ({recv_eop,recv_data}), // output[7:0]
.wclk (mclk), // input
.waddr (recv_fifo_waddr), // input[10:0]
.we (recv_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in ({~recv_prgrs,recv_fifo_din}) // input[7:0]
);
......
sensor/serial_destuffer.v
View file @ da24e724
......@@ -65,6 +65,7 @@ module serial_destuffer#(
reg [2:0] replaced;
reg thru; // pass input data through
reg [1:0] out_stb;
// reg flsp_end_r;
wire flsp_start;
wire flsp_end;
......@@ -85,6 +86,8 @@ module serial_destuffer#(
assign rx_stb = out_stb[1];
assign packet_done = packet_done_r;
always @(posedge mclk) begin
// flsp_end_r <= flsp_end && !mrst;
if (mrst) in_stb <= 0;
else in_stb <= {in_stb[1:0], rx_in_stb};
......@@ -109,6 +112,7 @@ module serial_destuffer#(
if (mrst) out_stb <= 0;
else out_stb <= {out_stb[0], in_stb[1] & payload & ~is_esc};
// else out_stb <= {out_stb[0], (in_stb[1] & payload & ~is_esc) || flsp_end_r}; // added extra pulse after end
if (out_stb[0]) rxd_r <=
({8{thru}} & rxd_in_r) |
......
sensor/serial_fslp.v
View file @ da24e724
......@@ -151,7 +151,7 @@ module serial_fslp #(
.rxd_in (uart_rxd[7:0]), // input[7:0]
.rx_in_stb (uart_rx_stb), // input
.rxd_out (rx_byte[7:0]), // output[7:0]
.rx_stb (rx_stb), // output
.rx_stb (rx_stb), // output
.packet_run (rx_packet_run), // output
.packet_done (rx_packet_done) // output
);
......
simulation_modules/simul_boson640.v
View file @ da24e724
......@@ -113,7 +113,7 @@ module simul_boson640#(
always #(CLK_PERIOD/2) pclk_r <= mrst ? ~pclk_r : 1'b0;
always @ (posedge pclk_r) begin
always @ (posedge pclk_r or negedge mrst) begin
dvalid_r <= pre_dav && mrst;
if (!mrst) ext_sync_d <= 0;
......@@ -193,7 +193,7 @@ module simul_boson640#(
default: line_state <= LSTATE_IDLE;
endcase
end
if (start_frame) frame_pixel <= 0;
if (start_frame || !mrst) frame_pixel <= 0;
else if (pre_dav) frame_pixel <= frame_pixel + 1;
if (pre_dav) pxd_r <= sensor_data[frame_pixel];
......
util_modules/clocks393m.v
View file @ da24e724
......@@ -48,7 +48,8 @@ module clocks393m#(
parameter CLK_RESET = 'h0, // which clocks should stay reset after release of masrter reset {ff1,ff0,mem,sync,xclk,pclk,xclk}
parameter CLK_PWDWN = 'h0, // which clocks should stay powered down after release of masrter reset {sync,xclk,pclk,xclk}
// CLocks derived from external clock source (for sesnors
// CLocks derived from external clock source (for sensors
`ifndef PCLK_MASTER
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
......@@ -59,6 +60,7 @@ module clocks393m#(
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK2X = "BUFG",
`endif
`endif
/*
Mutltiple clocks derived from PS source (excluding memory controller) using a single PLL
Fvco = 1200Mhz - maximal for spped grade -1
......@@ -122,9 +124,12 @@ module clocks393m#(
input ffclk1n_pad, // differential clock (N) same power as sensors 0 and 1 (VCC_SENS01)
output aclk, // global clock 50 MHz (used for maxi0)
output hclk, // global clock 150MHz (used for afi*, saxi*)
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifndef PCLK_MASTER
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifdef USE_PCLK2X
output pclk2x, // global clock for sensors, 2x frequency (now 192MHz)
`endif
`endif
output xclk, // global clock for compressor (now 100MHz)
`ifdef USE_XCLK2X
......@@ -160,7 +165,11 @@ module clocks393m#(
assign locked[3:2] = 3; // for compatibility with previous clocks393.v module
assign locked_sync_clk = locked[3];
assign locked_xclk = locked[2];
`ifndef PCLK_MASTER
assign locked_pclk = locked[1];
`else
assign locked_pclk = 1'b1;
`endif
assign locked_hclk = locked[0];
always @ (posedge mclk) begin
......@@ -210,7 +219,8 @@ module clocks393m#(
BUFG bufg_axi_aclk_i (.O(aclk), .I(fclk[0])); // PS clock, 50MHz
// from external clock sourec
// from external clock source
`ifndef PCLK_MASTER
dual_clock_source #(
.CLKIN_PERIOD (CLKIN_PERIOD_PCLK),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
......@@ -236,6 +246,8 @@ module clocks393m#(
`endif
.locked (locked[1]) // output
);
`endif //ifndef PCLK_MASTER
wire multi_clkfb;
wire hclk_pre;
wire dly_ref_clk_pre;
......
util_modules/sync_resets.v
View file @ da24e724
......@@ -41,7 +41,8 @@
module sync_resets#(
parameter WIDTH = 1,
parameter REGISTER = 4 // number of registers used at crossing clocks >1
parameter REGISTER = 4, // number of registers used at crossing clocks >1
parameter ACLK_INDEX = 5
)(
input arst, // async reset
input [WIDTH-1:0] locked, // clk[i] MMCM/PLL is locked
......@@ -79,9 +80,8 @@ module sync_resets#(
for (i = 1; i < WIDTH; i = i + 1) begin: rst_block
level_cross_clocks #(
.WIDTH (1),
.REGISTER ((i==5) ? 1: REGISTER), // disable for aclk
// .REGISTER (REGISTER), // disable for aclk - aclk is now (0)
.FAST1 (1) // Switch to next cycle, to 0 - regeisterd
.REGISTER ((i == ACLK_INDEX) ? 1: REGISTER), // disable for aclk
.FAST1 (1) // Switch to next cycle, to 0 - registerd
) level_cross_clocks_rst_i (
.clk (clk[i]), // input
.d_in (mrst || rst_early_master || ~locked[i] ), // input[0:0]
......
x393.v
View file @ da24e724
......@@ -2044,6 +2044,7 @@ assign axi_grst = axi_rst_pre;
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`elsif BOSON
/*
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
......@@ -2053,7 +2054,7 @@ assign axi_grst = axi_rst_pre;
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
*/
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0),
......@@ -2074,10 +2075,10 @@ assign axi_grst = axi_rst_pre;
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
// .PXD_DRIVE (PXD_DRIVE),
// .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
// .PXD_IOSTANDARD (PXD_IOSTANDARD),
// .PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.UART_START_FRAME_BYTE (UART_START_FRAME_BYTE),// 'h8E),
......@@ -2205,8 +2206,8 @@ assign axi_grst = axi_rst_pre;
.debug_di (debug_ring[1]) // input
`endif
);
wire[7:0]debug_UART_CLK_DIV = UART_CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = UART_RX_DEBOUNCE; // 6,
// wire[7:0]debug_UART_CLK_DIV = UART_CLK_DIV; // = 22,
// wire[7:0]debug_UART_RX_DEBOUNCE = UART_RX_DEBOUNCE; // 6,
// AFI1 (AXI_HP1) signals - write channels only
wire [31:0] afi1_awaddr; // output[31:0]
......@@ -2726,11 +2727,13 @@ assign axi_grst = axi_rst_pre;
.CLK_STATUS_REG_ADDR (CLK_STATUS_REG_ADDR),
.CLK_CNTRL (CLK_CNTRL),
.CLK_STATUS (CLK_STATUS),
`ifndef PCLK_MASTER
.CLKIN_PERIOD_PCLK (CLKIN_PERIOD_PCLK),
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
`endif
`ifdef USE_PCLK2X
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
......@@ -2788,14 +2791,12 @@ assign axi_grst = axi_rst_pre;
.ffclk1n_pad (ffclk1n), // input
.aclk (axi_aclk), // output
.hclk (hclk), // output
`ifdef PCLK_MASTER
.pclk (), // output // generated by each sensor
`else
`ifndef PCLK_MASTER
.pclk (pclk), // output
`endif
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // output
`endif
`endif
.xclk (xclk), // output
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // output
......@@ -2816,10 +2817,14 @@ assign axi_grst = axi_rst_pre;
sync_resets #(
`ifdef PCLK_MASTER
.WIDTH(10), // pclk[3:0], prst[3:0], locked_pclk[3:0]
.REGISTER(7),
.ACLK_INDEX(8)
`else
.WIDTH(7), // pclk, prst, locked_pclk
.REGISTER(4),
.ACLK_INDEX(5)
`endif
.REGISTER(4)
) sync_resets_i (
.arst (axi_rst_pre), // input
.locked ({locked_hclk, 1'b1, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked}), // input
......
x393_timing.tcl
View file @ da24e724
......@@ -88,18 +88,41 @@ create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]\
#report_clocks
if { $BOSON} {
# Nothing here yet
create_clock -name clk_boson0 -period 37.037 [get_ports {sns1_clkp}]
create_clock -name clk_boson1 -period 37.037 [get_ports {sns2_clkp}]
create_clock -name clk_boson2 -period 37.037 [get_ports {sns3_clkp}]
create_clock -name clk_boson3 -period 37.037 [get_ports {sns4_clkp}]
# puts [get_nets -hierarchical ipclk_pre]
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/pclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
} elseif { $LWIR} {
# Nothing here yet
# Nothing here yet
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
} elseif {$HISPI} {
#WARNING: [Vivado 12-4777] Setting CLOCK_DEDICATED_ROUTE constraint on the PARENT net instead of the specified net segment (net name: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in). Placer only honors CLOCK_DEDICATED_ROUTE when set on the PARENT net, e.g. net segment directly connected to the driver. To eliminate this message, please update your constraint to specify the PARENT net instead. [/home/xilinx/vdt/x393/x393_timing.tcl:68]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
} else {
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
......@@ -118,10 +141,12 @@ if { $BOSON} {
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
......
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