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Commit d3f2d87c authored by Andrey Filippov's avatar Andrey Filippov
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more debugging

parent 75477a7c
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dsp/dsp_ma_preadd.v
View file @ d3f2d87c
...@@ -42,8 +42,7 @@ module dsp_ma_preadd #( ...@@ -42,8 +42,7 @@ module dsp_ma_preadd #(
parameter B_WIDTH = 18, parameter B_WIDTH = 18,
parameter A_WIDTH = 25, parameter A_WIDTH = 25,
parameter P_WIDTH = 48, parameter P_WIDTH = 48,
parameter A_INPUT = "DIRECT", // other: "CASCADE" parameter BREG = 1) // means number in series, so "2" always reads the second
parameter B_INPUT = "DIRECT") // other: "CASCADE"
( (
input clk, input clk,
input rst, input rst,
...@@ -89,10 +88,10 @@ module dsp_ma_preadd #( ...@@ -89,10 +88,10 @@ module dsp_ma_preadd #(
.ALUMODEREG (1), .ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second .AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"), .AUTORESET_PATDET ("NO_RESET"),
.A_INPUT (A_INPUT), // "DIRECT", "CASCADE" .A_INPUT ("DIRECT"), // "DIRECT", "CASCADE"
.BCASCREG (1), .BCASCREG (1),
.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second .BREG (BREG), // (2), // (1) - means number in series, so "2" always reads the second
.B_INPUT (B_INPUT), // "DIRECT"), .B_INPUT ("DIRECT"), // "DIRECT"),
.CARRYINREG (1), .CARRYINREG (1),
.CARRYINSELREG (1), .CARRYINSELREG (1),
.CREG (0), //(1), .CREG (0), //(1),
......
dsp/dsp_ma_preadd_c_dbg.v 0 → 100644
View file @ d3f2d87c
/*!
* dsp_ma_preadd_c
* @file dsp_ma_preadd.v
* @date 2016-06-05
* @author Andrey Filippov
*
* @brief DSP with multi-input multiplier and accumulator with pre-adder
* and post-adder
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
* dsp_ma_preadd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dsp_ma_preadd.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`define INSTANTIATE_DSP48E1
//`undef INSTANTIATE_DSP48E1
module dsp_ma_preadd_c_dbg #(
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
parameter P_WIDTH = 48)
(
input clk,
input rst,
input signed [B_WIDTH-1:0] bin,
input ceb1, // load b1 register
input ceb2, // load b2 register
input selb, // 0 - select b1, 1 - select b2
input signed [A_WIDTH-1:0] ain,
input cea1, // clock enable a1 reg
input cea2, // clock enable a2 reg
input signed [A_WIDTH-1:0] din,
input ced, // enable d-reg
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input cead, // enable ad register (after pre-adder)
input sela, // 0 - select a1, 1 - select a2
input en_a, // 1 - enable a input (0 - zero) ~inmode[1]
input en_d, // 1 - enable d input (0 - zero) ~inmode[2]
input sub_a, // 0 - pre-add (D+A), 1 - pre-subtract (D-A)
input neg_m, // 1 - negate multiplier result
input accum, // 0 - use multiplier result, 1 add to accumulator
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
output signed [P_WIDTH-1:0] pout
);
`ifdef INSTANTIATE_DSP48E1
initial begin
$display("dsp_ma_preadd_c_dbg, using DSP48E1");
end
wire [4:0] inmode = {~selb,
sub_a,
en_d,
~en_a,
~sela};
wire [3:0] alumode = {2'b0,
neg_m,
neg_m};
wire [6:0] opmode = {1'b0,
accum | post_add,
post_add,
2'b01,
2'b01};
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second
.B_INPUT ("DIRECT"),
.CARRYINREG (1),
.CARRYINSELREG (1),
.CREG (1), //(0),
.DREG (1),
.INMODEREG (1),
.IS_ALUMODE_INVERTED (4'b0),
.IS_CARRYIN_INVERTED (1'b0),
.IS_CLK_INVERTED (1'b0),
.IS_INMODE_INVERTED (5'b0),
.IS_OPMODE_INVERTED (7'b0),
.MASK (48'hffffffffffff),
.MREG (1),
.OPMODEREG (1),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"), //("FALSE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48")
) DSP48E1_i (
.ACOUT (), // output[29:0]
.BCOUT (), // output[17:0]
.CARRYCASCOUT (), // output
.CARRYOUT (), // output[3:0]
.MULTSIGNOUT (), // output
.OVERFLOW (), // output
.P (pout), // output[47:0]
.PATTERNBDETECT (), // output
.PATTERNDETECT (), // output
.PCOUT (), // output[47:0]
.UNDERFLOW (), // output
.A ({{30-A_WIDTH{ain[A_WIDTH-1]}}, ain}), // input[29:0]
.ACIN (30'b0), // input[29:0]
.ALUMODE (alumode), // input[3:0]
.B (bin), // input[17:0]
.BCIN (18'b0), // input[17:0]
.C (cin), // input[47:0]
.CARRYCASCIN (1'b0), // input
.CARRYIN (1'b0), // input
.CARRYINSEL (3'h0), // input[2:0] // later modify?
.CEA1 (cea1), // input
.CEA2 (cea2), // input
.CEAD (cead), // input
.CEALUMODE (1'b1), // input
.CEB1 (ceb1), // input
.CEB2 (ceb2), // input
.CEC (cec), // input
.CECARRYIN (1'b0), // input
.CECTRL (1'b1), // input
.CED (ced), // input
.CEINMODE (1'b1), // input
.CEM (1'b1), // input
.CEP (1'b1), // input
.CLK (clk), // input
.D (din), // input[24:0]
.INMODE (inmode), // input[4:0]
.MULTSIGNIN (1'b0), // input
.OPMODE (opmode), // input[6:0]
.PCIN (48'b0), // input[47:0]
.RSTA (rst), // input
.RSTALLCARRYIN (rst), // input
.RSTALUMODE (rst), // input
.RSTB (rst), // input
.RSTC (rst), // input
.RSTCTRL (rst), // input
.RSTD (rst), // input
.RSTINMODE (rst), // input
.RSTM (rst), // input
.RSTP (rst) // input
);
`else
initial begin
$display("dsp_ma_preadd_c, not using DSP48E1");
end
// Will try to make it infer DSP48e1
reg signed [B_WIDTH-1:0] b1_reg;
reg signed [B_WIDTH-1:0] b2_reg;
reg signed [A_WIDTH-1:0] a1_reg;
reg signed [A_WIDTH-1:0] a2_reg;
reg signed [A_WIDTH-1:0] d_reg;
reg signed [P_WIDTH-1:0] c_reg;
reg signed [A_WIDTH-1:0] ad_reg;
reg signed [P_WIDTH-1:0] m_reg;
reg signed [P_WIDTH-1:0] p_reg;
wire signed [A_WIDTH+B_WIDTH-1:0] m_wire;
wire signed [B_WIDTH-1:0] b_wire;
wire signed [A_WIDTH-1:0] a_wire;
wire signed [A_WIDTH-1:0] d_wire;
reg selb_r;
reg sela_r;
reg en_a_r;
reg en_d_r;
reg sub_a_r;
reg neg_m_r;
reg accum_r;
reg post_add_r;
wire signed [P_WIDTH-1:0] m_reg_pm;
wire signed [P_WIDTH-1:0] p_reg_cond;
/*
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
*/
assign pout = p_reg;
assign b_wire = selb_r ? b2_reg : b1_reg;
assign a_wire = en_a_r ? (sela_r ? a2_reg : a1_reg) : {A_WIDTH{1'b0}};
// assign d_wire = en_d_r ? (sub_a_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
assign d_wire = en_d_r ? d_reg : {A_WIDTH{1'b0}};
assign m_wire = ad_reg * b_wire;
assign m_reg_pm = neg_m_r ? - m_reg : m_reg;
// assign p_reg_cond = accum_r ? p_reg : 0;
assign p_reg_cond = post_add_r? c_reg: (accum_r ? p_reg : 0);
always @ (posedge clk) begin
if (rst) b1_reg <= 0;
else if (ceb1) b1_reg <= bin;
if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin;
if (rst) a1_reg <= 0;
else if (cea1) a1_reg <= ain;
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain;
if (rst) d_reg <= 0;
else if (ced) d_reg <= din;
if (rst) c_reg <= 0;
else if (cec) c_reg <= cin;
if (rst) ad_reg <= 0;
else if (cead) ad_reg <= sub_a_r? (d_wire - a_wire): (d_wire + a_wire);
neg_m_r <= neg_m;
accum_r <= accum;
post_add_r <= post_add;
selb_r <= selb;
sela_r <= sela;
en_a_r <= en_a;
en_d_r <= en_d;
sub_a_r <= sub_a;
m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{m_wire[A_WIDTH+B_WIDTH-1]}}, m_wire};
p_reg <= p_reg_cond + m_reg_pm;
end
`endif
endmodule
dsp/mclt16x16.v
View file @ d3f2d87c
...@@ -76,11 +76,19 @@ module mclt16x16#( ...@@ -76,11 +76,19 @@ module mclt16x16#(
output dv, //!< output data valid output dv, //!< output data valid
output signed [OUT_WIDTH - 1 : 0] dout //!<frequency domain data output output signed [OUT_WIDTH - 1 : 0] dout //!<frequency domain data output
); );
localparam DTT_OUT_DELAY = 191; // start output to sin/cos rotator, ~=3/4 of 256
localparam DTT_IN_DELAY = 195; // fune tune? ~= 3/4 of 256
// maybe use small FIFO memory?
reg [SHIFT_WIDTH-1:0] x_shft_r; // registered at start
reg [SHIFT_WIDTH-1:0] y_shft_r; // registered at start
reg [SHIFT_WIDTH-1:0] x_shft_r2; // use for the window calculation
reg [SHIFT_WIDTH-1:0] y_shft_r2; // use for the window calculation
reg [SHIFT_WIDTH-1:0] x_shft_r3; // registered @ start_dtt
reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt
reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill
reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill
reg [SHIFT_WIDTH-1:0] x_shft_r;
reg [SHIFT_WIDTH-1:0] y_shft_r;
reg [SHIFT_WIDTH-1:0] x_shft_r2;
reg [SHIFT_WIDTH-1:0] y_shft_r2;
reg [3:0] bayer_r; reg [3:0] bayer_r;
reg [3:0] bayer_d; // same latency as mpix_a_w reg [3:0] bayer_d; // same latency as mpix_a_w
reg [7:0] in_cntr; // input counter reg [7:0] in_cntr; // input counter
...@@ -139,7 +147,7 @@ module mclt16x16#( ...@@ -139,7 +147,7 @@ module mclt16x16#(
wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...) wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...)
// reading/converting DTT // reading/converting DTT
wire start_dtt = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256 reg start_dtt; // = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256
reg [7:0] dtt_r_cntr; // reg [7:0] dtt_r_cntr; //
reg dtt_r_page; reg dtt_r_page;
reg dtt_r_re; reg dtt_r_re;
...@@ -166,13 +174,21 @@ module mclt16x16#( ...@@ -166,13 +174,21 @@ module mclt16x16#(
bayer_r <= bayer; bayer_r <= bayer;
end end
start_r <= {start_r[0], start}; start_r <= {start_r[0], start};
// if (in_busy[2]) begin // same latency as mpix_a_w
if (start_r[1]) begin // same latency as mpix_a_w if (start_r[1]) begin // same latency as mpix_a_w
x_shft_r2 <= x_shft_r; x_shft_r2 <= x_shft_r; // use for the window
y_shft_r2 <= y_shft_r; y_shft_r2 <= y_shft_r;
end end
/// if (in_busy[2]) bayer_d <= bayer_r; if (start_dtt) begin
x_shft_r3 <= x_shft_r2;
y_shft_r3 <= y_shft_r2;
end
if (dtt_start_first_fill) begin
x_shft_r4 <= x_shft_r3;
y_shft_r4 <= y_shft_r3;
end
if (in_busy[1]) bayer_d <= bayer_r; if (in_busy[1]) bayer_d <= bayer_r;
if (rst) in_busy <= 0; if (rst) in_busy <= 0;
...@@ -190,11 +206,7 @@ module mclt16x16#( ...@@ -190,11 +206,7 @@ module mclt16x16#(
if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; // 1 MSB is extra if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; // 1 MSB is extra
// pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60 // pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60
/// if (in_busy[10]) pix_wnd_r2 <= {2'b00,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
if (in_busy[10]) begin if (in_busy[10]) begin
/// if (in_busy[9]) begin
/// pix_wnd_r2 <= {2'b0,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
// pix_wnd_r2_old <= {{2{pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2]}},pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w}; pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};
mpix_use_r <= mpix_use_d; mpix_use_r <= mpix_use_d;
var_first_r <= var_first_d; var_first_r <= var_first_d;
...@@ -222,6 +234,9 @@ module mclt16x16#( ...@@ -222,6 +234,9 @@ module mclt16x16#(
if (!in_busy[16]) dtt_in_cntr <= 0; if (!in_busy[16]) dtt_in_cntr <= 0;
else dtt_in_cntr <= dtt_in_cntr + 1; else dtt_in_cntr <= dtt_in_cntr + 1;
start_dtt <= dtt_in_cntr == DTT_IN_DELAY;
if (rst) dtt_in_page <= 0; if (rst) dtt_in_page <= 0;
else if (&dtt_in_cntr) dtt_in_page <= dtt_in_page + 1; else if (&dtt_in_cntr) dtt_in_page <= dtt_in_page + 1;
...@@ -435,15 +450,17 @@ D11 - negate for mode 3 (SS) ...@@ -435,15 +450,17 @@ D11 - negate for mode 3 (SS)
reg [4:0] dtt_out_ram_cntr; reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah; reg [4:0] dtt_out_ram_wah;
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill;
reg dtt_start_out; // start read out to sin/cos rotator reg dtt_start_out; // start read out to sin/cos rotator
// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first) // frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16}; wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
localparam DTT_OUT_DELAY = 192; // start output to sin/cos rotator, ~=3/4 of 256
reg [7:0] dtt_dly_cntr; reg [7:0] dtt_dly_cntr;
reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator
wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[1:0],dtt_rd_cntr[7:2]}; // page, mode, frequency // wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[1:0],dtt_rd_cntr[7:2]}; // page, mode, frequency
wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
wire [35:0] dtt_rd_data_w; // high bits are not used wire [35:0] dtt_rd_data_w; // high bits are not used
// data to be input to phase rotator // data to be input to phase rotator
...@@ -457,10 +474,14 @@ D11 - negate for mode 3 (SS) ...@@ -457,10 +474,14 @@ D11 - negate for mode 3 (SS)
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16; dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
if (rst) dtt_dly_cntr <= 0; if (rst) dtt_dly_cntr <= 0;
else if (dtt_start_fill & dtt_first_quad_out) dtt_dly_cntr <= DTT_OUT_DELAY; else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1; else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= dtt_dly_cntr == 1; dtt_start_out <= dtt_dly_cntr == 1;
if (rst) dtt_rd_regen_dv[0] <= 0; if (rst) dtt_rd_regen_dv[0] <= 0;
...@@ -534,8 +555,8 @@ D11 - negate for mode 3 (SS) ...@@ -534,8 +555,8 @@ D11 - negate for mode 3 (SS)
.rst (rst), // input .rst (rst), // input
.start (dtt_start_out), // input .start (dtt_start_out), // input
// are these shift OK? Will need to be valis only @ dtt_start_out // are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r2), // input[6:0] signed .shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r2), // input[6:0] signed .shift_v (y_shft_r4), // input[6:0] signed
.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start .fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout), // output[24:0] reg signed .fd_out (dout), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg .pre_first_out (pre_first_out), // output reg
......
dsp/mclt_test_01.tf
View file @ d3f2d87c
...@@ -95,12 +95,14 @@ module mclt_test_01 (); ...@@ -95,12 +95,14 @@ module mclt_test_01 ();
reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [WND_WIDTH - 1:0] tiles_wnd[0:1023]; reg [WND_WIDTH - 1:0] tiles_wnd[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023]; reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [DTT_IN_WIDTH - 1:0] java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_out[0:1023]; reg [DTT_IN_WIDTH - 1:0] java_dtt_out[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_rot0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_rot[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i, n, n_out; integer i, n, n_out;
initial begin initial begin
$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs); $readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);
...@@ -129,6 +131,10 @@ module mclt_test_01 (); ...@@ -129,6 +131,10 @@ module mclt_test_01 ();
java_dtt_out['h000 + i] = java_dtt_out0[i]; java_dtt_out['h000 + i] = java_dtt_out0[i];
end end
$readmemh("input_data/clt_dtt_rot_00_2_x1489_y951.dat",java_dtt_rot0);
for (i=0; i<256; i=i+1) begin
java_dtt_rot['h000 + i] = java_dtt_rot0[i];
end
$readmemh("input_data/tile_02.dat",tile_shift); $readmemh("input_data/tile_02.dat",tile_shift);
shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
...@@ -360,7 +366,8 @@ module mclt_test_01 (); ...@@ -360,7 +366,8 @@ module mclt_test_01 ();
integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data; wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2]; // wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[0],cntr6[1],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n6 = 0; n6 < 4; n6 = n6+1) begin for (n6 = 0; n6 < 4; n6 = n6+1) begin
......
dsp/phase_rotator.v
View file @ d3f2d87c
...@@ -43,7 +43,8 @@ module phase_rotator#( ...@@ -43,7 +43,8 @@ module phase_rotator#(
parameter SHIFT_WIDTH = 7, // x/y subpixel shift, signed -0.5<=shift<0.5 parameter SHIFT_WIDTH = 7, // x/y subpixel shift, signed -0.5<=shift<0.5
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25, parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48 parameter DSP_P_WIDTH = 48,
parameter COEFF_WIDTH = 17 // = DSP_B_WIDTH - 1 or positive numbers,
)( )(
input clk, //!< system clock, posedge input clk, //!< system clock, posedge
input rst, //!< sync reset input rst, //!< sync reset
...@@ -89,7 +90,7 @@ module phase_rotator#( ...@@ -89,7 +90,7 @@ module phase_rotator#(
reg [SHIFT_WIDTH-1:0] shift_v0; reg [SHIFT_WIDTH-1:0] shift_v0;
reg [SHIFT_WIDTH-1:0] shift_vr; reg [SHIFT_WIDTH-1:0] shift_vr;
reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux; reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux;
reg sign_cs; // sign for cos / sin, feed to DSP reg [5:0] sign_cs; // sign for cos / sin, feed to DSP
wire sign_cs_d; // sign_cs delayed by 3 clocks wire sign_cs_d; // sign_cs delayed by 3 clocks
reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks
reg [SHIFT_WIDTH-2:0] rom_a_shift; // ~shift absolute value reg [SHIFT_WIDTH-2:0] rom_a_shift; // ~shift absolute value
...@@ -99,7 +100,7 @@ module phase_rotator#( ...@@ -99,7 +100,7 @@ module phase_rotator#(
wire shift_ends_0 = shift_hv[SHIFT_WIDTH-2:0] == 0; wire shift_ends_0 = shift_hv[SHIFT_WIDTH-2:0] == 0;
reg [2:0] rom_re_regen; reg [2:0] rom_re_regen;
wire signed [DSP_B_WIDTH-1:0] cos_sin_w; wire signed [DSP_B_WIDTH-1:0] cos_sin_w;
wire mux_v = run_v && cntr_v[1]; wire mux_v = cntr_v[1]; // && run_v; // removed for debugging to see 'x'
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst) start_d <= 0; if (rst) start_d <= 0;
...@@ -131,7 +132,8 @@ module phase_rotator#( ...@@ -131,7 +132,8 @@ module phase_rotator#(
rom_a_shift <= shift_hv[SHIFT_WIDTH-1] ? -shift_hv[SHIFT_WIDTH-2:0] : shift_hv[SHIFT_WIDTH-2:0]; rom_a_shift <= shift_hv[SHIFT_WIDTH-1] ? -shift_hv[SHIFT_WIDTH-2:0] : shift_hv[SHIFT_WIDTH-2:0];
rom_a_sin <= shift_ends_0 ? shift_hv[SHIFT_WIDTH-1] : hv_sin; rom_a_sin <= shift_ends_0 ? shift_hv[SHIFT_WIDTH-1] : hv_sin;
// sign_cs <= shift_hv[SHIFT_WIDTH-1] & ( hv_sin | (shift_ends_0 & hv_index[2])); // sign_cs <= shift_hv[SHIFT_WIDTH-1] & ( hv_sin | (shift_ends_0 & hv_index[2]));
sign_cs <= shift_hv[SHIFT_WIDTH-1] & hv_sin; // sign_cs <= shift_hv[SHIFT_WIDTH-1] & hv_sin;
sign_cs <= {sign_cs[4:0], shift_hv[SHIFT_WIDTH-1] & hv_sin};
rom_re_regen <= {rom_re_regen[1:0],run_hv}; rom_re_regen <= {rom_re_regen[1:0],run_hv};
...@@ -157,7 +159,7 @@ module phase_rotator#( ...@@ -157,7 +159,7 @@ module phase_rotator#(
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h2), // input[3:0] .dly (4'h2), // input[3:0]
.din (sign_cs), // input[0:0] .din (sign_cs[0]), // input[0:0]
.dout (sign_cs_d) // output[0:0] .dout (sign_cs_d) // output[0:0]
); );
...@@ -168,7 +170,7 @@ module phase_rotator#( ...@@ -168,7 +170,7 @@ module phase_rotator#(
.LOG2WIDTH_A(4), .LOG2WIDTH_A(4),
.LOG2WIDTH_B(4) .LOG2WIDTH_B(4)
`ifdef PRELOAD_BRAMS `ifdef PRELOAD_BRAMS
`include "mclt_fold_rom.vh" // TODO: put real! `include "mclt_rotator_rom.vh"
`endif `endif
) i_mclt_rot_rom ( ) i_mclt_rot_rom (
...@@ -192,8 +194,8 @@ module phase_rotator#( ...@@ -192,8 +194,8 @@ module phase_rotator#(
reg ceb1_1, ceb1_2, ceb1_3, ceb1_4; reg ceb1_1, ceb1_2, ceb1_3, ceb1_4;
reg ceb2_1, ceb2_2, ceb2_3, ceb2_4; reg ceb2_1, ceb2_2, ceb2_3, ceb2_4;
reg selb_1, selb_2, selb_3, selb_4; reg selb_1, selb_2, selb_3, selb_4;
wire signed [DSP_A_WIDTH-1:0] ain_34 = pout_1[DSP_P_WIDTH-1 -: FD_WIDTH]; // bit select from pout_1 wire signed [DSP_A_WIDTH-1:0] ain_34 = pout_1[COEFF_WIDTH +: DSP_A_WIDTH]; // bit select from pout_1
wire signed [DSP_A_WIDTH-1:0] din_34 = pout_2[DSP_P_WIDTH-1 -: FD_WIDTH]; // bit select from pout_1 wire signed [DSP_A_WIDTH-1:0] din_34 = pout_2[COEFF_WIDTH +: DSP_A_WIDTH]; // bit select from pout_1
reg cea1_1, cea1_2, cea1_3, cea1_4; reg cea1_1, cea1_2, cea1_3, cea1_4;
reg cea2_1, cea2_2, ced_3, ced_4; reg cea2_1, cea2_2, ced_3, ced_4;
reg sela_1, sela_2, end_3, end_4; reg sela_1, sela_2, end_3, end_4;
...@@ -210,7 +212,8 @@ module phase_rotator#( ...@@ -210,7 +212,8 @@ module phase_rotator#(
always @(posedge clk) begin always @(posedge clk) begin
if (rst) ph <= 0; if (rst) ph <= 0;
else ph <= {ph[15:0], run_h & ~cntr_h[0] & cntr_h[1]}; // else ph <= {ph[15:0], run_h & ~cntr_h[0] & cntr_h[1]};
else ph <= {ph[15:0], run_h & ~cntr_h[0] & ~cntr_h[1]};
cea1_1 <= ph[0]; cea2_1 <= ph[2]; cea1_2 <= ph[1]; cea2_2 <= ph[3]; cea1_1 <= ph[0]; cea2_1 <= ph[2]; cea1_2 <= ph[1]; cea2_2 <= ph[3];
ceb1_1 <= ph[3]; ceb2_1 <= ph[2]; ceb1_2 <= ph[2] | ph[3]; ceb2_2 <= ph[3]; ceb1_1 <= ph[3]; ceb2_1 <= ph[2]; ceb1_2 <= ph[2] | ph[3]; ceb2_2 <= ph[3];
cead_1 <= |ph[5:2]; cead_2 <= |ph[6:3]; cead_1 <= |ph[5:2]; cead_2 <= |ph[6:3];
...@@ -218,8 +221,12 @@ module phase_rotator#( ...@@ -218,8 +221,12 @@ module phase_rotator#(
sela_1 <= ph[2] | ph[4]; sela_2 <= ph[3] | ph[5]; sela_1 <= ph[2] | ph[4]; sela_2 <= ph[3] | ph[5];
selb_1 <= ph[2] | ph[5]; selb_2 <= ph[3] | ph[6]; selb_1 <= ph[2] | ph[5]; selb_2 <= ph[3] | ph[6];
// 0 1 0 0 // 0 1 0 0
negm_1 <= (ph[3] ^ sign_cs_d) | (~ph[4] ^ sign_cs_d) | (ph[5] ^ sign_cs_r[1]) | (ph[6] ^ sign_cs_r[1]); // negm_1 <= (ph[3] ^ sign_cs_d) | (~ph[4] ^ sign_cs_d) | (ph[5] ^ sign_cs_r[1]) | (ph[6] ^ sign_cs_r[1]);
negm_2 <= (ph[4] ^ sign_cs_d) | (~ph[5] ^ sign_cs_d) | (ph[6] ^ sign_cs_r[1]) | (ph[7] ^ sign_cs_r[1]); // negm_2 <= (ph[4] ^ sign_cs_d) | (~ph[5] ^ sign_cs_d) | (ph[6] ^ sign_cs_r[1]) | (ph[7] ^ sign_cs_r[1]);
/// negm_1 <= (ph[4] & ~sign_cs[0]) | (ph[5] & sign_cs[1]);
/// negm_2 <= (ph[5] & ~sign_cs[1]) | (ph[6] & sign_cs[2]);
negm_1 <= (ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3]);
negm_2 <= (ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4]);
accum_1 <= ph[4] | ph[6]; accum_2 <= ph[5] | ph[7]; accum_1 <= ph[4] | ph[6]; accum_2 <= ph[5] | ph[7];
// vertical shift DSPs // vertical shift DSPs
...@@ -230,16 +237,22 @@ module phase_rotator#( ...@@ -230,16 +237,22 @@ module phase_rotator#(
end_3 <= ph[10] | ph[8]; end_4 <= ph[11] | ph[9]; end_3 <= ph[10] | ph[8]; end_4 <= ph[11] | ph[9];
selb_3 <= ph[8] | ph[11]; selb_4 <= ph[9] | ph[12]; selb_3 <= ph[8] | ph[11]; selb_4 <= ph[9] | ph[12];
negm_4 <= (ph[ 9] ^ sign_cs_d) | (~ph[10] ^ sign_cs_d) | (ph[11] ^ sign_cs_r[1]) | (ph[12] ^ sign_cs_r[1]); // negm_4 <= (ph[ 9] ^ sign_cs_d) | (~ph[10] ^ sign_cs_d) | (ph[11] ^ sign_cs_r[1]) | (ph[12] ^ sign_cs_r[1]);
negm_3 <= (ph[10] ^ sign_cs_d) | (~ph[11] ^ sign_cs_d) | (ph[12] ^ sign_cs_r[1]) | (ph[13] ^ sign_cs_r[1]); // negm_3 <= (ph[10] ^ sign_cs_d) | (~ph[11] ^ sign_cs_d) | (ph[12] ^ sign_cs_r[1]) | (ph[13] ^ sign_cs_r[1]);
/// negm_3 <= (ph[10] & ~sign_cs[0]) | (ph[11] & sign_cs[1]);
/// negm_4 <= (ph[11] & ~sign_cs[1]) | (ph[12] & sign_cs[2]);
negm_3 <= (ph[10] & ~sign_cs[2]) | (ph[11] & sign_cs[3]);
negm_4 <= (ph[11] & ~sign_cs[3]) | (ph[12] & sign_cs[4]);
accum_3 <= ph[10] | ph[12]; accum_4 <= ph[11] | ph[13]; accum_3 <= ph[10] | ph[12]; accum_4 <= ph[11] | ph[13];
omux_sel <= ph[13] | ph[15]; omux_sel <= ph[13] | ph[15];
fd_dv <= pre_dv; fd_dv <= pre_dv;
if (pre_dv) fd_out <= omux_sel ? pout_4[DSP_P_WIDTH-1 -: FD_WIDTH] : pout_3[DSP_P_WIDTH-1 -: FD_WIDTH]; if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH];
// pre_first_out <= ph[12];
pre_first_out <= cntr_h[7:0] == 8'hf;
pre_first_out <= ph[12];
end end
/* /*
...@@ -251,9 +264,7 @@ module phase_rotator#( ...@@ -251,9 +264,7 @@ module phase_rotator#(
dsp_ma_preadd #( dsp_ma_preadd #(
.B_WIDTH(DSP_B_WIDTH), .B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH), .A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH), .P_WIDTH(DSP_P_WIDTH)
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT")
) dsp_1_i ( ) dsp_1_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
...@@ -280,8 +291,7 @@ module phase_rotator#( ...@@ -280,8 +291,7 @@ module phase_rotator#(
.B_WIDTH(DSP_B_WIDTH), .B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH), .A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH), .P_WIDTH(DSP_P_WIDTH),
.A_INPUT("DIRECT"), .BREG (2)
.B_INPUT("CASCADE")
) dsp_2_i ( ) dsp_2_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
...@@ -309,9 +319,7 @@ module phase_rotator#( ...@@ -309,9 +319,7 @@ module phase_rotator#(
dsp_ma_preadd #( dsp_ma_preadd #(
.B_WIDTH(DSP_B_WIDTH), .B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH), .A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH), .P_WIDTH(DSP_P_WIDTH)
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT")
) dsp_3_i ( ) dsp_3_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
...@@ -338,8 +346,7 @@ module phase_rotator#( ...@@ -338,8 +346,7 @@ module phase_rotator#(
.B_WIDTH(DSP_B_WIDTH), .B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH), .A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH), .P_WIDTH(DSP_P_WIDTH),
.A_INPUT("DIRECT"), .BREG (2)
.B_INPUT("CASCADE")
) dsp_4_i ( ) dsp_4_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
......
input_data/clt_dtt_in_00_2_x1489_y951.dat
View file @ d3f2d87c
// DTT input range: -341.093520 ... 345.703701 // DTT input range: -341.093520 ... 345.703701
a6e42 bbecb b0d82 757e8 888a0 44f14 3df14 4f8f a6e2e bbeb3 b0d6b 757d9 8888f 44f0b 3df0d 4f8e
9bacb c2323 8292d 94604 3dd5c 7c9f2 928f 3da1f 9bab8 c230a 8291d 945f1 3dd54 7c9e3 928e 3da17
a737e 8f707 c33dd 4c6b3 9ea56 1fffa0a 7736b 1fb3813 a7369 8f6f5 c33c5 4c6a9 9ea42 1fffa0b 7735c 1fb381d
9aa38 c729a 53827 c82f8 3db4 9a8b6 1fc678d 6d045 9aa25 c7281 5381c c82df 3db3 9a8a3 1fc6794 6d038
9dde5 542e6 c29ad 72b8 a6d06 1fc51bf 95f2b 1f969fc 9ddd2 542dc c2995 72b7 a6cf1 1fc51c7 95f18 1f96a09
71fc8 a3d29 9586 b3172 1fb7b28 b1e4e 1f85a94 aac83 71fba a3d15 9585 b315b 1fb7b31 b1e38 1f85aa4 aac6e
5526c 1fe55b1 9908c 1face78 2b36b0 1f6ec1c a5ece 1f4982f 55262 1fe55b4 99079 1face82 2b365a 1f6ec2e a5eb9 1f49846
269b2 3bb9a 1f8177b ac042 1f778e6 ae96a 1f385d0 d69c9 269ad 3bb93 1f8178b ac02c 1f778f7 ae954 1f385e9 d69ae
1fe3382 1fd4a1c 1f965df 1fae322 1f6c881 1f78cdc 1f6c360 1f640e0 1fe3385 1fd4a22 1f965ed 1fae32c 1f6c893 1f78ced 1f6c373 1f640f4
3011b 1f8b460 1ff2381 1f81088 1fb1cb0 1f625f5 1f64e21 1f664ab 30115 1f8b46f 1ff2383 1f81098 1fb1cb9 1f62608 1f64e35 1f664be
1f90fae 2d78c 1f5d4f8 1feb1c2 1f5c6fb 1fac5db 1f640c5 1f6fa75 1f90fbc 2d786 1f5d50c 1feb1c5 1f5c70f 1fac5e5 1f640d8 1f6fa87
8338c 1f45b22 3b259 1f3b8e0 1feafb8 1f5f0f0 1fb07fe 1f80604 8337b 1f45b39 3b251 1f3b8f9 1feafbb 1f5f104 1fb0808 1f80614
1f4675f 80c13 1f2f275 3cb9b 1f5b248 1fe87dc 1f7abd1 1fb126f 1f46776 80c03 1f2f28f 3cb93 1f5b25c 1fe87df 1f7abe2 1fb1279
cb130 1f2435c 9b2ae 1f3ea65 35bcc 1f6751a 1fdc518 1f918a4 cb116 1f24377 9b29a 1f3ea7d 35bc5 1f6752d 1fdc51d 1f918b2
1f272bc 26fe2b 1f2bdb4 92266 1d55cd7 35f2e 1fad736 1fdba2d 1f272d7 26fddd 1f2bdcf 92254 1d55d2d 35f28 1fad740 1fdba31
11f686 1f257ae ff5bb 1f2ff73 7aecf 1f835ee 430ad 1fd9293 11f662 1f257ca ff59b 1f2ff8d 7aec0 1f835fe 430a5 1fd9297
1fe3382 2b5e4 1f965df 51cde 1f6c881 87324 1f6c360 9bf20 1fe3385 2b5de 1f965ed 51cd4 1f6c893 87313 1f6c373 9bf0c
1fcfee5 1f8b460 dc7f 1f81088 4e350 1f625f5 9b1df 1f664ab 1fcfeeb 1f8b46f dc7d 1f81098 4e347 1f62608 9b1cb 1f664be
1f90fae 1fd2874 1f5d4f8 14e3e 1f5c6fb 53a25 1f640c5 9058b 1f90fbc 1fd287a 1f5d50c 14e3b 1f5c70f 53a1b 1f640d8 90579
1f7cc74 1f45b22 1fc4da7 1f3b8e0 15048 1f5f0f0 4f802 1f80604 1f7cc85 1f45b39 1fc4daf 1f3b8f9 15045 1f5f104 4f7f8 1f80614
1f4675f 1f7f3ed 1f2f275 1fc3465 1f5b248 17824 1f7abd1 4ed91 1f46776 1f7f3fd 1f2f28f 1fc346d 1f5b25c 17821 1f7abe2 4ed87
1f34ed0 1f2435c 1f64d52 1f3ea65 1fca434 1f6751a 23ae8 1f918a4 1f34eea 1f24377 1f64d66 1f3ea7d 1fca43b 1f6752d 23ae3 1f918b2
1f272bc 1d901d5 1f2bdb4 1f6dd9a 1d55cd7 1fca0d2 1fad736 245d3 1f272d7 1d90223 1f2bdcf 1f6ddac 1d55d2d 1fca0d8 1fad740 245cf
1ee097a 1f257ae 1f00a45 1f2ff73 1f85131 1f835ee 1fbcf53 1fd9293 1ee099e 1f257ca 1f00a65 1f2ff8d 1f85140 1f835fe 1fbcf5b 1fd9297
a6e42 1f44135 b0d82 1f8a818 888a0 1fbb0ec 3df14 1ffb071 a6e2e 1f4414d b0d6b 1f8a827 8888f 1fbb0f5 3df0d 1ffb072
1f64535 c2323 1f7d6d3 94604 1fc22a4 7c9f2 1ff6d71 3da1f 1f64548 c230a 1f7d6e3 945f1 1fc22ac 7c9e3 1ff6d72 3da17
a737e 1f708f9 c33dd 1fb394d 9ea56 5f6 7736b 4c7ed a7369 1f7090b c33c5 1fb3957 9ea42 5f5 7735c 4c7e3
1f655c8 c729a 1fac7d9 c82f8 1ffc24c 9a8b6 39873 6d045 1f655db c7281 1fac7e4 c82df 1ffc24d 9a8a3 3986c 6d038
9dde5 1fabd1a c29ad 1ff8d48 a6d06 3ae41 95f2b 69604 9ddd2 1fabd24 c2995 1ff8d49 a6cf1 3ae39 95f18 695f7
1f8e038 a3d29 1ff6a7a b3172 484d8 b1e4e 7a56c aac83 1f8e046 a3d15 1ff6a7b b315b 484cf b1e38 7a55c aac6e
5526c 1aa4f 9908c 53188 2b36b0 913e4 a5ece b67d1 55262 1aa4c 99079 5317e 2b365a 913d2 a5eb9 b67ba
1fd964e 3bb9a 7e885 ac042 8871a ae96a c7a30 d69c9 1fd9653 3bb93 7e875 ac02c 88709 ae954 c7a17 d69ae
input_data/clt_dtt_out_00_2_x1489_y951.dat
View file @ d3f2d87c
// DTT output range: -549.382667 ... 423.390240 // DTT output range: -549.382667 ... 423.390240
315109 1f92301 43d55 1fd020f 261cf 17f0f 1fd00d1 3a887 3150d8 1f92308 43d51 1fd0212 261cc 17f0e 1fd00d4 3a883
1b63 347b7 1f915eb 641b8 1fc955f 1ff6884 4910b 1f8cc86 1b63 347b4 1f915f2 641b2 1fc9563 1ff6885 49107 1f8cc8d
1fef712 172eb 1fdefea 285a2 1fe2c41 1ff1075 1be6d 1fc58dd 1fef713 172e9 1fdefec 2859f 1fe2c43 1ff1076 1be6b 1fc58e0
157b0 1f8c318 91bdf 1f78f98 567f7 1fff60a 1fc0339 667f7 157ae 1f8c31f 91bd6 1f78fa1 567f1 1fff60a 1fc033d 667f0
1fec4c5 1feb531 1ffb84f 1ffd39b ee9a 1fec774 1cd99 1fda125 1fec4c6 1feb533 1ffb84f 1ffd39b ee99 1fec775 1cd97 1fda127
1fd6b26 4cb61 1f7fb9c 62f91 1fc4197 1ff1c11 48875 1f9c804 1fd6b29 4cb5c 1f7fba4 62f8b 1fc419b 1ff1c12 48870 1f9c80a
fe63 1fc82c8 50e22 1fd06d9 1b70d 1ffed35 1fd8c5f 6308f fe62 1fc82cc 50e1d 1fd06dc 1b70c 1ffed35 1fd8c61 63089
1d835 1fbe500 5e8ad 1fa35a2 23770 2d2a5 1f8631f 34ec7d 1d833 1fbe504 5e8a7 1fa35a8 2376e 2d2a2 1f86326 34ec48
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mclt_test_01.sav
View file @ d3f2d87c
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 19 16:58:00 2017 [*] Wed Dec 20 07:04:05 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171219005000376.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171219235955852.fst"
[dumpfile_mtime] "Tue Dec 19 07:50:02 2017" [dumpfile_mtime] "Wed Dec 20 06:59:58 2017"
[dumpfile_size] 1108642 [dumpfile_size] 1334335
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 4720000 [timestart] 5698200
[size] 1814 1171 [size] 1814 1171
[pos] 1923 0 [pos] 0 0
*-19.408367 7791000 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.519981 5777900 2715000 3535000 3355000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01. [treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i. [treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i. [treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i. [treeopen] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i. [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.
[sst_width] 285 [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.
[signals_width] 289 [treeopen] mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.
[sst_width] 204
[signals_width] 341
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 344 [sst_vpaned_height] 344
@800200 @800200
...@@ -144,6 +145,312 @@ mclt_test_01.diff6a ...@@ -144,6 +145,312 @@ mclt_test_01.diff6a
@1000200 @1000200
-top -top
@800200 @800200
-rotator
@c00200
-main
@28
mclt_test_01.mclt16x16_i.start
@22
mclt_test_01.mclt16x16_i.x_shft[6:0]
mclt_test_01.mclt16x16_i.x_shft_r[6:0]
mclt_test_01.mclt16x16_i.x_shft_r2[6:0]
mclt_test_01.mclt16x16_i.x_shft_r3[6:0]
mclt_test_01.mclt16x16_i.y_shft[6:0]
mclt_test_01.mclt16x16_i.y_shft_r[6:0]
mclt_test_01.mclt16x16_i.y_shft_r2[6:0]
mclt_test_01.mclt16x16_i.y_shft_r3[6:0]
@28
mclt_test_01.mclt16x16_i.start_dtt
mclt_test_01.mclt16x16_i.dtt_start_first_fill
mclt_test_01.mclt16x16_i.dtt_start_out
mclt_test_01.mclt16x16_i.pre_first_out
mclt_test_01.mclt16x16_i.dv
@c00022
mclt_test_01.mclt16x16_i.dout[24:0]
@28
(0)mclt_test_01.mclt16x16_i.dout[24:0]
(1)mclt_test_01.mclt16x16_i.dout[24:0]
(2)mclt_test_01.mclt16x16_i.dout[24:0]
(3)mclt_test_01.mclt16x16_i.dout[24:0]
(4)mclt_test_01.mclt16x16_i.dout[24:0]
(5)mclt_test_01.mclt16x16_i.dout[24:0]
(6)mclt_test_01.mclt16x16_i.dout[24:0]
(7)mclt_test_01.mclt16x16_i.dout[24:0]
(8)mclt_test_01.mclt16x16_i.dout[24:0]
(9)mclt_test_01.mclt16x16_i.dout[24:0]
(10)mclt_test_01.mclt16x16_i.dout[24:0]
(11)mclt_test_01.mclt16x16_i.dout[24:0]
(12)mclt_test_01.mclt16x16_i.dout[24:0]
(13)mclt_test_01.mclt16x16_i.dout[24:0]
(14)mclt_test_01.mclt16x16_i.dout[24:0]
(15)mclt_test_01.mclt16x16_i.dout[24:0]
(16)mclt_test_01.mclt16x16_i.dout[24:0]
(17)mclt_test_01.mclt16x16_i.dout[24:0]
(18)mclt_test_01.mclt16x16_i.dout[24:0]
(19)mclt_test_01.mclt16x16_i.dout[24:0]
(20)mclt_test_01.mclt16x16_i.dout[24:0]
(21)mclt_test_01.mclt16x16_i.dout[24:0]
(22)mclt_test_01.mclt16x16_i.dout[24:0]
(23)mclt_test_01.mclt16x16_i.dout[24:0]
(24)mclt_test_01.mclt16x16_i.dout[24:0]
@1401200
-group_end
@c08420
mclt_test_01.mclt16x16_i.dout[24:0]
@28
(0)mclt_test_01.mclt16x16_i.dout[24:0]
(1)mclt_test_01.mclt16x16_i.dout[24:0]
(2)mclt_test_01.mclt16x16_i.dout[24:0]
(3)mclt_test_01.mclt16x16_i.dout[24:0]
(4)mclt_test_01.mclt16x16_i.dout[24:0]
(5)mclt_test_01.mclt16x16_i.dout[24:0]
(6)mclt_test_01.mclt16x16_i.dout[24:0]
(7)mclt_test_01.mclt16x16_i.dout[24:0]
(8)mclt_test_01.mclt16x16_i.dout[24:0]
(9)mclt_test_01.mclt16x16_i.dout[24:0]
(10)mclt_test_01.mclt16x16_i.dout[24:0]
(11)mclt_test_01.mclt16x16_i.dout[24:0]
(12)mclt_test_01.mclt16x16_i.dout[24:0]
(13)mclt_test_01.mclt16x16_i.dout[24:0]
(14)mclt_test_01.mclt16x16_i.dout[24:0]
(15)mclt_test_01.mclt16x16_i.dout[24:0]
(16)mclt_test_01.mclt16x16_i.dout[24:0]
(17)mclt_test_01.mclt16x16_i.dout[24:0]
(18)mclt_test_01.mclt16x16_i.dout[24:0]
(19)mclt_test_01.mclt16x16_i.dout[24:0]
(20)mclt_test_01.mclt16x16_i.dout[24:0]
(21)mclt_test_01.mclt16x16_i.dout[24:0]
(22)mclt_test_01.mclt16x16_i.dout[24:0]
(23)mclt_test_01.mclt16x16_i.dout[24:0]
(24)mclt_test_01.mclt16x16_i.dout[24:0]
@1401200
-group_end
-main
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.start
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_din[24:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.start_d[5:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_h[6:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_hr[6:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.run_h
@c00022
mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
@28
(0)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(1)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(2)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(3)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(4)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(5)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(6)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
(7)mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_h[7:0]
@1401200
-group_end
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_v[6:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_v0[6:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_vr[6:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.run_v
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.cntr_v[7:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.run_hv
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.rom_a[9:0]
@c00028
mclt_test_01.mclt16x16_i.phase_rotator_i.rom_re_regen[2:0]
@28
(0)mclt_test_01.mclt16x16_i.phase_rotator_i.rom_re_regen[2:0]
(1)mclt_test_01.mclt16x16_i.phase_rotator_i.rom_re_regen[2:0]
(2)mclt_test_01.mclt16x16_i.phase_rotator_i.rom_re_regen[2:0]
@1401200
-group_end
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.rom_a_sin
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.rom_a_shift[5:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.rom_a_indx[2:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_hv[6:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_hr[6:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.mux_v
mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs_d
mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs_r[1:0]
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_1[47:0]
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.ain_34[24:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_2[47:0]
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.din_34[24:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_3[47:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_4[47:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_dv
@22
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_out[24:0]
@800200
-dsps
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_out[24:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.pre_first_out
mclt_test_01.mclt16x16_i.phase_rotator_i.fd_dv
@c00022
mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
@28
(0)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(1)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(2)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(3)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(4)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(5)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(6)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(7)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(8)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(9)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(10)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(11)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(12)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(13)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(14)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(15)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(16)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
@1401200
-group_end
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.cea1_1
mclt_test_01.mclt16x16_i.phase_rotator_i.cea2_1
mclt_test_01.mclt16x16_i.phase_rotator_i.sela_1
mclt_test_01.mclt16x16_i.phase_rotator_i.cead_1
@22
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.cos_sin_w[17:0]
@28
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb1_1
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb2_1
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.selb_1
(12)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(11)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.negm_1
mclt_test_01.mclt16x16_i.phase_rotator_i.accum_1
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_1[47:0]
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.ain_34[24:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.cea1_2
mclt_test_01.mclt16x16_i.phase_rotator_i.cea2_2
mclt_test_01.mclt16x16_i.phase_rotator_i.sela_2
mclt_test_01.mclt16x16_i.phase_rotator_i.cead_2
@22
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.cos_sin_w[17:0]
@28
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb1_2
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb2_2
[color] 2
mclt_test_01.mclt16x16_i.phase_rotator_i.selb_2
mclt_test_01.mclt16x16_i.phase_rotator_i.negm_2
mclt_test_01.mclt16x16_i.phase_rotator_i.accum_2
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_2[47:0]
[color] 6
mclt_test_01.mclt16x16_i.phase_rotator_i.din_34[24:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.cea1_3
mclt_test_01.mclt16x16_i.phase_rotator_i.ced_3
mclt_test_01.mclt16x16_i.phase_rotator_i.cead_3
@22
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.cos_sin_w[17:0]
@28
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb1_3
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb2_3
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.selb_3
mclt_test_01.mclt16x16_i.phase_rotator_i.hv_sin
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.shift_hv[6:0]
@800022
mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
@28
(0)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(1)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(2)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(3)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(4)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
(5)mclt_test_01.mclt16x16_i.phase_rotator_i.sign_cs[5:0]
@1001200
-group_end
@28
(6)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
(5)mclt_test_01.mclt16x16_i.phase_rotator_i.ph[16:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.negm_3
mclt_test_01.mclt16x16_i.phase_rotator_i.accum_3
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_3[47:0]
@200
-
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.cea1_4
mclt_test_01.mclt16x16_i.phase_rotator_i.ced_4
mclt_test_01.mclt16x16_i.phase_rotator_i.cead_4
@22
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.cos_sin_w[17:0]
@28
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb1_4
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.ceb2_4
[color] 3
mclt_test_01.mclt16x16_i.phase_rotator_i.selb_4
mclt_test_01.mclt16x16_i.phase_rotator_i.negm_4
mclt_test_01.mclt16x16_i.phase_rotator_i.accum_4
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.pout_4[47:0]
@c00200
-dsp2
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.ain[24:0]
@28
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.cea1
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.cea2
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.sela
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.cead
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.neg_m
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.accum
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.selb
@800200
-dsp48
@22
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.B[17:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.b_mult[17:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.qb_o_mux[17:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_01.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.qb_o_reg2[17:0]
@200
-
@1000200
-dsp48
@1401200
-dsp2
@1000200
-dsps
-rotator
@800200
-mclt16x16 -mclt16x16
@c00022 @c00022
mclt_test_01.mclt16x16_i.in_busy[16:0] mclt_test_01.mclt16x16_i.in_busy[16:0]
...@@ -597,7 +904,6 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.x_ra1h ...@@ -597,7 +904,6 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.x_ra1h
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_wa[7:0] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_wa[7:0]
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_di[24:0] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_di[24:0]
@28 @28
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.pre2_dsth[1:0]
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_out_start mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_out_start
@22 @22
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_rcntr[6:0] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.transpose_rcntr[6:0]
...@@ -617,7 +923,6 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.out_wa[3:0] ...@@ -617,7 +923,6 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.out_wa[3:0]
@22 @22
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.out_wd[24:0] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.out_wd[24:0]
@28 @28
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.pre2_dstv[1:0]
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.sub16 mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.sub16
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.inc16 mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.inc16
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.start_out mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.start_out
...@@ -705,7 +1010,7 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.dst_in ...@@ -705,7 +1010,7 @@ mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.dst_in
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.start mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.start
@22 @22
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.d_in[24:0] mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.d_in[24:0]
@29 @28
mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.pre2_start_out mclt_test_01.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_1_i.pre2_start_out
@200 @200
- -
......
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