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Commit d3767c2c authored by Andrey Filippov's avatar Andrey Filippov
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merged with parallel-sensors

parents 901020c6 dce5b57c
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.project
View file @ d3767c2c
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160329102811515.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160329103342970.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160406001856812.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160329102811515.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160329102811515.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -122,12 +122,12 @@
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20160405181335960.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160329102811515.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/org.eclipse.core.resources.prefs
View file @ d3767c2c
......@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
fpga_version.vh
View file @ d3767c2c
......@@ -32,7 +32,13 @@
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking
parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped
// parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
// parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF
// parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo
// parameter FPGA_VERSION = 32'h03930081; // re-started parallel - timing met
// parameter FPGA_VERSION = 32'h03930080; // serial, failed timing, >84%
// parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking
// parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met
// parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met
// parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly
......
includes/x393_parameters.vh
View file @ d3767c2c
......@@ -367,6 +367,10 @@
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......
py393/cargs 0 → 100644
View file @ d3767c2c
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-c export_all
\ No newline at end of file
py393/generate_c.sh 0 → 100755
View file @ d3767c2c
#!/bin/bash
# See x393_export_c.py
./test_mcntrl.py @cargs
\ No newline at end of file
py393/generated/x393.c deleted 100644 → 0
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py393/generated/x393_defs.h deleted 100644 → 0
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py393/generated/x393_map.h deleted 100644 → 0
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py393/generated/x393_types.h deleted 100644 → 0
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py393/init_jtag.sh 0 → 100755
View file @ d3767c2c
#!/bin/sh
#mkdir -p /lib/modules
#ln -sf /usr/local/lib /lib/modules/4.0.0-xilinx
#insmod /usr/local/lib/fpgajtag.ko
#mknod -m 0666 /dev/fjtag c 132 2
mknod -m 0666 /dev/fpgaresetjtag c 132 0
mknod -m 0666 /dev/jtagraw c 132 0
mknod -m 0666 /dev/fpgaconfjtag c 132 1
mknod -m 0666 /dev/sfpgaconfjtag c 132 2
mknod -m 0666 /dev/afpgaconfjtag c 132 3
#mknod -m 0666 /dev/fpgabscan c 132 5
#mknod -m 0666 /dev/sfpgabscan c 132 6
#mknod -m 0666 /dev/afpgabscan c 132 7
mknod -m 0666 /dev/sfpgaconfjtag0 c 132 8
mknod -m 0666 /dev/sfpgaconfjtag1 c 132 9
mknod -m 0666 /dev/sfpgaconfjtag2 c 132 10
mknod -m 0666 /dev/sfpgaconfjtag3 c 132 11
mknod -m 0666 /dev/sfpgabscan0 c 132 12
mknod -m 0666 /dev/sfpgabscan1 c 132 13
mknod -m 0666 /dev/sfpgabscan2 c 132 14
mknod -m 0666 /dev/sfpgabscan3 c 132 15
# @$(MKNOD) -m 0666 $(DEV)/fpgaresetjtag c 132 0
# @$(MKNOD) -m 0666 $(DEV)/jtagraw c 132 0
# @$(MKNOD) -m 0666 $(DEV)/fpgaconfjtag c 132 1
# @$(MKNOD) -m 0666 $(DEV)/sfpgaconfjtag c 132 2
# @$(MKNOD) -m 0666 $(DEV)/afpgaconfjtag c 132 3
# @$(MKNOD) -m 0666 $(DEV)/fpgabscan c 132 5
# @$(MKNOD) -m 0666 $(DEV)/sfpgabscan c 132 6
# @$(MKNOD) -m 0666 $(DEV)/afpgabscan c 132 7
py393/vrlg.py
View file @ d3767c2c
......@@ -263,6 +263,7 @@ SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL = int
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
......@@ -345,6 +346,7 @@ MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str
SENS_DIVCLK_DIVIDE = int
NEWPAR = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str
CMPRS_CONTROL_REG = int
GPIO_STATUS_REG_ADDR = int
......@@ -1393,6 +1395,7 @@ NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
MCONTR_PHY_16BIT_EXTRA__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
SENSI2C_CMD_SOFT_SCL__RAW = str
CMPRS_CSAT_CR__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
DLY_LANE1_IDELAY = long
......@@ -1582,6 +1585,7 @@ CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
HIST_SAXI_ADDR_REL__TYPE = str
......@@ -1629,6 +1633,7 @@ CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
......@@ -2040,6 +2045,7 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSI2C_CMD_SOFT_SDA__RAW = str
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
......
py393/x393_axi_control_status.py
View file @ d3767c2c
......@@ -274,7 +274,7 @@ class X393AxiControlStatus(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param pattern 26-bit pattern to match
@param mask 26-bit mask to enable pattern matching (0-s - ignore)
@param invert_match invert match (wait until matching condition becomes false)
......@@ -352,10 +352,10 @@ class X393AxiControlStatus(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
<seq_number> - 6-bit sequence number of the status message to be sent
"""
self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f))
self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number & 0x3f))
def program_status_all( self,
......@@ -367,7 +367,7 @@ class X393AxiControlStatus(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
......
py393/x393_cmprs.py
View file @ d3767c2c
......@@ -69,7 +69,7 @@ class X393Cmprs(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
......
py393/x393_export_c.py
View file @ d3767c2c
......@@ -107,7 +107,10 @@ class X393ExportC(object):
* Author: auto-generated file, see %s
* Description: %s
*******************************************************************************/"""
return header_template%(filename, datetime.date.today().isoformat(), os.path.basename(__file__), description)
script_name = os.path.basename(__file__)
if script_name[-1] == "c":
script_name = script_name[:-1]
return header_template%(filename, datetime.date.today().isoformat(), script_name, description)
def save_typedefs(self, directory, filename):
description = 'typedef definitions for the x393 hardware registers'
......@@ -125,7 +128,7 @@ class X393ExportC(object):
ld= self.define_macros()
ld+=self.define_other_macros()
# Includes section
txt = '\n#include "elphel/x393_types.h"\n'
txt = '\n#include "x393_types.h"\n'
txt +='//#include "elphel/x393_defs.h // alternative variant"\n\n'
txt +='// See elphel/x393_map.h for the ordered list of all I/O register addresses used\n'
txt += '// init_mmio_ptr() should be called once before using any of the other declared functions\n\n'
......@@ -385,7 +388,7 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
data = self._enc_sensio_jtag(),
name = "x393_sensio_jpag", typ="wo",
name = "x393_sensio_jtag", typ="wo",
frmt_spcs = frmt_spcs)
"""
stypedefs += self.get_typedef32(comment = "Sensor delays (uses 4 DWORDs)",
......@@ -754,7 +757,7 @@ class X393ExportC(object):
(("X393_SENS_SYNC_LATE", c, vrlg.SENS_SYNC_RADDR + vrlg.SENS_SYNC_LATE + ba, ia, z3, "x393_sens_sync_late", "wo", "Configure frame sync delay")),
(("X393_SENSIO_CTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL + ba, ia, z3, "x393_sensio_ctl", "wo", "Configure sensor I/O port")),
(("X393_SENSIO_STATUS_CNTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_STATUS + ba, ia, z3, "x393_status_ctrl", "rw", "Set status control for SENSIO module")),
(("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jpag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
(("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jtag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
(("X393_SENSIO_WIDTH", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_WIDTH + ba, ia, z3, "x393_sensio_width", "rw", "Set sensor line in pixels (0 - use line sync from the sensor)")),
# (("X393_SENSIO_DELAYS", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + ba, ia, z3, "x393_sensio_dly", "rw", "Sensor port input delays (uses 4 DWORDs)")),
(("X393_SENSIO_TIM0", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + 0 + ba, ia, z3, "x393_sensio_tim0", "rw", "Sensor port i/o timing configuration, register 0")),
......@@ -1681,7 +1684,7 @@ class X393ExportC(object):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data"))
dw.append(("i2c_fifo_cntrl", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)"))
dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)"))
dw.append(("busy", 10, 1,0, "I2C sequencer busy"))
dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update"))
dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number"))
......@@ -1717,7 +1720,7 @@ class X393ExportC(object):
def _enc_i2c_tbl_addr(self):
dw=[]
dw.append(("tbl_addr", 0, 8,0, "Address/length in 64-bit words (<<3 to get byte address)"))
dw.append(("tbl_addr", 0, 8,0, "I2C table index"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,3, "Should be 3 to select table address write mode"))
return dw
......@@ -1735,7 +1738,7 @@ class X393ExportC(object):
dw=[]
dw.append(("rah", vrlg.SENSI2C_TBL_RAH, vrlg.SENSI2C_TBL_RAH_BITS, 0, "High byte of the i2c register address"))
dw.append(("rnw", vrlg.SENSI2C_TBL_RNWREG, 1, 0, "Read/not write i2c register, should be 1 here"))
dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..18, 0 means '8')"))
dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..8, 0 means '8')"))
dw.append(("nabrd", vrlg.SENSI2C_TBL_NABRD, 1, 0, "Number of address bytes for read (0 - one byte, 1 - two bytes)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
......@@ -1747,6 +1750,10 @@ class X393ExportC(object):
dw.append(("sda_release", vrlg.SENSI2C_CMD_ACIVE_EARLY0, 1,0, "Release SDA early if next bit ==1 (valid with drive_ctl)"))
dw.append(("drive_ctl", vrlg.SENSI2C_CMD_ACIVE, 1,0, "0 - nop, 1 - set sda_release and sda_drive_high"))
dw.append(("next_fifo_rd", vrlg.SENSI2C_CMD_FIFO_RD, 1,0, "Advance I2C read FIFO pointer"))
dw.append(("soft_scl", vrlg.SENSI2C_CMD_SOFT_SCL, 2,0, "Control SCL pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("soft_sda", vrlg.SENSI2C_CMD_SOFT_SDA, 2,0, "Control SDA pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("cmd_run", vrlg.SENSI2C_CMD_RUN-1, 2,0, "Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run "))
dw.append(("reset", vrlg.SENSI2C_CMD_RESET, 1,0, "Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,0, "Should be 0 to select controls"))
......
py393/x393_gpio.py
View file @ d3767c2c
......@@ -66,7 +66,7 @@ class X393GPIO(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
......
py393/x393_jpeg.py
View file @ d3767c2c
......@@ -828,7 +828,7 @@ class X393Jpeg(object):
y_quality = y_quality, #80,
c_quality = c_quality,
portrait = portrait,
color_mode = window["cmode"], #
# color_mode = window["cmode"], #
byrshift = byrshift,
verbose = verbose)
html_text += html_text_finish
......@@ -965,6 +965,72 @@ class X393Jpeg(object):
ff d9
"""
"""
################## 10359 ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12"
measure_all "*DI"
program_status_sensor_io all 1 0
print_status_sensor_io all
setup_all_sensors True None 0x4
################## Parallel ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12"
measure_all "*DI"
setup_all_sensors True None 0xf
#set quadrants
set_sensor_io_ctl 0 None None None None None 0 0xe
set_sensor_io_ctl 1 None None None None None 0 0xe
#set_sensor_io_ctl 2 None None None None None 0 0x4
set_sensor_io_ctl 2 None None None None None 0 0xe
set_sensor_io_ctl 3 None None None None None 0 0xe
# Set Bayer = 3 (probably #1 and #3 need different hact/pxd delays to use the same compressor bayer for all channels)
compressor_control all None None None None None 3
#Get rid of the corrupted last pixel column
#longer line (default 0xa1f)
write_sensor_i2c all 1 0 0x90040a23
#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#Gamma 0.57
program_gamma all 0 0.57 0.04
#colors - outdoor
write_sensor_i2c all 1 0 0x9035000a
write_sensor_i2c all 1 0 0x902c000e
write_sensor_i2c all 1 0 0x902d000d
#colors indoor
write_sensor_i2c all 1 0 0x90350009
write_sensor_i2c all 1 0 0x902c000f
write_sensor_i2c all 1 0 0x902d000a
#exposure 0x100 lines (default was 0x797)
write_sensor_i2c all 1 0 0x90090100
#exposure 0x797 (default)
write_sensor_i2c all 1 0 0x90090797
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
#jpeg_write "img.jpeg" 0
jpeg_write "img.jpeg" All
#changing quality (example 85%):
set_qtables all 0 85
compressor_control all 2
#jpeg_write "img.jpeg" all 85
jpeg_write "img.jpeg" 0 85
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "HISPI"
measure_all "*DI"
......
py393/x393_mcntrl_adjust.py
View file @ d3767c2c
This diff is collapsed.
py393/x393_pio_sequences.py
View file @ d3767c2c
......@@ -1152,7 +1152,8 @@ class X393PIOSequences(object):
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
#calculate 1-s ratio for both lanes
rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1]
# rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1]
rslt=[0.0,0.0,0.0,0.0] # last 2 words - number of "problem" bytes that have non-ones in bits [7:1] or byte is not the same
for i in range(0,numBufWords):
rslt[i & 1] += ((buf[i] & 1) +
......@@ -1164,11 +1165,25 @@ class X393PIOSequences(object):
(0,1)[(buf[i] & 0xfe00) != 0]+
(0,1)[(buf[i] & 0xfe0000) != 0]+
(0,1)[(buf[i] & 0xfe000000) != 0])
bm = buf[i] & 0x01010101
bm |= (bm << 1)
bm |= (bm << 2)
bm |= (bm << 4)
bm ^= buf[i]
rslt[3] += ((0,1)[(bm & 0xfe) != 0]+
(0,1)[(bm & 0xfe00) != 0]+
(0,1)[(bm & 0xfe0000) != 0]+
(0,1)[(bm & 0xfe000000) != 0])
for i in range(2):
rslt[i]/=2*numBufWords
rslt[2]/=4*numBufWords
rslt[3]/=4*numBufWords
if quiet <1:
print ("WLEV lanes ratios: %f %f, non 0x00/0x01 bytes: %f"%(rslt[0],rslt[1],rslt[2]))
print ("WLEV lanes ratios: %f %f, non 0x00/0x01 byte: %f, non 0x00/0xffs: %f"%(rslt[0],rslt[1],rslt[2],rslt[3]))
if (rslt[3] < rslt[2]):
rslt[2] = rslt[3]
return rslt
def read_levelling(self,
......
py393/x393_rtc.py
View file @ d3767c2c
......@@ -67,7 +67,7 @@ class X393Rtc(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
......
py393/x393_sens_cmprs.py
View file @ d3767c2c
......@@ -188,11 +188,18 @@ class X393SensCmprs(object):
print(voltage_mv, file = f)
if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1)
time.sleep(0.1)
def setupSensorsPower(self, ifaceType, quiet=0):
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setupSensorsPower(self, ifaceType, pairs = "all", quiet=0):
try:
if (pairs == all) or (pairs[0].upper() == "A"): #all is a built-in function
pairs = (0,1)
except:
pass
if not isinstance(pairs,(list,tuple)):
pairs = (pairs,)
for pair in pairs:
self.setSensorIfaceVoltagePower(pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
"""
......@@ -208,16 +215,19 @@ class X393SensCmprs(object):
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
if quiet == 0:
print ("Turning on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
time.sleep(0.2)
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
time.sleep(0.2)
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
time.sleep(0.2)
# for sub_pair in (0,1):
# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
......@@ -1419,7 +1429,7 @@ class X393SensCmprs(object):
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
......
py393/x393_sensor.py
View file @ d3767c2c
This diff is collapsed.
sensor/sens_parallel12.v
View file @ d3767c2c
......@@ -190,7 +190,9 @@ module sens_parallel12 #(
wire [17:0] status;
// wire [17:0] status;
// wire [18:0] status;
wire [22:0] status;
wire cmd_we;
wire [2:0] cmd_a;
......@@ -228,7 +230,12 @@ module sens_parallel12 #(
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
// assign status = {pxd_out_pre[1],vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
// clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
// ps_rdy, ps_out, xfpgatdo, senspgmin};
assign status = {irst, async_prst_with_sens_mrst, imrst, rst_mmcm, pxd_out_pre[1],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r;
......@@ -414,14 +421,16 @@ module sens_parallel12 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
// .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH+1) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mclk_rst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
.status ({status_alive,status}), // input[25:0]
// .status ({status_alive,status}), // input[25:0]
.status ({status}), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......@@ -456,8 +465,27 @@ module sens_parallel12 #(
.ld_idelay (ld_idelay), // input
.quadrant (quadrants[1:0]) // input[1:0]
);
// debugging implementation
//assign xfpgatdo = pxd_out[1];
/* Instance template for module iobuf */
//`define DEBUF_JTAG 1
`ifdef DEBUF_JTAG
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) pxd_pxd1_i (
.O (pxd_out_pre[1]), // output
.IO (pxd[1]), // inout
.I (1'b0), // input
.T (1'b1) // input
);
assign xfpgatdo = pxd_out_pre[1];
`else
wire n_xfpgatdo;
assign xfpgatdo = !n_xfpgatdo;
pxd_single #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
......@@ -471,7 +499,7 @@ module sens_parallel12 #(
.pxd (pxd[1]), // inout
.pxd_out (1'b0), // input
.pxd_en (1'b0), // input
.pxd_async (xfpgatdo), // output
.pxd_async (n_xfpgatdo), // output
.pxd_in (pxd_out_pre[1]), // output
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
......@@ -483,6 +511,10 @@ module sens_parallel12 #(
.ld_idelay (ld_idelay), // input
.quadrant (quadrants[1:0]) // input[1:0]
);
`endif
// bits 2..11 are just PXD inputs, instance them all together
generate
genvar i;
......
sensor/sensor_channel.v
View file @ d3767c2c
......@@ -81,6 +81,8 @@ module sensor_channel#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......@@ -467,7 +469,10 @@ module sensor_channel#(
`ifdef DEBUG_RING
// reg vact_to_fifo_r;
`ifdef HISPI
`else
reg vact_to_fifo_r;
`endif
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
......@@ -611,6 +616,8 @@ module sensor_channel#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
......
sensor/sensor_i2c.v
View file @ d3767c2c
......@@ -48,7 +48,8 @@ module sensor_i2c#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......@@ -112,16 +113,7 @@ module sensor_i2c#(
wire wen;
wire [31:0] di;
wire [3:0] wa;
// wire busy; // busy (do not use software i2i)
// reg [4:0] wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
// reg [3:0] wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
// reg [3:0] wad;
reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
// reg [15:0] di_1;
// reg [15:0] di_2;
// reg [15:0] di_3;
reg [3:0] wpage0; // FIFO page where ASAP writes go
reg [3:0] wpage_prev; // unused page, currently being cleared
reg [3:0] page_r; // FIFO page where current i2c commands are taken from
......@@ -129,21 +121,15 @@ module sensor_i2c#(
reg [3:0] wpage_wr; // FIFO page where current write goes (reading from write address)
reg [1:0] wpage0_inc; // increment wpage0 (after frame sync or during reset)
reg reset_cmd;
// reg dly_cmd;
// reg bytes_cmd;
reg run_cmd;
reg twe;
reg active_cmd;
reg active_sda;
reg early_release_0;
reg reset_on; // reset FIFO in progress
// reg [1:0] i2c_bytes;
// reg [7:0] i2c_dly;
reg i2c_enrun; // enable i2c
reg we_fifo_wp; // enable writing to fifo write pointer memory
reg req_clr; // request for clearing fifo_wp (delay frame sync if previous is not yet sent out), also used for clearing all
// wire is_ctl= (wad[3:0]==4'hf);
// wire is_abs= (wad[3]==0);
wire pre_wpage0_inc; // ready to increment
wire [3:0] frame_num=wpage0[3:0];
......@@ -165,7 +151,6 @@ module sensor_i2c#(
reg i2c_start; // initiate i2c register write sequence
wire i2c_run; // i2c sequence is in progress (early end)
reg i2c_run_d; // i2c sequence is in progress (early end)
// wire i2c_busy; // i2c sequence is in progress (until bus is free and stop finished)
wire [1:0] byte_number; // byte number to send next (3-2-1-0)
wire [1:0] seq_mem_re;
wire [7:0] i2c_data;
......@@ -182,9 +167,17 @@ module sensor_i2c#(
wire set_status_w;
reg [1:0] wen_r;
// reg [1:0] wen_fifo;
reg wen_fifo; // [1] was not used - we_fifo_wp was used instead
reg scl_en_soft; // software i2c control signals (used when i2c controller is disabled)
reg scl_soft;
reg sda_en_soft;
reg sda_soft;
wire sda_hard;
wire sda_en_hard;
wire scl_hard;
assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
......@@ -196,7 +189,13 @@ module sensor_i2c#(
assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w?
assign scl_en = i2c_enrun;
// assign scl_en = i2c_enrun;
assign scl_out = i2c_enrun? scl_hard: scl_soft ;
assign scl_en = i2c_enrun? 1'b1: scl_en_soft ;
assign sda_out = i2c_enrun? sda_hard: sda_soft ;
assign sda_en = i2c_enrun? sda_en_hard: sda_en_soft ;
reg alive_fs;
......@@ -287,6 +286,16 @@ module sensor_i2c#(
if (reset_cmd || mrst) i2c_enrun <= 1'b0;
else if (run_cmd) i2c_enrun <= di_r[SENSI2C_CMD_RUN - 1 -: SENSI2C_CMD_RUN_PBITS]; // [12];
if (i2c_enrun || mrst) scl_en_soft <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_en_soft <= di[SENSI2C_CMD_SOFT_SCL +:2] != 3;
if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_soft <= di[SENSI2C_CMD_SOFT_SCL + 1];
if (i2c_enrun || mrst) sda_en_soft <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_en_soft <= di[SENSI2C_CMD_SOFT_SDA +:2] != 3;
if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_soft <= di[SENSI2C_CMD_SOFT_SDA + 1];
if (active_cmd) begin
early_release_0 <= di_r[SENSI2C_CMD_ACIVE_EARLY0];
active_sda <= di_r[SENSI2C_CMD_ACIVE_SDA];
......@@ -377,9 +386,9 @@ module sensor_i2c#(
.td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0]
.twe (twe), // input
.sda_in (sda_in), // input
.sda (sda_out), // output
.sda_en (sda_en), // output
.scl (scl_out), // output
.sda (sda_hard), // output
.sda_en (sda_en_hard), // output
.scl (scl_hard), // output
.i2c_run (i2c_run), // output reg
.i2c_busy (), //i2c_busy), // output reg
.seq_mem_ra (byte_number), // output[1:0] reg
......
sensor/sensor_i2c_io.v
View file @ d3767c2c
......@@ -48,7 +48,8 @@ module sensor_i2c_io#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......@@ -108,6 +109,8 @@ module sensor_i2c_io#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
......
sensor/sensors393.v
View file @ d3767c2c
......@@ -72,6 +72,8 @@ module sensors393 #(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......@@ -479,6 +481,8 @@ module sensors393 #(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0 (SENSI2C_CMD_ACIVE_EARLY0),
......
system_defines.vh
View file @ d3767c2c
......@@ -48,7 +48,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define HISPI
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
......
x393.bit
View file @ d3767c2c
No preview for this file type
x393_timing.tcl
View file @ d3767c2c
......@@ -55,25 +55,11 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
if ($HISPI) {
create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
} else {
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
}
create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
......@@ -84,11 +70,7 @@ if ($HISPI) {
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
} else {
create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
......@@ -102,16 +84,16 @@ if ($HISPI) {
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
......
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