Commit d3767c2c authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with parallel-sensors

parents 901020c6 dce5b57c
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+12 −12
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@@ -62,52 +62,52 @@
		<link>
			<name>vivado_logs/VivadoBitstream.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329103342970.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329103342970.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location>
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			<name>vivado_logs/VivadoOptPower.log</name>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329103342970.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location>
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@@ -122,12 +122,12 @@
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		</link>
	</linkedResources>
</projectDescription>
+2 −0
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@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
+7 −1
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@@ -32,7 +32,13 @@
 * with at least one of the Free Software programs.
 *******************************************************************************/
 
      parameter FPGA_VERSION =          32'h0393007f;    // More constraints files tweaking
      parameter FPGA_VERSION =          32'h03930085;    // Adding software control for i2c pins when sequencer is stopped
//      parameter FPGA_VERSION =          32'h03930084;    // Back to iserdes, inverting xfpgatdo - met
//      parameter FPGA_VERSION =          32'h03930083;    // Debugging JTAG, using plain IOBUF
//      parameter FPGA_VERSION =          32'h03930082;    // trying other path to read xfpgatdo
//      parameter FPGA_VERSION =          32'h03930081;    // re-started parallel - timing met
//      parameter FPGA_VERSION =          32'h03930080;    // serial, failed timing, >84%
//      parameter FPGA_VERSION =          32'h0393007f;    // More constraints files tweaking
//      parameter FPGA_VERSION =          32'h0393007e;    // Trying .tcl constraints instead of xdc - timing met
//      parameter FPGA_VERSION =          32'h0393007d;    // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met
//      parameter FPGA_VERSION =          32'h0393007c;    // fixed cmdseqmux - reporting interrupt status and mask correctly
+4 −0
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@@ -367,6 +367,10 @@
        parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
        parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
        parameter SENSI2C_CMD_RUN_PBITS =    1,
        
        parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
        parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
        
        parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1
        parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
        parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1

py393/cargs

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-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-c export_all
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