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Commit d3767c2c authored by Andrey Filippov's avatar Andrey Filippov
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merged with parallel-sensors

parents 901020c6 dce5b57c
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.project
View file @ d3767c2c
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160329103342970.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160329102811515.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
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<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160329102811515.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160329102811515.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
...@@ -122,12 +122,12 @@ ...@@ -122,12 +122,12 @@
<link> <link>
<name>vivado_state/x393-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20160405181335960.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160329102811515.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
.settings/org.eclipse.core.resources.prefs
View file @ d3767c2c
...@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8 ...@@ -3,3 +3,5 @@ encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8 encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8 encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8 encoding//py393/test_mcntrl.py=utf-8
encoding//py393/x393_i2c.py.test=utf-8
encoding//py393/x393_init_usb_hub.py=utf-8
fpga_version.vh
View file @ d3767c2c
...@@ -32,7 +32,13 @@ ...@@ -32,7 +32,13 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped
// parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
// parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF
// parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo
// parameter FPGA_VERSION = 32'h03930081; // re-started parallel - timing met
// parameter FPGA_VERSION = 32'h03930080; // serial, failed timing, >84%
// parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking
// parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met // parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met
// parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met // parameter FPGA_VERSION = 32'h0393007d; // Changing IMU logger LOGGER_PAGE_IMU 0-> 3 to avoid overlap with other registers. Timing met
// parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly // parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly
......
includes/x393_parameters.vh
View file @ d3767c2c
...@@ -367,6 +367,10 @@ ...@@ -367,6 +367,10 @@
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
......
py393/cargs 0 → 100644
View file @ d3767c2c
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-c export_all
\ No newline at end of file
py393/generate_c.sh 0 → 100755
View file @ d3767c2c
#!/bin/bash
# See x393_export_c.py
./test_mcntrl.py @cargs
\ No newline at end of file
py393/generated/x393.c deleted 100644 → 0
View file @ 901020c6
/*******************************************************************************
* File: x393.c
* Date: 2016-03-29
* Author: auto-generated file, see x393_export_c.py
* Description: Functions definitions to access x393 hardware registers
*******************************************************************************/
#include <linux/io.h>
#include "x393.h"
static void __iomem* mmio_ptr;
// init_mmio_ptr() should be called once before using any of the other defined functions
int init_mmio_ptr(void) {mmio_ptr = ioremap(0x40000000, 0x00003000); if (!mmio_ptr) return -1; else return 0;}
// R/W addresses to set up memory arbiter priorities. For sensors (chn = 8..11), for compressors - 12..15
void set_x393_mcntrl_arbiter_priority (x393_arbite_pri_t d, int chn){writel(d.d32, mmio_ptr + (0x0180 + 0x4 * chn));} // Set memory arbiter priority (currently r/w, may become just wo)
x393_arbite_pri_t get_x393_mcntrl_arbiter_priority (int chn) { x393_arbite_pri_t d; d.d32 = readl(mmio_ptr + (0x0180 + 0x4 * chn)); return d; }
// Enable/disable memory channels (bits in a 16-bit word). For sensors (chn = 8..11), for compressors - 12..15
void set_x393_mcntrl_chn_en (x393_mcntr_chn_en_t d){writel(d.d32, mmio_ptr + 0x01c0);} // Enable/disable memory channels (currently r/w, may become just wo)
x393_mcntr_chn_en_t get_x393_mcntrl_chn_en (void) { x393_mcntr_chn_en_t d; d.d32 = readl(mmio_ptr + 0x01c0); return d; }
void set_x393_mcntrl_dqs_dqm_patt (x393_mcntr_dqs_dqm_patt_t d){writel(d.d32, mmio_ptr + 0x0140);} // Setup DQS and DQM patterns
x393_mcntr_dqs_dqm_patt_t get_x393_mcntrl_dqs_dqm_patt (void) { x393_mcntr_dqs_dqm_patt_t d; d.d32 = readl(mmio_ptr + 0x0140); return d; }
void set_x393_mcntrl_dq_dqs_tri (x393_mcntr_dqs_dqm_tri_t d){writel(d.d32, mmio_ptr + 0x0144);} // Setup DQS and DQ on/off sequence
x393_mcntr_dqs_dqm_tri_t get_x393_mcntrl_dq_dqs_tri (void) { x393_mcntr_dqs_dqm_tri_t d; d.d32 = readl(mmio_ptr + 0x0144); return d; }
// Following enable/disable addresses can be written with any data, only addresses matter
void x393_mcntrl_dis (void) {writel(0, mmio_ptr + 0x00c0);} // Disable DDR3 memory controller
void x393_mcntrl_en (void) {writel(0, mmio_ptr + 0x00c4);} // Enable DDR3 memory controller
void x393_mcntrl_refresh_dis (void) {writel(0, mmio_ptr + 0x00c8);} // Disable DDR3 memory refresh
void x393_mcntrl_refresh_en (void) {writel(0, mmio_ptr + 0x00cc);} // Enable DDR3 memory refresh
void x393_mcntrl_sdrst_dis (void) {writel(0, mmio_ptr + 0x0098);} // Disable DDR3 memory reset
void x393_mcntrl_sdrst_en (void) {writel(0, mmio_ptr + 0x009c);} // Enable DDR3 memory reset
void x393_mcntrl_cke_dis (void) {writel(0, mmio_ptr + 0x00a0);} // Disable DDR3 memory CKE
void x393_mcntrl_cke_en (void) {writel(0, mmio_ptr + 0x00a4);} // Enable DDR3 memory CKE
void x393_mcntrl_cmda_dis (void) {writel(0, mmio_ptr + 0x0090);} // Disable DDR3 memory command/address lines
void x393_mcntrl_cmda_en (void) {writel(0, mmio_ptr + 0x0094);} // Enable DDR3 memory command/address lines
// Set DDR3 memory controller I/O delays and other timing parameters (should use individually calibrated values)
void set_x393_mcntrl_dq_odly0 (x393_dly_t d, int chn){writel(d.d32, mmio_ptr + (0x0200 + 0x4 * chn));} // Lane0 DQ output delays
x393_dly_t get_x393_mcntrl_dq_odly0 (int chn) { x393_dly_t d; d.d32 = readl(mmio_ptr + (0x0200 + 0x4 * chn)); return d; }
void set_x393_mcntrl_dq_odly1 (x393_dly_t d, int chn){writel(d.d32, mmio_ptr + (0x0280 + 0x4 * chn));} // Lane1 DQ output delays
x393_dly_t get_x393_mcntrl_dq_odly1 (int chn) { x393_dly_t d; d.d32 = readl(mmio_ptr + (0x0280 + 0x4 * chn)); return d; }
void set_x393_mcntrl_dq_idly0 (x393_dly_t d, int chn){writel(d.d32, mmio_ptr + (0x0240 + 0x4 * chn));} // Lane0 DQ input delays
x393_dly_t get_x393_mcntrl_dq_idly0 (int chn) { x393_dly_t d; d.d32 = readl(mmio_ptr + (0x0240 + 0x4 * chn)); return d; }
void set_x393_mcntrl_dq_idly1 (x393_dly_t d, int chn){writel(d.d32, mmio_ptr + (0x02c0 + 0x4 * chn));} // Lane1 DQ input delays
x393_dly_t get_x393_mcntrl_dq_idly1 (int chn) { x393_dly_t d; d.d32 = readl(mmio_ptr + (0x02c0 + 0x4 * chn)); return d; }
void set_x393_mcntrl_dqs_odly0 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x0220);} // Lane0 DQS output delay
x393_dly_t get_x393_mcntrl_dqs_odly0 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x0220); return d; }
void set_x393_mcntrl_dqs_odly1 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x02a0);} // Lane1 DQS output delay
x393_dly_t get_x393_mcntrl_dqs_odly1 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x02a0); return d; }
void set_x393_mcntrl_dqs_idly0 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x0260);} // Lane0 DQS input delay
x393_dly_t get_x393_mcntrl_dqs_idly0 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x0260); return d; }
void set_x393_mcntrl_dqs_idly1 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x02e0);} // Lane1 DQS input delay
x393_dly_t get_x393_mcntrl_dqs_idly1 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x02e0); return d; }
void set_x393_mcntrl_dm_odly0 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x0224);} // Lane0 DM output delay
x393_dly_t get_x393_mcntrl_dm_odly0 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x0224); return d; }
void set_x393_mcntrl_dm_odly1 (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x02a4);} // Lane1 DM output delay
x393_dly_t get_x393_mcntrl_dm_odly1 (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x02a4); return d; }
void set_x393_mcntrl_cmda_odly (x393_dly_t d, int chn){writel(d.d32, mmio_ptr + (0x0300 + 0x4 * chn));} // Address, bank and commands delays
x393_dly_t get_x393_mcntrl_cmda_odly (int chn) { x393_dly_t d; d.d32 = readl(mmio_ptr + (0x0300 + 0x4 * chn)); return d; }
void set_x393_mcntrl_phase (x393_dly_t d) {writel(d.d32, mmio_ptr + 0x0380);} // Clock phase
x393_dly_t get_x393_mcntrl_phase (void) { x393_dly_t d; d.d32 = readl(mmio_ptr + 0x0380); return d; }
void x393_mcntrl_dly_set (void) {writel(0, mmio_ptr + 0x0080);} // Set all pre-programmed delays
void set_x393_mcntrl_wbuf_dly (x393_wbuf_dly_t d) {writel(d.d32, mmio_ptr + 0x0148);} // Set write buffer delay
x393_wbuf_dly_t get_x393_mcntrl_wbuf_dly (void) { x393_wbuf_dly_t d; d.d32 = readl(mmio_ptr + 0x0148); return d; }
// Write-only addresses to program memory channels for sensors (chn = 0..3), memory channels 8..11
void x393_sens_mcntrl_scanline_mode (x393_mcntrl_mode_scan_t d, int chn){writel(d.d32, mmio_ptr + (0x1a00 + 0x40 * chn));} // Set mode register (write last after other channel registers are set)
void set_x393_sens_mcntrl_scanline_status_cntrl(x393_status_ctrl_t d, int chn){writel(d.d32, mmio_ptr + (0x1a04 + 0x40 * chn));} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_sens_mcntrl_scanline_status_cntrl(int chn) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + (0x1a04 + 0x40 * chn)); return d; }
void x393_sens_mcntrl_scanline_startaddr (x393_mcntrl_window_frame_sa_t d, int chn){writel(d.d32, mmio_ptr + (0x1a08 + 0x40 * chn));} // Set frame start address
void x393_sens_mcntrl_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_t d, int chn){writel(d.d32, mmio_ptr + (0x1a0c + 0x40 * chn));} // Set frame size (address increment)
void x393_sens_mcntrl_scanline_frame_last(x393_mcntrl_window_last_frame_num_t d, int chn){writel(d.d32, mmio_ptr + (0x1a10 + 0x40 * chn));} // Set last frame number (number of frames in buffer minus 1)
void x393_sens_mcntrl_scanline_frame_full_width(x393_mcntrl_window_full_width_t d, int chn){writel(d.d32, mmio_ptr + (0x1a14 + 0x40 * chn));} // Set frame full(padded) width
void x393_sens_mcntrl_scanline_window_wh (x393_mcntrl_window_width_height_t d, int chn){writel(d.d32, mmio_ptr + (0x1a18 + 0x40 * chn));} // Set frame window size
void x393_sens_mcntrl_scanline_window_x0y0(x393_mcntrl_window_left_top_t d, int chn){writel(d.d32, mmio_ptr + (0x1a1c + 0x40 * chn));} // Set frame position
void x393_sens_mcntrl_scanline_startxy (x393_mcntrl_window_startx_starty_t d, int chn){writel(d.d32, mmio_ptr + (0x1a20 + 0x40 * chn));} // Set startXY register
// Write-only addresses to program memory channels for compressors (chn = 0..3), memory channels 12..15
void x393_sens_mcntrl_tiled_mode (x393_mcntrl_mode_scan_t d, int chn){writel(d.d32, mmio_ptr + (0x1b00 + 0x40 * chn));} // Set mode register (write last after other channel registers are set)
void set_x393_sens_mcntrl_tiled_status_cntrl(x393_status_ctrl_t d, int chn){writel(d.d32, mmio_ptr + (0x1b04 + 0x40 * chn));} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_sens_mcntrl_tiled_status_cntrl(int chn) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + (0x1b04 + 0x40 * chn)); return d; }
void x393_sens_mcntrl_tiled_startaddr (x393_mcntrl_window_frame_sa_t d, int chn){writel(d.d32, mmio_ptr + (0x1b08 + 0x40 * chn));} // Set frame start address
void x393_sens_mcntrl_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d, int chn){writel(d.d32, mmio_ptr + (0x1b0c + 0x40 * chn));} // Set frame size (address increment)
void x393_sens_mcntrl_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d, int chn){writel(d.d32, mmio_ptr + (0x1b10 + 0x40 * chn));} // Set last frame number (number of frames in buffer minus 1)
void x393_sens_mcntrl_tiled_frame_full_width(x393_mcntrl_window_full_width_t d, int chn){writel(d.d32, mmio_ptr + (0x1b14 + 0x40 * chn));} // Set frame full(padded) width
void x393_sens_mcntrl_tiled_window_wh (x393_mcntrl_window_width_height_t d, int chn){writel(d.d32, mmio_ptr + (0x1b18 + 0x40 * chn));} // Set frame window size
void x393_sens_mcntrl_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d, int chn){writel(d.d32, mmio_ptr + (0x1b1c + 0x40 * chn));} // Set frame position
void x393_sens_mcntrl_tiled_startxy (x393_mcntrl_window_startx_starty_t d, int chn){writel(d.d32, mmio_ptr + (0x1b20 + 0x40 * chn));} // Set startXY register
void x393_sens_mcntrl_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d, int chn){writel(d.d32, mmio_ptr + (0x1b24 + 0x40 * chn));} // Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel for membridge, memory channel 1
void x393_membridge_scanline_mode (x393_mcntrl_mode_scan_t d){writel(d.d32, mmio_ptr + 0x0480);} // Set mode register (write last after other channel registers are set)
void set_x393_membridge_scanline_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0484);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_membridge_scanline_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0484); return d; }
void x393_membridge_scanline_startaddr (x393_mcntrl_window_frame_sa_t d){writel(d.d32, mmio_ptr + 0x0488);} // Set frame start address
void x393_membridge_scanline_frame_size (x393_mcntrl_window_frame_sa_inc_t d){writel(d.d32, mmio_ptr + 0x048c);} // Set frame size (address increment)
void x393_membridge_scanline_frame_last (x393_mcntrl_window_last_frame_num_t d){writel(d.d32, mmio_ptr + 0x0490);} // Set last frame number (number of frames in buffer minus 1)
void x393_membridge_scanline_frame_full_width(x393_mcntrl_window_full_width_t d){writel(d.d32, mmio_ptr + 0x0494);} // Set frame full(padded) width
void x393_membridge_scanline_window_wh (x393_mcntrl_window_width_height_t d){writel(d.d32, mmio_ptr + 0x0498);} // Set frame window size
void x393_membridge_scanline_window_x0y0 (x393_mcntrl_window_left_top_t d){writel(d.d32, mmio_ptr + 0x049c);} // Set frame position
void x393_membridge_scanline_startxy (x393_mcntrl_window_startx_starty_t d){writel(d.d32, mmio_ptr + 0x04a0);} // Set startXY register
void x393_membridge_ctrl (x393_membridge_cmd_t d){writel(d.d32, mmio_ptr + 0x0800);} // Issue membridge command
void set_x393_membridge_status_cntrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0804);} // Set membridge status control register
x393_status_ctrl_t get_x393_membridge_status_cntrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0804); return d; }
void x393_membridge_lo_addr64 (u29_t d) {writel(d.d32, mmio_ptr + 0x0808);} // start address of the system memory range in QWORDs (4 LSBs==0)
void x393_membridge_size64 (u29_t d) {writel(d.d32, mmio_ptr + 0x080c);} // size of the system memory range in QWORDs (4 LSBs==0), rolls over
void x393_membridge_start64 (u29_t d) {writel(d.d32, mmio_ptr + 0x0810);} // start of transfer offset to system memory range in QWORDs (4 LSBs==0)
void x393_membridge_len64 (u29_t d) {writel(d.d32, mmio_ptr + 0x0814);} // Full length of transfer in QWORDs
void x393_membridge_width64 (u29_t d) {writel(d.d32, mmio_ptr + 0x0818);} // Frame width in QWORDs (last xfer in each line may be partial)
void x393_membridge_mode (x393_membridge_mode_t d){writel(d.d32, mmio_ptr + 0x081c);} // AXI cache mode
// Write-only addresses to PS PIO (Software generated DDR3 memory access sequences)
void x393_mcntrl_ps_en_rst (x393_ps_pio_en_rst_t d){writel(d.d32, mmio_ptr + 0x0400);} // Set PS PIO enable and reset
void x393_mcntrl_ps_cmd (x393_ps_pio_cmd_t d){writel(d.d32, mmio_ptr + 0x0404);} // Set PS PIO commands
void set_x393_mcntrl_ps_status_cntrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0408);} // Set PS PIO status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_ps_status_cntrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0408); return d; }
// Write-only addresses to to program status report mode for memory controller
void set_x393_mcontr_phy_status_cntrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0150);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcontr_phy_status_cntrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0150); return d; }
void set_x393_mcontr_top_16bit_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x014c);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcontr_top_16bit_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x014c); return d; }
// Write-only addresses to to program status report mode for test channels
void set_x393_mcntrl_test01_chn2_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x03d4);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn2_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x03d4); return d; }
void set_x393_mcntrl_test01_chn3_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x03dc);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn3_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x03dc); return d; }
void set_x393_mcntrl_test01_chn4_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x03e4);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn4_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x03e4); return d; }
// Write-only addresses for test channels commands
void x393_mcntrl_test01_chn2_mode (x393_test01_mode_t d){writel(d.d32, mmio_ptr + 0x03d0);} // Set command for test01 channel 2
void x393_mcntrl_test01_chn3_mode (x393_test01_mode_t d){writel(d.d32, mmio_ptr + 0x03d8);} // Set command for test01 channel 3
void x393_mcntrl_test01_chn4_mode (x393_test01_mode_t d){writel(d.d32, mmio_ptr + 0x03e0);} // Set command for test01 channel 4
// Read-only addresses for status information
x393_status_mcntrl_phy_t x393_mcontr_phy_status (void) { x393_status_mcntrl_phy_t d; d.d32 = readl(mmio_ptr + 0x2000); return d; } // Status register for MCNTRL PHY
x393_status_mcntrl_top_t x393_mcontr_top_status (void) { x393_status_mcntrl_top_t d; d.d32 = readl(mmio_ptr + 0x2004); return d; } // Status register for MCNTRL requests
x393_status_mcntrl_ps_t x393_mcntrl_ps_status (void) { x393_status_mcntrl_ps_t d; d.d32 = readl(mmio_ptr + 0x2008); return d; } // Status register for MCNTRL software R/W
x393_status_mcntrl_lintile_t x393_mcntrl_chn1_status (void) { x393_status_mcntrl_lintile_t d; d.d32 = readl(mmio_ptr + 0x2010); return d; } // Status register for MCNTRL CHN1 (membridge)
x393_status_mcntrl_lintile_t x393_mcntrl_chn3_status (void) { x393_status_mcntrl_lintile_t d; d.d32 = readl(mmio_ptr + 0x2018); return d; } // Status register for MCNTRL CHN3 (scanline)
x393_status_mcntrl_lintile_t x393_mcntrl_chn2_status (void) { x393_status_mcntrl_lintile_t d; d.d32 = readl(mmio_ptr + 0x2014); return d; } // Status register for MCNTRL CHN2 (tiled)
x393_status_mcntrl_lintile_t x393_mcntrl_chn4_status (void) { x393_status_mcntrl_lintile_t d; d.d32 = readl(mmio_ptr + 0x201c); return d; } // Status register for MCNTRL CHN4 (tiled)
x393_status_mcntrl_testchn_t x393_test01_chn2_status (void) { x393_status_mcntrl_testchn_t d; d.d32 = readl(mmio_ptr + 0x20f4); return d; } // Status register for test channel 2
x393_status_mcntrl_testchn_t x393_test01_chn3_status (void) { x393_status_mcntrl_testchn_t d; d.d32 = readl(mmio_ptr + 0x20f8); return d; } // Status register for test channel 3
x393_status_mcntrl_testchn_t x393_test01_chn4_status (void) { x393_status_mcntrl_testchn_t d; d.d32 = readl(mmio_ptr + 0x20fc); return d; } // Status register for test channel 4
x393_status_membridge_t x393_membridge_status (void) { x393_status_membridge_t d; d.d32 = readl(mmio_ptr + 0x20ec); return d; } // Status register for membridge
// Write-only control of the sensor channels
void x393_sens_mode (x393_sens_mode_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1000 + 0x100 * sens_num));} // Write sensor channel mode
void x393_sensi2c_ctrl (x393_i2c_ctltbl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1008 + 0x100 * sens_num));} // Control sensor i2c, write i2c LUT
void set_x393_sensi2c_status_ctrl (x393_status_ctrl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x100c + 0x100 * sens_num));} // Setup sensor i2c status report mode
x393_status_ctrl_t get_x393_sensi2c_status_ctrl (int sens_num) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + (0x100c + 0x100 * sens_num)); return d; }
void x393_sens_sync_mult (x393_sens_sync_mult_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1018 + 0x100 * sens_num));} // Configure frames combining
void x393_sens_sync_late (x393_sens_sync_late_t d, int sens_num){writel(d.d32, mmio_ptr + (0x101c + 0x100 * sens_num));} // Configure frame sync delay
void x393_sensio_ctrl (x393_sensio_ctl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1020 + 0x100 * sens_num));} // Configure sensor I/O port
void set_x393_sensio_status_cntrl (x393_status_ctrl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1024 + 0x100 * sens_num));} // Set status control for SENSIO module
x393_status_ctrl_t get_x393_sensio_status_cntrl (int sens_num) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + (0x1024 + 0x100 * sens_num)); return d; }
void x393_sensio_jtag (x393_sensio_jpag_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1028 + 0x100 * sens_num));} // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)
void set_x393_sensio_width (x393_sensio_width_t d, int sens_num){writel(d.d32, mmio_ptr + (0x102c + 0x100 * sens_num));} // Set sensor line in pixels (0 - use line sync from the sensor)
x393_sensio_width_t get_x393_sensio_width (int sens_num) { x393_sensio_width_t d; d.d32 = readl(mmio_ptr + (0x102c + 0x100 * sens_num)); return d; }
void set_x393_sensio_tim0 (x393_sensio_tim0_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1030 + 0x100 * sens_num));} // Sensor port i/o timing configuration, register 0
x393_sensio_tim0_t get_x393_sensio_tim0 (int sens_num) { x393_sensio_tim0_t d; d.d32 = readl(mmio_ptr + (0x1030 + 0x100 * sens_num)); return d; }
void set_x393_sensio_tim1 (x393_sensio_tim1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1034 + 0x100 * sens_num));} // Sensor port i/o timing configuration, register 1
x393_sensio_tim1_t get_x393_sensio_tim1 (int sens_num) { x393_sensio_tim1_t d; d.d32 = readl(mmio_ptr + (0x1034 + 0x100 * sens_num)); return d; }
void set_x393_sensio_tim2 (x393_sensio_tim2_t d, int sens_num){writel(d.d32, mmio_ptr + (0x1038 + 0x100 * sens_num));} // Sensor port i/o timing configuration, register 2
x393_sensio_tim2_t get_x393_sensio_tim2 (int sens_num) { x393_sensio_tim2_t d; d.d32 = readl(mmio_ptr + (0x1038 + 0x100 * sens_num)); return d; }
void set_x393_sensio_tim3 (x393_sensio_tim3_t d, int sens_num){writel(d.d32, mmio_ptr + (0x103c + 0x100 * sens_num));} // Sensor port i/o timing configuration, register 3
x393_sensio_tim3_t get_x393_sensio_tim3 (int sens_num) { x393_sensio_tim3_t d; d.d32 = readl(mmio_ptr + (0x103c + 0x100 * sens_num)); return d; }
// I2C command sequencer, block of 16 DWORD slots for absolute frame numbers (modulo 16) and 15 slots for relative ones
// 0 - ASAP, 1 next frame, 14 -14-th next.
// Data written depends on context:
// 1 - I2C register write: index page (MSB), 3 payload bytes. Payload bytes are used according to table and sent
// after the slave address and optional high address byte. Other bytes are sent in descending order (LSB- last).
// If less than 4 bytes are programmed in the table the high bytes (starting with the one from the table) are
// skipped.
// If more than 4 bytes are programmed in the table for the page (high byte), one or two next 32-bit words
// bypass the index table and all 4 bytes are considered payload ones. If less than 4 extra bytes are to be
// sent for such extra word, only the lower bytes are sent.
//
// 2 - I2C register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
// in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
// read address in the table is programmed to be a single-byte one
void x393_sensi2c_abs (u32 d, int sens_num, int offset){writel(d, mmio_ptr + (0x1040 + 0x40 * sens_num + 0x1 * offset));} // Write sensor i2c sequencer
void x393_sensi2c_rel (u32 d, int sens_num, int offset){writel(d, mmio_ptr + (0x1080 + 0x40 * sens_num + 0x1 * offset));} // Write sensor i2c sequencer
// Lens vignetting correction (for each sub-frame separately)
void set_x393_lens_height0_m1 (x393_lens_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10f0 + 0x100 * sens_num));} // Subframe 0 height minus 1
x393_lens_height_m1_t get_x393_lens_height0_m1 (int sens_num) { x393_lens_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10f0 + 0x100 * sens_num)); return d; }
void set_x393_lens_height1_m1 (x393_lens_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10f4 + 0x100 * sens_num));} // Subframe 1 height minus 1
x393_lens_height_m1_t get_x393_lens_height1_m1 (int sens_num) { x393_lens_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10f4 + 0x100 * sens_num)); return d; }
void set_x393_lens_height2_m1 (x393_lens_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10f8 + 0x100 * sens_num));} // Subframe 2 height minus 1
x393_lens_height_m1_t get_x393_lens_height2_m1 (int sens_num) { x393_lens_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10f8 + 0x100 * sens_num)); return d; }
void x393_lens_corr_cnh_addr_data (x393_lens_corr_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10fc + 0x100 * sens_num));} // Combined address/data to write lens vignetting correction coefficients
// Lens vignetting coefficient addresses - use with x393_lens_corr_wo_t (X393_LENS_CORR_CNH_ADDR_DATA)
// Sensor gamma conversion control (See Python code for examples of the table data generation)
void set_x393_sens_gamma_ctrl (x393_gamma_ctl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10e0 + 0x100 * sens_num));} // Gamma module control
x393_gamma_ctl_t get_x393_sens_gamma_ctrl (int sens_num) { x393_gamma_ctl_t d; d.d32 = readl(mmio_ptr + (0x10e0 + 0x100 * sens_num)); return d; }
void x393_sens_gamma_tbl (x393_gamma_tbl_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10e4 + 0x100 * sens_num));} // Write sensor gamma table address/data (with autoincrement)
void set_x393_sens_gamma_height01m1 (x393_gamma_height01m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10e8 + 0x100 * sens_num));} // Gamma module subframes 0,1 heights minus 1
x393_gamma_height01m1_t get_x393_sens_gamma_height01m1 (int sens_num) { x393_gamma_height01m1_t d; d.d32 = readl(mmio_ptr + (0x10e8 + 0x100 * sens_num)); return d; }
void set_x393_sens_gamma_height2m1 (x393_gamma_height2m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10ec + 0x100 * sens_num));} // Gamma module subframe 2 height minus 1
x393_gamma_height2m1_t get_x393_sens_gamma_height2m1 (int sens_num) { x393_gamma_height2m1_t d; d.d32 = readl(mmio_ptr + (0x10ec + 0x100 * sens_num)); return d; }
// Windows for histogram subchannels
void set_x393_histogram_lt0 (x393_hist_left_top_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10c0 + 0x100 * sens_num));} // Specify histogram 0 left/top
x393_hist_left_top_t get_x393_histogram_lt0 (int sens_num) { x393_hist_left_top_t d; d.d32 = readl(mmio_ptr + (0x10c0 + 0x100 * sens_num)); return d; }
void set_x393_histogram_wh0 (x393_hist_width_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10c4 + 0x100 * sens_num));} // Specify histogram 0 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh0 (int sens_num) { x393_hist_width_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10c4 + 0x100 * sens_num)); return d; }
void set_x393_histogram_lt1 (x393_hist_left_top_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10c8 + 0x100 * sens_num));} // Specify histogram 1 left/top
x393_hist_left_top_t get_x393_histogram_lt1 (int sens_num) { x393_hist_left_top_t d; d.d32 = readl(mmio_ptr + (0x10c8 + 0x100 * sens_num)); return d; }
void set_x393_histogram_wh1 (x393_hist_width_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10cc + 0x100 * sens_num));} // Specify histogram 1 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh1 (int sens_num) { x393_hist_width_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10cc + 0x100 * sens_num)); return d; }
void set_x393_histogram_lt2 (x393_hist_left_top_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10d0 + 0x100 * sens_num));} // Specify histogram 2 left/top
x393_hist_left_top_t get_x393_histogram_lt2 (int sens_num) { x393_hist_left_top_t d; d.d32 = readl(mmio_ptr + (0x10d0 + 0x100 * sens_num)); return d; }
void set_x393_histogram_wh2 (x393_hist_width_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10d4 + 0x100 * sens_num));} // Specify histogram 2 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh2 (int sens_num) { x393_hist_width_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10d4 + 0x100 * sens_num)); return d; }
void set_x393_histogram_lt3 (x393_hist_left_top_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10d8 + 0x100 * sens_num));} // Specify histogram 3 left/top
x393_hist_left_top_t get_x393_histogram_lt3 (int sens_num) { x393_hist_left_top_t d; d.d32 = readl(mmio_ptr + (0x10d8 + 0x100 * sens_num)); return d; }
void set_x393_histogram_wh3 (x393_hist_width_height_m1_t d, int sens_num){writel(d.d32, mmio_ptr + (0x10dc + 0x100 * sens_num));} // Specify histogram 3 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh3 (int sens_num) { x393_hist_width_height_m1_t d; d.d32 = readl(mmio_ptr + (0x10dc + 0x100 * sens_num)); return d; }
// DMA control for the histograms. Subchannel here is 4*sensor_port+ histogram_subchannel
void set_x393_hist_saxi_mode (x393_hist_saxi_mode_t d){writel(d.d32, mmio_ptr + 0x1440);} // Histogram DMA operation mode
x393_hist_saxi_mode_t get_x393_hist_saxi_mode (void) { x393_hist_saxi_mode_t d; d.d32 = readl(mmio_ptr + 0x1440); return d; }
void set_x393_hist_saxi_addr (x393_hist_saxi_addr_t d, int subchannel){writel(d.d32, mmio_ptr + (0x1400 + 0x4 * subchannel));} // Histogram DMA addresses (in 4096 byte pages)
x393_hist_saxi_addr_t get_x393_hist_saxi_addr (int subchannel) { x393_hist_saxi_addr_t d; d.d32 = readl(mmio_ptr + (0x1400 + 0x4 * subchannel)); return d; }
// Read-only addresses for sensors status information
x393_status_sens_i2c_t x393_sensi2c_status (int sens_num) { x393_status_sens_i2c_t d; d.d32 = readl(mmio_ptr + (0x2080 + 0x8 * sens_num)); return d; } // Status of the sensors i2c
x393_status_sens_io_t x393_sensio_status (int sens_num) { x393_status_sens_io_t d; d.d32 = readl(mmio_ptr + (0x2084 + 0x8 * sens_num)); return d; } // Status of the sensor ports I/O pins
// Compressor bitfields values
// Compressor control
void x393_cmprs_control_reg (x393_cmprs_mode_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x1800 + 0x40 * cmprs_chn));} // Program compressor channel operation mode
void set_x393_cmprs_status (x393_status_ctrl_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x1804 + 0x40 * cmprs_chn));} // Setup compressor status report mode
x393_status_ctrl_t get_x393_cmprs_status (int cmprs_chn) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + (0x1804 + 0x40 * cmprs_chn)); return d; }
void set_x393_cmprs_format (x393_cmprs_frame_format_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x1808 + 0x40 * cmprs_chn));} // Compressor frame format
x393_cmprs_frame_format_t get_x393_cmprs_format (int cmprs_chn) { x393_cmprs_frame_format_t d; d.d32 = readl(mmio_ptr + (0x1808 + 0x40 * cmprs_chn)); return d; }
void set_x393_cmprs_color_saturation (x393_cmprs_colorsat_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x180c + 0x40 * cmprs_chn));} // Compressor color saturation
x393_cmprs_colorsat_t get_x393_cmprs_color_saturation (int cmprs_chn) { x393_cmprs_colorsat_t d; d.d32 = readl(mmio_ptr + (0x180c + 0x40 * cmprs_chn)); return d; }
void set_x393_cmprs_coring_mode (x393_cmprs_coring_mode_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x1810 + 0x40 * cmprs_chn));} // Select coring mode
x393_cmprs_coring_mode_t get_x393_cmprs_coring_mode (int cmprs_chn) { x393_cmprs_coring_mode_t d; d.d32 = readl(mmio_ptr + (0x1810 + 0x40 * cmprs_chn)); return d; }
void x393_cmprs_interrupts (x393_cmprs_interrupts_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x1814 + 0x40 * cmprs_chn));} // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable)
// Compressor tables load control
// Several tables can be loaded to the compressor, there are 4 types of them:
// 0:quantization tables - 8 pairs can be loaded and switched at run time,
// 1:coring tables - 8 pairs can be loaded and switched at run time,
// 2:focusing tables - 15 tables can be loaded and switched at run time (16-th table address space
// is used to program other focusing mode parameters,
// 3:Huffman tables - 1 pair tables can be loaded
// Default tables are loaded with the bitstream file (100% quality for quantization table 0
// Loading a table requires to load address of the beginning of data, it includes table type and optional offset
// when multiple tables of the same type are used. Next the data should be written to the same register address,
// the table address is auto-incremented,
// Data for the tables 0..2 should be combined: two items into a single 32-bit DWORD (little endian), treating
// each item as a 16-bit word. The Huffman table is one item per DWORD. Address offset is calculated in DWORDs
// Compressor table types
// Compressor tables control
void x393_cmprs_tables_data (u32 d, int cmprs_chn){writel(d, mmio_ptr + (0x1818 + 0x40 * cmprs_chn));} // Compressor tables data
void x393_cmprs_tables_address (x393_cmprs_table_addr_t d, int cmprs_chn){writel(d.d32, mmio_ptr + (0x181c + 0x40 * cmprs_chn));} // Compressor tables type/address
// Compressor channel status)
x393_cmprs_status_t x393_cmprs_status (int chn) { x393_cmprs_status_t d; d.d32 = readl(mmio_ptr + (0x2040 + 0x4 * chn)); return d; } // Status of the compressor channel (incl. interrupt
u32 x393_cmprs_hifreq (int chn) { u32 d; d = readl(mmio_ptr + (0x2050 + 0x4 * chn)); return d; } // Focus helper high-frequency amount
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
// serving all 4 compressor channels through its input ports. Below afi_port (0..3) references to one of the 4 ports of each. Control
// for two AXI HP channels is implemented as separate functions. Currently only the first channel is used
void x393_afimux0_en (x393_afimux_en_t d){writel(d.d32, mmio_ptr + 0x1900);} // AFI MUX 0 global/port run/pause control
void set_x393_afimux0_rst (x393_afimux_rst_t d){writel(d.d32, mmio_ptr + 0x1904);} // AFI MUX 0 per-port resets
x393_afimux_rst_t get_x393_afimux0_rst (void) { x393_afimux_rst_t d; d.d32 = readl(mmio_ptr + 0x1904); return d; }
void x393_afimux0_report_mode (x393_afimux_report_t d){writel(d.d32, mmio_ptr + 0x1908);} // AFI MUX 0 readout pointer report mode
void set_x393_afimux0_status_control (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1910);} // AFI MUX 0 status report mode
x393_status_ctrl_t get_x393_afimux0_status_control (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1910); return d; }
void set_x393_afimux0_sa (x393_afimux_sa_t d, int afi_port){writel(d.d32, mmio_ptr + (0x1920 + 0x4 * afi_port));} // AFI MUX 0 DMA buffer start address in 32-byte blocks
x393_afimux_sa_t get_x393_afimux0_sa (int afi_port) { x393_afimux_sa_t d; d.d32 = readl(mmio_ptr + (0x1920 + 0x4 * afi_port)); return d; }
void set_x393_afimux0_len (x393_afimux_len_t d, int afi_port){writel(d.d32, mmio_ptr + (0x1930 + 0x4 * afi_port));} // AFI MUX 0 DMA buffer length in 32-byte blocks
x393_afimux_len_t get_x393_afimux0_len (int afi_port) { x393_afimux_len_t d; d.d32 = readl(mmio_ptr + (0x1930 + 0x4 * afi_port)); return d; }
// Same for the second AXI HP channel (not currently used)
void x393_afimux1_en (x393_afimux_en_t d){writel(d.d32, mmio_ptr + 0x1940);} // AFI MUX 1 global/port run/pause control
void set_x393_afimux1_rst (x393_afimux_rst_t d){writel(d.d32, mmio_ptr + 0x1944);} // AFI MUX 1 per-port resets
x393_afimux_rst_t get_x393_afimux1_rst (void) { x393_afimux_rst_t d; d.d32 = readl(mmio_ptr + 0x1944); return d; }
void x393_afimux1_report_mode (x393_afimux_report_t d){writel(d.d32, mmio_ptr + 0x1948);} // AFI MUX 1 readout pointer report mode
void set_x393_afimux1_status_control (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1950);} // AFI MUX 1 status report mode
x393_status_ctrl_t get_x393_afimux1_status_control (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1950); return d; }
void set_x393_afimux1_sa (x393_afimux_sa_t d, int afi_port){writel(d.d32, mmio_ptr + (0x1960 + 0x4 * afi_port));} // AFI MUX 1 DMA buffer start address in 32-byte blocks
x393_afimux_sa_t get_x393_afimux1_sa (int afi_port) { x393_afimux_sa_t d; d.d32 = readl(mmio_ptr + (0x1960 + 0x4 * afi_port)); return d; }
void set_x393_afimux1_len (x393_afimux_len_t d, int afi_port){writel(d.d32, mmio_ptr + (0x1970 + 0x4 * afi_port));} // AFI MUX 1 DMA buffer length in 32-byte blocks
x393_afimux_len_t get_x393_afimux1_len (int afi_port) { x393_afimux_len_t d; d.d32 = readl(mmio_ptr + (0x1970 + 0x4 * afi_port)); return d; }
// Read-only sensors status information (pointer offset and last sequence number)
x393_afimux_status_t x393_afimux0_status (int afi_port) { x393_afimux_status_t d; d.d32 = readl(mmio_ptr + (0x2060 + 0x4 * afi_port)); return d; } // Status of the AFI MUX 0 (including image pointer)
x393_afimux_status_t x393_afimux1_status (int afi_port) { x393_afimux_status_t d; d.d32 = readl(mmio_ptr + (0x2070 + 0x4 * afi_port)); return d; } // Status of the AFI MUX 1 (including image pointer)
//
// GPIO contol. Each of the 10 pins can be controlled by the software - individually or simultaneously or from any of the 3 masters (other FPGA modules)
// Currently these modules are;
// A - camsync (intercamera synchronization), uses up to 4 pins
// B - reserved (not yet used) and
// C - logger (IMU, GPS, images), uses 6 pins, including separate i2c available on extension boards
// If several enabled ports try to contol the same bit, highest priority has port C, lowest - software controlled
void x393_gpio_set_pins (x393_gpio_set_pins_t d){writel(d.d32, mmio_ptr + 0x1c00);} // State of the GPIO pins and seq. number
void set_x393_gpio_status_control (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1c04);} // GPIO status control mode
x393_status_ctrl_t get_x393_gpio_status_control (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1c04); return d; }
// Read-only GPIO pins state
x393_gpio_status_t x393_gpio_status (void) { x393_gpio_status_t d; d.d32 = readl(mmio_ptr + 0x20c0); return d; } // State of the GPIO pins and seq. number
// RTC control
void set_x393_rtc_usec (x393_rtc_usec_t d) {writel(d.d32, mmio_ptr + 0x1c10);} // RTC microseconds
x393_rtc_usec_t get_x393_rtc_usec (void) { x393_rtc_usec_t d; d.d32 = readl(mmio_ptr + 0x1c10); return d; }
void set_x393_rtc_sec_set (x393_rtc_sec_t d) {writel(d.d32, mmio_ptr + 0x1c14);} // RTC seconds and set clock
x393_rtc_sec_t get_x393_rtc_sec_set (void) { x393_rtc_sec_t d; d.d32 = readl(mmio_ptr + 0x1c14); return d; }
void set_x393_rtc_corr (x393_rtc_corr_t d) {writel(d.d32, mmio_ptr + 0x1c18);} // RTC correction (+/- 1/256 full scale)
x393_rtc_corr_t get_x393_rtc_corr (void) { x393_rtc_corr_t d; d.d32 = readl(mmio_ptr + 0x1c18); return d; }
void set_x393_rtc_set_status (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1c1c);} // RTC status control mode, write makes a snapshot to be read out
x393_status_ctrl_t get_x393_rtc_set_status (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1c1c); return d; }
// Read-only RTC state
x393_rtc_status_t x393_rtc_status (void) { x393_rtc_status_t d; d.d32 = readl(mmio_ptr + 0x20c4); return d; } // RTC status reg
x393_rtc_sec_t x393_rtc_status_sec (void) { x393_rtc_sec_t d; d.d32 = readl(mmio_ptr + 0x20c8); return d; } // RTC snapshot seconds
x393_rtc_usec_t x393_rtc_status_usec (void) { x393_rtc_usec_t d; d.d32 = readl(mmio_ptr + 0x20cc); return d; } // RTC snapshot microseconds
// CAMSYNC control
void x393_camsync_mode (x393_camsync_mode_t d){writel(d.d32, mmio_ptr + 0x1c20);} // CAMSYNC mode
void x393_camsync_trig_src (x393_camsync_io_t d){writel(d.d32, mmio_ptr + 0x1c24);} // CAMSYNC trigger source
void x393_camsync_trig_dst (x393_camsync_io_t d){writel(d.d32, mmio_ptr + 0x1c28);} // CAMSYNC trigger destination
// Trigger period has special value for small (<255) values written to this register
// d == 0 - disable (stop periodic mode)
// d == 1 - single trigger
// d == 2..255 - set output pulse / input-output serial bit duration (no start generated)
// d >= 256 - repetitive trigger
void set_x393_camsync_trig_period (u32 d) {writel(d, mmio_ptr + 0x1c2c);} // CAMSYNC trigger period
u32 get_x393_camsync_trig_period (void) { u32 d; d = readl(mmio_ptr + 0x1c2c); return d; }
void set_x393_camsync_trig_delay (u32 d, int sens_chn){writel(d, mmio_ptr + (0x1c30 + 0x4 * sens_chn));} // CAMSYNC trigger delay
u32 get_x393_camsync_trig_delay (int sens_chn) { u32 d; d = readl(mmio_ptr + (0x1c30 + 0x4 * sens_chn)); return d; }
// Command sequencer control
// Controller is programmed through 32 locations. Each registers but the control require two writes:
// First write - register address (AXI_WR_ADDR_BITS bits), second - register data (32 bits)
// Writing to the contol register (0x1f) resets the first/second counter so the next write will be "first"
// 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame
// "just missed" - in that case data will go to the current frame.
// 0x10 - write seq commands to be sent ASAP
// 0x11 - write seq commands to be sent after the next frame starts
//
// 0x1e - write seq commands to be sent after the next 14 frame start pulses
// 0x1f - control register:
// [14] - reset all FIFO (takes 32 clock pulses), also - stops seq until run command
// [13:12] - 3 - run seq, 2 - stop seq , 1,0 - no change to run state
// [1:0] - 0: NOP, 1: clear IRQ, 2 - Clear IE, 3: set IE
void x393_cmdframeseq_ctrl (x393_cmdframeseq_mode_t d, int sens_chn){writel(d.d32, mmio_ptr + (0x1e7c + 0x80 * sens_chn));} // CMDFRAMESEQ control register
void x393_cmdframeseq_abs (u32 d, int sens_chn, int offset){writel(d, mmio_ptr + (0x1e00 + 0x20 * sens_chn + 0x1 * offset));} // CMDFRAMESEQ absolute frame address/command
void x393_cmdframeseq_rel (u32 d, int sens_chn, int offset){writel(d, mmio_ptr + (0x1e40 + 0x20 * sens_chn + 0x1 * offset));} // CMDFRAMESEQ relative frame address/command
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
void set_x393_cmdseqmux_status_ctrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1c08);} // CMDSEQMUX status control mode (status provides current frame numbers)
x393_status_ctrl_t get_x393_cmdseqmux_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1c08); return d; }
x393_cmdseqmux_status_t x393_cmdseqmux_status (void) { x393_cmdseqmux_status_t d; d.d32 = readl(mmio_ptr + 0x20e0); return d; } // CMDSEQMUX status data (frame numbers and interrupts
// Event logger
// Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.
// Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.
// Register pages:
// Register configuration addresses (with X393_LOGGER_PAGE_CONF):
void set_x393_logger_status_ctrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1c88);} // Logger status configuration (to report sample number)
x393_status_ctrl_t get_x393_logger_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1c88); return d; }
void x393_logger_data (x393_logger_data_t d){writel(d.d32, mmio_ptr + 0x1c80);} // Logger register write data
void x393_logger_address (x393_logger_address_t d){writel(d.d32, mmio_ptr + 0x1c84);} // Logger register write page/address
x393_logger_status_t x393_logger_status (void) { x393_logger_status_t d; d.d32 = readl(mmio_ptr + 0x20e4); return d; } // Logger status data (sequence number)
// MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger
void set_x393_mult_saxi_status_ctrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1ce0);} // MULT_SAXI status control mode (status provides current DWORD pointer)
x393_status_ctrl_t get_x393_mult_saxi_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1ce0); return d; }
void x393_mult_saxi_buf_address (x393_mult_saxi_al_t d, int chn){writel(d.d32, mmio_ptr + (0x1cc0 + 0x8 * chn));} // MULT_SAXI buffer start address in DWORDS
void x393_mult_saxi_buf_len (x393_mult_saxi_al_t d, int chn){writel(d.d32, mmio_ptr + (0x1cc4 + 0x8 * chn));} // MULT_SAXI buffer length in DWORDS
x393_mult_saxi_al_t x393_mult_saxi_status (int chn) { x393_mult_saxi_al_t d; d.d32 = readl(mmio_ptr + (0x20d0 + 0x4 * chn)); return d; } // MULT_SAXI current DWORD pointer
// MULTI_CLK - global clock generation PLLs. Interface provided for debugging, no interaction is needed for normal operation
void set_x393_multiclk_status_ctrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1ca4);} // MULTI_CLK status generation (do not use or do not set auto)
x393_status_ctrl_t get_x393_multiclk_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1ca4); return d; }
void set_x393_multiclk_ctrl (x393_multiclk_ctl_t d){writel(d.d32, mmio_ptr + 0x1ca0);} // MULTI_CLK reset and power down control
x393_multiclk_ctl_t get_x393_multiclk_ctrl (void) { x393_multiclk_ctl_t d; d.d32 = readl(mmio_ptr + 0x1ca0); return d; }
x393_multiclk_status_t x393_multiclk_status (void) { x393_multiclk_status_t d; d.d32 = readl(mmio_ptr + 0x20e8); return d; } // MULTI_CLK lock and toggle state
// Debug ring module
// Debug ring module (when enabled with DEBUG_RING in system_defines.vh) provides low-overhead read/write access to internal test points
// To write data you need to write 32-bit data with x393_debug_shift(u32) multiple times to fill the ring register (length depends on
// implementation), skip this step if only reading from the modules under test is required.
// Exchange data with x393_debug_load(), the data from the ring shift register.
// Write 0xffffffff (or other "magic" data) if the ring length is unknown - this DWORD will appear on the output after the useful data
// Read all data, waiting for status sequence number to be incremented,status mode should be set to auto (3) wor each DWORD certain
// number of times or until the "magic" DWORD appears, writing "magic" to shift out next 32 bits.
void set_x393_debug_status_ctrl (x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x1c48);} // Debug ring status generation - set to auto(3) if used
x393_status_ctrl_t get_x393_debug_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x1c48); return d; }
void x393_debug_load (void) {writel(0, mmio_ptr + 0x1c44);} // Debug ring copy shift register to/from tested modules
void x393_debug_shift (u32 d) {writel(d, mmio_ptr + 0x1c40);} // Debug ring shift ring by 32 bits
x393_debug_status_t x393_debug_status (void) { x393_debug_status_t d; d.d32 = readl(mmio_ptr + 0x23f0); return d; } // Debug read status (watch sequence number)
u32 x393_debug_read (void) { u32 d; d = readl(mmio_ptr + 0x23f4); return d; } // Debug read DWORD form ring register
// Write-only addresses to program memory channel 3 (test channel)
void x393_mcntrl_chn3_scanline_mode (x393_mcntrl_mode_scan_t d){writel(d.d32, mmio_ptr + 0x04c0);} // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn3_scanline_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x04c4);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn3_scanline_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x04c4); return d; }
void x393_mcntrl_chn3_scanline_startaddr (x393_mcntrl_window_frame_sa_t d){writel(d.d32, mmio_ptr + 0x04c8);} // Set frame start address
void x393_mcntrl_chn3_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_t d){writel(d.d32, mmio_ptr + 0x04cc);} // Set frame size (address increment)
void x393_mcntrl_chn3_scanline_frame_last(x393_mcntrl_window_last_frame_num_t d){writel(d.d32, mmio_ptr + 0x04d0);} // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn3_scanline_frame_full_width(x393_mcntrl_window_full_width_t d){writel(d.d32, mmio_ptr + 0x04d4);} // Set frame full(padded) width
void x393_mcntrl_chn3_scanline_window_wh (x393_mcntrl_window_width_height_t d){writel(d.d32, mmio_ptr + 0x04d8);} // Set frame window size
void x393_mcntrl_chn3_scanline_window_x0y0(x393_mcntrl_window_left_top_t d){writel(d.d32, mmio_ptr + 0x04dc);} // Set frame position
void x393_mcntrl_chn3_scanline_startxy (x393_mcntrl_window_startx_starty_t d){writel(d.d32, mmio_ptr + 0x04e0);} // Set startXY register
// Write-only addresses to program memory channel 2 (test channel)
void x393_mcntrl_chn2_tiled_mode (x393_mcntrl_mode_scan_t d){writel(d.d32, mmio_ptr + 0x0500);} // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn2_tiled_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0504);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn2_tiled_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0504); return d; }
void x393_mcntrl_chn2_tiled_startaddr (x393_mcntrl_window_frame_sa_t d){writel(d.d32, mmio_ptr + 0x0508);} // Set frame start address
void x393_mcntrl_chn2_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d){writel(d.d32, mmio_ptr + 0x050c);} // Set frame size (address increment)
void x393_mcntrl_chn2_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d){writel(d.d32, mmio_ptr + 0x0510);} // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn2_tiled_frame_full_width(x393_mcntrl_window_full_width_t d){writel(d.d32, mmio_ptr + 0x0514);} // Set frame full(padded) width
void x393_mcntrl_chn2_tiled_window_wh (x393_mcntrl_window_width_height_t d){writel(d.d32, mmio_ptr + 0x0518);} // Set frame window size
void x393_mcntrl_chn2_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d){writel(d.d32, mmio_ptr + 0x051c);} // Set frame position
void x393_mcntrl_chn2_tiled_startxy (x393_mcntrl_window_startx_starty_t d){writel(d.d32, mmio_ptr + 0x0520);} // Set startXY register
void x393_mcntrl_chn2_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d){writel(d.d32, mmio_ptr + 0x0524);} // Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel 4 (test channel)
void x393_mcntrl_chn4_tiled_mode (x393_mcntrl_mode_scan_t d){writel(d.d32, mmio_ptr + 0x0540);} // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn4_tiled_status_cntrl(x393_status_ctrl_t d){writel(d.d32, mmio_ptr + 0x0544);} // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn4_tiled_status_cntrl(void) { x393_status_ctrl_t d; d.d32 = readl(mmio_ptr + 0x0544); return d; }
void x393_mcntrl_chn4_tiled_startaddr (x393_mcntrl_window_frame_sa_t d){writel(d.d32, mmio_ptr + 0x0548);} // Set frame start address
void x393_mcntrl_chn4_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d){writel(d.d32, mmio_ptr + 0x054c);} // Set frame size (address increment)
void x393_mcntrl_chn4_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d){writel(d.d32, mmio_ptr + 0x0550);} // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn4_tiled_frame_full_width(x393_mcntrl_window_full_width_t d){writel(d.d32, mmio_ptr + 0x0554);} // Set frame full(padded) width
void x393_mcntrl_chn4_tiled_window_wh (x393_mcntrl_window_width_height_t d){writel(d.d32, mmio_ptr + 0x0558);} // Set frame window size
void x393_mcntrl_chn4_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d){writel(d.d32, mmio_ptr + 0x055c);} // Set frame position
void x393_mcntrl_chn4_tiled_startxy (x393_mcntrl_window_startx_starty_t d){writel(d.d32, mmio_ptr + 0x0560);} // Set startXY register
void x393_mcntrl_chn4_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d){writel(d.d32, mmio_ptr + 0x0564);} // Set tile size/step (tiled mode only)
py393/generated/x393.h deleted 100644 → 0
View file @ 901020c6
/*******************************************************************************
* File: x393.h
* Date: 2016-03-29
* Author: auto-generated file, see x393_export_c.py
* Description: Constants definitions and functions declarations to access x393 hardware registers
*******************************************************************************/
#include "elphel/x393_types.h"
//#include "elphel/x393_defs.h // alternative variant"
// See elphel/x393_map.h for the ordered list of all I/O register addresses used
// init_mmio_ptr() should be called once before using any of the other declared functions
int init_mmio_ptr(void);
// R/W addresses to set up memory arbiter priorities. For sensors (chn = 8..11), for compressors - 12..15
void set_x393_mcntrl_arbiter_priority (x393_arbite_pri_t d, int chn); // Set memory arbiter priority (currently r/w, may become just wo)
x393_arbite_pri_t get_x393_mcntrl_arbiter_priority (int chn);
// Enable/disable memory channels (bits in a 16-bit word). For sensors (chn = 8..11), for compressors - 12..15
void set_x393_mcntrl_chn_en (x393_mcntr_chn_en_t d); // Enable/disable memory channels (currently r/w, may become just wo)
x393_mcntr_chn_en_t get_x393_mcntrl_chn_en (void);
void set_x393_mcntrl_dqs_dqm_patt (x393_mcntr_dqs_dqm_patt_t d); // Setup DQS and DQM patterns
x393_mcntr_dqs_dqm_patt_t get_x393_mcntrl_dqs_dqm_patt (void);
void set_x393_mcntrl_dq_dqs_tri (x393_mcntr_dqs_dqm_tri_t d); // Setup DQS and DQ on/off sequence
x393_mcntr_dqs_dqm_tri_t get_x393_mcntrl_dq_dqs_tri (void);
// Following enable/disable addresses can be written with any data, only addresses matter
void x393_mcntrl_dis (void); // Disable DDR3 memory controller
void x393_mcntrl_en (void); // Enable DDR3 memory controller
void x393_mcntrl_refresh_dis (void); // Disable DDR3 memory refresh
void x393_mcntrl_refresh_en (void); // Enable DDR3 memory refresh
void x393_mcntrl_sdrst_dis (void); // Disable DDR3 memory reset
void x393_mcntrl_sdrst_en (void); // Enable DDR3 memory reset
void x393_mcntrl_cke_dis (void); // Disable DDR3 memory CKE
void x393_mcntrl_cke_en (void); // Enable DDR3 memory CKE
void x393_mcntrl_cmda_dis (void); // Disable DDR3 memory command/address lines
void x393_mcntrl_cmda_en (void); // Enable DDR3 memory command/address lines
// Set DDR3 memory controller I/O delays and other timing parameters (should use individually calibrated values)
void set_x393_mcntrl_dq_odly0 (x393_dly_t d, int chn); // Lane0 DQ output delays
x393_dly_t get_x393_mcntrl_dq_odly0 (int chn);
void set_x393_mcntrl_dq_odly1 (x393_dly_t d, int chn); // Lane1 DQ output delays
x393_dly_t get_x393_mcntrl_dq_odly1 (int chn);
void set_x393_mcntrl_dq_idly0 (x393_dly_t d, int chn); // Lane0 DQ input delays
x393_dly_t get_x393_mcntrl_dq_idly0 (int chn);
void set_x393_mcntrl_dq_idly1 (x393_dly_t d, int chn); // Lane1 DQ input delays
x393_dly_t get_x393_mcntrl_dq_idly1 (int chn);
void set_x393_mcntrl_dqs_odly0 (x393_dly_t d); // Lane0 DQS output delay
x393_dly_t get_x393_mcntrl_dqs_odly0 (void);
void set_x393_mcntrl_dqs_odly1 (x393_dly_t d); // Lane1 DQS output delay
x393_dly_t get_x393_mcntrl_dqs_odly1 (void);
void set_x393_mcntrl_dqs_idly0 (x393_dly_t d); // Lane0 DQS input delay
x393_dly_t get_x393_mcntrl_dqs_idly0 (void);
void set_x393_mcntrl_dqs_idly1 (x393_dly_t d); // Lane1 DQS input delay
x393_dly_t get_x393_mcntrl_dqs_idly1 (void);
void set_x393_mcntrl_dm_odly0 (x393_dly_t d); // Lane0 DM output delay
x393_dly_t get_x393_mcntrl_dm_odly0 (void);
void set_x393_mcntrl_dm_odly1 (x393_dly_t d); // Lane1 DM output delay
x393_dly_t get_x393_mcntrl_dm_odly1 (void);
void set_x393_mcntrl_cmda_odly (x393_dly_t d, int chn); // Address, bank and commands delays
x393_dly_t get_x393_mcntrl_cmda_odly (int chn);
void set_x393_mcntrl_phase (x393_dly_t d); // Clock phase
x393_dly_t get_x393_mcntrl_phase (void);
void x393_mcntrl_dly_set (void); // Set all pre-programmed delays
void set_x393_mcntrl_wbuf_dly (x393_wbuf_dly_t d); // Set write buffer delay
x393_wbuf_dly_t get_x393_mcntrl_wbuf_dly (void);
// Write-only addresses to program memory channels for sensors (chn = 0..3), memory channels 8..11
void x393_sens_mcntrl_scanline_mode (x393_mcntrl_mode_scan_t d, int chn); // Set mode register (write last after other channel registers are set)
void set_x393_sens_mcntrl_scanline_status_cntrl(x393_status_ctrl_t d, int chn); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_sens_mcntrl_scanline_status_cntrl(int chn);
void x393_sens_mcntrl_scanline_startaddr (x393_mcntrl_window_frame_sa_t d, int chn); // Set frame start address
void x393_sens_mcntrl_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_t d, int chn); // Set frame size (address increment)
void x393_sens_mcntrl_scanline_frame_last(x393_mcntrl_window_last_frame_num_t d, int chn); // Set last frame number (number of frames in buffer minus 1)
void x393_sens_mcntrl_scanline_frame_full_width(x393_mcntrl_window_full_width_t d, int chn); // Set frame full(padded) width
void x393_sens_mcntrl_scanline_window_wh (x393_mcntrl_window_width_height_t d, int chn); // Set frame window size
void x393_sens_mcntrl_scanline_window_x0y0(x393_mcntrl_window_left_top_t d, int chn); // Set frame position
void x393_sens_mcntrl_scanline_startxy (x393_mcntrl_window_startx_starty_t d, int chn); // Set startXY register
// Write-only addresses to program memory channels for compressors (chn = 0..3), memory channels 12..15
void x393_sens_mcntrl_tiled_mode (x393_mcntrl_mode_scan_t d, int chn); // Set mode register (write last after other channel registers are set)
void set_x393_sens_mcntrl_tiled_status_cntrl(x393_status_ctrl_t d, int chn); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_sens_mcntrl_tiled_status_cntrl(int chn);
void x393_sens_mcntrl_tiled_startaddr (x393_mcntrl_window_frame_sa_t d, int chn); // Set frame start address
void x393_sens_mcntrl_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d, int chn); // Set frame size (address increment)
void x393_sens_mcntrl_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d, int chn); // Set last frame number (number of frames in buffer minus 1)
void x393_sens_mcntrl_tiled_frame_full_width(x393_mcntrl_window_full_width_t d, int chn); // Set frame full(padded) width
void x393_sens_mcntrl_tiled_window_wh (x393_mcntrl_window_width_height_t d, int chn); // Set frame window size
void x393_sens_mcntrl_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d, int chn); // Set frame position
void x393_sens_mcntrl_tiled_startxy (x393_mcntrl_window_startx_starty_t d, int chn); // Set startXY register
void x393_sens_mcntrl_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d, int chn); // Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel for membridge, memory channel 1
void x393_membridge_scanline_mode (x393_mcntrl_mode_scan_t d); // Set mode register (write last after other channel registers are set)
void set_x393_membridge_scanline_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_membridge_scanline_status_cntrl(void);
void x393_membridge_scanline_startaddr (x393_mcntrl_window_frame_sa_t d); // Set frame start address
void x393_membridge_scanline_frame_size (x393_mcntrl_window_frame_sa_inc_t d); // Set frame size (address increment)
void x393_membridge_scanline_frame_last (x393_mcntrl_window_last_frame_num_t d); // Set last frame number (number of frames in buffer minus 1)
void x393_membridge_scanline_frame_full_width(x393_mcntrl_window_full_width_t d); // Set frame full(padded) width
void x393_membridge_scanline_window_wh (x393_mcntrl_window_width_height_t d); // Set frame window size
void x393_membridge_scanline_window_x0y0 (x393_mcntrl_window_left_top_t d); // Set frame position
void x393_membridge_scanline_startxy (x393_mcntrl_window_startx_starty_t d); // Set startXY register
void x393_membridge_ctrl (x393_membridge_cmd_t d); // Issue membridge command
void set_x393_membridge_status_cntrl (x393_status_ctrl_t d); // Set membridge status control register
x393_status_ctrl_t get_x393_membridge_status_cntrl (void);
void x393_membridge_lo_addr64 (u29_t d); // start address of the system memory range in QWORDs (4 LSBs==0)
void x393_membridge_size64 (u29_t d); // size of the system memory range in QWORDs (4 LSBs==0), rolls over
void x393_membridge_start64 (u29_t d); // start of transfer offset to system memory range in QWORDs (4 LSBs==0)
void x393_membridge_len64 (u29_t d); // Full length of transfer in QWORDs
void x393_membridge_width64 (u29_t d); // Frame width in QWORDs (last xfer in each line may be partial)
void x393_membridge_mode (x393_membridge_mode_t d); // AXI cache mode
// Write-only addresses to PS PIO (Software generated DDR3 memory access sequences)
void x393_mcntrl_ps_en_rst (x393_ps_pio_en_rst_t d); // Set PS PIO enable and reset
void x393_mcntrl_ps_cmd (x393_ps_pio_cmd_t d); // Set PS PIO commands
void set_x393_mcntrl_ps_status_cntrl (x393_status_ctrl_t d); // Set PS PIO status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_ps_status_cntrl (void);
// Write-only addresses to to program status report mode for memory controller
void set_x393_mcontr_phy_status_cntrl (x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcontr_phy_status_cntrl (void);
void set_x393_mcontr_top_16bit_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcontr_top_16bit_status_cntrl(void);
// Write-only addresses to to program status report mode for test channels
void set_x393_mcntrl_test01_chn2_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn2_status_cntrl(void);
void set_x393_mcntrl_test01_chn3_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn3_status_cntrl(void);
void set_x393_mcntrl_test01_chn4_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_test01_chn4_status_cntrl(void);
// Write-only addresses for test channels commands
void x393_mcntrl_test01_chn2_mode (x393_test01_mode_t d); // Set command for test01 channel 2
void x393_mcntrl_test01_chn3_mode (x393_test01_mode_t d); // Set command for test01 channel 3
void x393_mcntrl_test01_chn4_mode (x393_test01_mode_t d); // Set command for test01 channel 4
// Read-only addresses for status information
x393_status_mcntrl_phy_t x393_mcontr_phy_status (void); // Status register for MCNTRL PHY
x393_status_mcntrl_top_t x393_mcontr_top_status (void); // Status register for MCNTRL requests
x393_status_mcntrl_ps_t x393_mcntrl_ps_status (void); // Status register for MCNTRL software R/W
x393_status_mcntrl_lintile_t x393_mcntrl_chn1_status (void); // Status register for MCNTRL CHN1 (membridge)
x393_status_mcntrl_lintile_t x393_mcntrl_chn3_status (void); // Status register for MCNTRL CHN3 (scanline)
x393_status_mcntrl_lintile_t x393_mcntrl_chn2_status (void); // Status register for MCNTRL CHN2 (tiled)
x393_status_mcntrl_lintile_t x393_mcntrl_chn4_status (void); // Status register for MCNTRL CHN4 (tiled)
x393_status_mcntrl_testchn_t x393_test01_chn2_status (void); // Status register for test channel 2
x393_status_mcntrl_testchn_t x393_test01_chn3_status (void); // Status register for test channel 3
x393_status_mcntrl_testchn_t x393_test01_chn4_status (void); // Status register for test channel 4
x393_status_membridge_t x393_membridge_status (void); // Status register for membridge
// Write-only control of the sensor channels
void x393_sens_mode (x393_sens_mode_t d, int sens_num); // Write sensor channel mode
void x393_sensi2c_ctrl (x393_i2c_ctltbl_t d, int sens_num); // Control sensor i2c, write i2c LUT
void set_x393_sensi2c_status_ctrl (x393_status_ctrl_t d, int sens_num); // Setup sensor i2c status report mode
x393_status_ctrl_t get_x393_sensi2c_status_ctrl (int sens_num);
void x393_sens_sync_mult (x393_sens_sync_mult_t d, int sens_num); // Configure frames combining
void x393_sens_sync_late (x393_sens_sync_late_t d, int sens_num); // Configure frame sync delay
void x393_sensio_ctrl (x393_sensio_ctl_t d, int sens_num); // Configure sensor I/O port
void set_x393_sensio_status_cntrl (x393_status_ctrl_t d, int sens_num); // Set status control for SENSIO module
x393_status_ctrl_t get_x393_sensio_status_cntrl (int sens_num);
void x393_sensio_jtag (x393_sensio_jpag_t d, int sens_num); // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)
void set_x393_sensio_width (x393_sensio_width_t d, int sens_num); // Set sensor line in pixels (0 - use line sync from the sensor)
x393_sensio_width_t get_x393_sensio_width (int sens_num);
void set_x393_sensio_tim0 (x393_sensio_tim0_t d, int sens_num); // Sensor port i/o timing configuration, register 0
x393_sensio_tim0_t get_x393_sensio_tim0 (int sens_num);
void set_x393_sensio_tim1 (x393_sensio_tim1_t d, int sens_num); // Sensor port i/o timing configuration, register 1
x393_sensio_tim1_t get_x393_sensio_tim1 (int sens_num);
void set_x393_sensio_tim2 (x393_sensio_tim2_t d, int sens_num); // Sensor port i/o timing configuration, register 2
x393_sensio_tim2_t get_x393_sensio_tim2 (int sens_num);
void set_x393_sensio_tim3 (x393_sensio_tim3_t d, int sens_num); // Sensor port i/o timing configuration, register 3
x393_sensio_tim3_t get_x393_sensio_tim3 (int sens_num);
// I2C command sequencer, block of 16 DWORD slots for absolute frame numbers (modulo 16) and 15 slots for relative ones
// 0 - ASAP, 1 next frame, 14 -14-th next.
// Data written depends on context:
// 1 - I2C register write: index page (MSB), 3 payload bytes. Payload bytes are used according to table and sent
// after the slave address and optional high address byte. Other bytes are sent in descending order (LSB- last).
// If less than 4 bytes are programmed in the table the high bytes (starting with the one from the table) are
// skipped.
// If more than 4 bytes are programmed in the table for the page (high byte), one or two next 32-bit words
// bypass the index table and all 4 bytes are considered payload ones. If less than 4 extra bytes are to be
// sent for such extra word, only the lower bytes are sent.
//
// 2 - I2C register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
// in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
// read address in the table is programmed to be a single-byte one
void x393_sensi2c_abs (u32 d, int sens_num, int offset); // Write sensor i2c sequencer
void x393_sensi2c_rel (u32 d, int sens_num, int offset); // Write sensor i2c sequencer
// Lens vignetting correction (for each sub-frame separately)
void set_x393_lens_height0_m1 (x393_lens_height_m1_t d, int sens_num); // Subframe 0 height minus 1
x393_lens_height_m1_t get_x393_lens_height0_m1 (int sens_num);
void set_x393_lens_height1_m1 (x393_lens_height_m1_t d, int sens_num); // Subframe 1 height minus 1
x393_lens_height_m1_t get_x393_lens_height1_m1 (int sens_num);
void set_x393_lens_height2_m1 (x393_lens_height_m1_t d, int sens_num); // Subframe 2 height minus 1
x393_lens_height_m1_t get_x393_lens_height2_m1 (int sens_num);
void x393_lens_corr_cnh_addr_data (x393_lens_corr_t d, int sens_num); // Combined address/data to write lens vignetting correction coefficients
// Lens vignetting coefficient addresses - use with x393_lens_corr_wo_t (X393_LENS_CORR_CNH_ADDR_DATA)
#define X393_LENS_AX 0x00000000 // Address of correction parameter Ax
#define X393_LENS_AX_MASK 0x000000f8 // Correction parameter Ax mask
#define X393_LENS_AY 0x00000008 // Address of correction parameter Ay
#define X393_LENS_AY_MASK 0x000000f8 // Correction parameter Ay mask
#define X393_LENS_C 0x00000010 // Address of correction parameter C
#define X393_LENS_C_MASK 0x000000f8 // Correction parameter C mask
#define X393_LENS_BX 0x00000020 // Address of correction parameter Bx
#define X393_LENS_BX_MASK 0x000000e0 // Correction parameter Bx mask
#define X393_LENS_BY 0x00000040 // Address of correction parameter By
#define X393_LENS_BY_MASK 0x000000e0 // Correction parameter By mask
#define X393_LENS_SCALE0 0x00000060 // Address of correction parameter scale0
#define X393_LENS_SCALE1 0x00000062 // Address of correction parameter scale1
#define X393_LENS_SCALE2 0x00000064 // Address of correction parameter scale2
#define X393_LENS_SCALE3 0x00000066 // Address of correction parameter scale3
#define X393_LENS_SCALES_MASK 0x000000f8 // Common mask for scales
#define X393_LENS_FAT0_IN 0x00000068 // Address of input fat zero parameter (to subtract from input)
#define X393_LENS_FAT0_IN_MASK 0x000000ff // Mask for fat zero input parameter
#define X393_LENS_FAT0_OUT 0x00000069 // Address of output fat zero parameter (to add to output)
#define X393_LENS_FAT0_OUT_MASK 0x000000ff // Mask for fat zero output parameters
#define X393_LENS_POST_SCALE 0x0000006a // Address of post scale (shift output) parameter
#define X393_LENS_POST_SCALE_MASK 0x000000ff // Mask for post scale parameter
// Sensor gamma conversion control (See Python code for examples of the table data generation)
void set_x393_sens_gamma_ctrl (x393_gamma_ctl_t d, int sens_num); // Gamma module control
x393_gamma_ctl_t get_x393_sens_gamma_ctrl (int sens_num);
void x393_sens_gamma_tbl (x393_gamma_tbl_t d, int sens_num); // Write sensor gamma table address/data (with autoincrement)
void set_x393_sens_gamma_height01m1 (x393_gamma_height01m1_t d, int sens_num); // Gamma module subframes 0,1 heights minus 1
x393_gamma_height01m1_t get_x393_sens_gamma_height01m1 (int sens_num);
void set_x393_sens_gamma_height2m1 (x393_gamma_height2m1_t d, int sens_num); // Gamma module subframe 2 height minus 1
x393_gamma_height2m1_t get_x393_sens_gamma_height2m1 (int sens_num);
// Windows for histogram subchannels
void set_x393_histogram_lt0 (x393_hist_left_top_t d, int sens_num); // Specify histogram 0 left/top
x393_hist_left_top_t get_x393_histogram_lt0 (int sens_num);
void set_x393_histogram_wh0 (x393_hist_width_height_m1_t d, int sens_num); // Specify histogram 0 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh0 (int sens_num);
void set_x393_histogram_lt1 (x393_hist_left_top_t d, int sens_num); // Specify histogram 1 left/top
x393_hist_left_top_t get_x393_histogram_lt1 (int sens_num);
void set_x393_histogram_wh1 (x393_hist_width_height_m1_t d, int sens_num); // Specify histogram 1 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh1 (int sens_num);
void set_x393_histogram_lt2 (x393_hist_left_top_t d, int sens_num); // Specify histogram 2 left/top
x393_hist_left_top_t get_x393_histogram_lt2 (int sens_num);
void set_x393_histogram_wh2 (x393_hist_width_height_m1_t d, int sens_num); // Specify histogram 2 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh2 (int sens_num);
void set_x393_histogram_lt3 (x393_hist_left_top_t d, int sens_num); // Specify histogram 3 left/top
x393_hist_left_top_t get_x393_histogram_lt3 (int sens_num);
void set_x393_histogram_wh3 (x393_hist_width_height_m1_t d, int sens_num); // Specify histogram 3 width/height
x393_hist_width_height_m1_t get_x393_histogram_wh3 (int sens_num);
// DMA control for the histograms. Subchannel here is 4*sensor_port+ histogram_subchannel
void set_x393_hist_saxi_mode (x393_hist_saxi_mode_t d); // Histogram DMA operation mode
x393_hist_saxi_mode_t get_x393_hist_saxi_mode (void);
void set_x393_hist_saxi_addr (x393_hist_saxi_addr_t d, int subchannel); // Histogram DMA addresses (in 4096 byte pages)
x393_hist_saxi_addr_t get_x393_hist_saxi_addr (int subchannel);
// Read-only addresses for sensors status information
x393_status_sens_i2c_t x393_sensi2c_status (int sens_num); // Status of the sensors i2c
x393_status_sens_io_t x393_sensio_status (int sens_num); // Status of the sensor ports I/O pins
// Compressor bitfields values
#define X393_CMPRS_CBIT_RUN_RST 0x00000000 // Reset compressor, stop immediately
#define X393_CMPRS_CBIT_RUN_DISABLE 0x00000001 // Disable compression of the new frames, finish any already started
#define X393_CMPRS_CBIT_RUN_STANDALONE 0x00000002 // Enable compressor, compress single frame from memory (async)
#define X393_CMPRS_CBIT_RUN_ENABLE 0x00000003 // Enable synchronous compression mode
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0 3x3 de-bayer core
#define X393_CMPRS_CBIT_CMODE_MONO6 0x00000001 // Mono 4:2:0 (6 blocks)
#define X393_CMPRS_CBIT_CMODE_JP46 0x00000002 // jp4, 6 blocks, original
#define X393_CMPRS_CBIT_CMODE_JP46DC 0x00000003 // jp4, 6 blocks, DC-improved
#define X393_CMPRS_CBIT_CMODE_JPEG20 0x00000004 // Color 4:2:0 with 5x5 de-bayer (not implemented)
#define X393_CMPRS_CBIT_CMODE_JP4 0x00000005 // jp4, 4 blocks
#define X393_CMPRS_CBIT_CMODE_JP4DC 0x00000006 // jp4, 4 blocks, DC-improved
#define X393_CMPRS_CBIT_CMODE_JP4DIFF 0x00000007 // jp4, 4 blocks, differential
#define X393_CMPRS_CBIT_CMODE_JP4DIFFHDR 0x00000008 // jp4, 4 blocks, differential, hdr
#define X393_CMPRS_CBIT_CMODE_JP4DIFFDIV2 0x00000009 // jp4, 4 blocks, differential, divide by 2
#define X393_CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 0x0000000a // jp4, 4 blocks, differential, hdr,divide by 2
#define X393_CMPRS_CBIT_CMODE_MONO1 0x0000000b // Mono JPEG (not yet implemented)
#define X393_CMPRS_CBIT_CMODE_MONO4 0x0000000e // Mono, 4 blocks (2x2 macroblocks)
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0
#define X393_CMPRS_CBIT_FRAMES_SINGLE 0x00000000 // Use single-frame buffer
#define X393_CMPRS_CBIT_FRAMES_MULTI 0x00000001 // Use multi-frame buffer
// Compressor control
void x393_cmprs_control_reg (x393_cmprs_mode_t d, int cmprs_chn); // Program compressor channel operation mode
void set_x393_cmprs_status (x393_status_ctrl_t d, int cmprs_chn); // Setup compressor status report mode
x393_status_ctrl_t get_x393_cmprs_status (int cmprs_chn);
void set_x393_cmprs_format (x393_cmprs_frame_format_t d, int cmprs_chn); // Compressor frame format
x393_cmprs_frame_format_t get_x393_cmprs_format (int cmprs_chn);
void set_x393_cmprs_color_saturation (x393_cmprs_colorsat_t d, int cmprs_chn); // Compressor color saturation
x393_cmprs_colorsat_t get_x393_cmprs_color_saturation (int cmprs_chn);
void set_x393_cmprs_coring_mode (x393_cmprs_coring_mode_t d, int cmprs_chn); // Select coring mode
x393_cmprs_coring_mode_t get_x393_cmprs_coring_mode (int cmprs_chn);
void x393_cmprs_interrupts (x393_cmprs_interrupts_t d, int cmprs_chn); // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable)
// Compressor tables load control
// Several tables can be loaded to the compressor, there are 4 types of them:
// 0:quantization tables - 8 pairs can be loaded and switched at run time,
// 1:coring tables - 8 pairs can be loaded and switched at run time,
// 2:focusing tables - 15 tables can be loaded and switched at run time (16-th table address space
// is used to program other focusing mode parameters,
// 3:Huffman tables - 1 pair tables can be loaded
// Default tables are loaded with the bitstream file (100% quality for quantization table 0
// Loading a table requires to load address of the beginning of data, it includes table type and optional offset
// when multiple tables of the same type are used. Next the data should be written to the same register address,
// the table address is auto-incremented,
// Data for the tables 0..2 should be combined: two items into a single 32-bit DWORD (little endian), treating
// each item as a 16-bit word. The Huffman table is one item per DWORD. Address offset is calculated in DWORDs
// Compressor table types
#define X393_TABLE_QUANTIZATION_TYPE 0x00000000 // Quantization table type
#define X393_TABLE_CORING_TYPE 0x00000001 // Coring table type
#define X393_TABLE_FOCUS_TYPE 0x00000002 // Focus table type
#define X393_TABLE_HUFFMAN_TYPE 0x00000003 // Huffman table type
// Compressor tables control
void x393_cmprs_tables_data (u32 d, int cmprs_chn); // Compressor tables data
void x393_cmprs_tables_address (x393_cmprs_table_addr_t d, int cmprs_chn); // Compressor tables type/address
// Compressor channel status)
x393_cmprs_status_t x393_cmprs_status (int chn); // Status of the compressor channel (incl. interrupt
u32 x393_cmprs_hifreq (int chn); // Focus helper high-frequency amount
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
// serving all 4 compressor channels through its input ports. Below afi_port (0..3) references to one of the 4 ports of each. Control
// for two AXI HP channels is implemented as separate functions. Currently only the first channel is used
void x393_afimux0_en (x393_afimux_en_t d); // AFI MUX 0 global/port run/pause control
void set_x393_afimux0_rst (x393_afimux_rst_t d); // AFI MUX 0 per-port resets
x393_afimux_rst_t get_x393_afimux0_rst (void);
void x393_afimux0_report_mode (x393_afimux_report_t d); // AFI MUX 0 readout pointer report mode
void set_x393_afimux0_status_control (x393_status_ctrl_t d); // AFI MUX 0 status report mode
x393_status_ctrl_t get_x393_afimux0_status_control (void);
void set_x393_afimux0_sa (x393_afimux_sa_t d, int afi_port); // AFI MUX 0 DMA buffer start address in 32-byte blocks
x393_afimux_sa_t get_x393_afimux0_sa (int afi_port);
void set_x393_afimux0_len (x393_afimux_len_t d, int afi_port); // AFI MUX 0 DMA buffer length in 32-byte blocks
x393_afimux_len_t get_x393_afimux0_len (int afi_port);
// Same for the second AXI HP channel (not currently used)
void x393_afimux1_en (x393_afimux_en_t d); // AFI MUX 1 global/port run/pause control
void set_x393_afimux1_rst (x393_afimux_rst_t d); // AFI MUX 1 per-port resets
x393_afimux_rst_t get_x393_afimux1_rst (void);
void x393_afimux1_report_mode (x393_afimux_report_t d); // AFI MUX 1 readout pointer report mode
void set_x393_afimux1_status_control (x393_status_ctrl_t d); // AFI MUX 1 status report mode
x393_status_ctrl_t get_x393_afimux1_status_control (void);
void set_x393_afimux1_sa (x393_afimux_sa_t d, int afi_port); // AFI MUX 1 DMA buffer start address in 32-byte blocks
x393_afimux_sa_t get_x393_afimux1_sa (int afi_port);
void set_x393_afimux1_len (x393_afimux_len_t d, int afi_port); // AFI MUX 1 DMA buffer length in 32-byte blocks
x393_afimux_len_t get_x393_afimux1_len (int afi_port);
// Read-only sensors status information (pointer offset and last sequence number)
x393_afimux_status_t x393_afimux0_status (int afi_port); // Status of the AFI MUX 0 (including image pointer)
x393_afimux_status_t x393_afimux1_status (int afi_port); // Status of the AFI MUX 1 (including image pointer)
//
// GPIO contol. Each of the 10 pins can be controlled by the software - individually or simultaneously or from any of the 3 masters (other FPGA modules)
// Currently these modules are;
// A - camsync (intercamera synchronization), uses up to 4 pins
// B - reserved (not yet used) and
// C - logger (IMU, GPS, images), uses 6 pins, including separate i2c available on extension boards
// If several enabled ports try to contol the same bit, highest priority has port C, lowest - software controlled
void x393_gpio_set_pins (x393_gpio_set_pins_t d); // State of the GPIO pins and seq. number
void set_x393_gpio_status_control (x393_status_ctrl_t d); // GPIO status control mode
x393_status_ctrl_t get_x393_gpio_status_control (void);
// Read-only GPIO pins state
x393_gpio_status_t x393_gpio_status (void); // State of the GPIO pins and seq. number
// RTC control
void set_x393_rtc_usec (x393_rtc_usec_t d); // RTC microseconds
x393_rtc_usec_t get_x393_rtc_usec (void);
void set_x393_rtc_sec_set (x393_rtc_sec_t d); // RTC seconds and set clock
x393_rtc_sec_t get_x393_rtc_sec_set (void);
void set_x393_rtc_corr (x393_rtc_corr_t d); // RTC correction (+/- 1/256 full scale)
x393_rtc_corr_t get_x393_rtc_corr (void);
void set_x393_rtc_set_status (x393_status_ctrl_t d); // RTC status control mode, write makes a snapshot to be read out
x393_status_ctrl_t get_x393_rtc_set_status (void);
// Read-only RTC state
x393_rtc_status_t x393_rtc_status (void); // RTC status reg
x393_rtc_sec_t x393_rtc_status_sec (void); // RTC snapshot seconds
x393_rtc_usec_t x393_rtc_status_usec (void); // RTC snapshot microseconds
// CAMSYNC control
void x393_camsync_mode (x393_camsync_mode_t d); // CAMSYNC mode
void x393_camsync_trig_src (x393_camsync_io_t d); // CAMSYNC trigger source
void x393_camsync_trig_dst (x393_camsync_io_t d); // CAMSYNC trigger destination
// Trigger period has special value for small (<255) values written to this register
// d == 0 - disable (stop periodic mode)
// d == 1 - single trigger
// d == 2..255 - set output pulse / input-output serial bit duration (no start generated)
// d >= 256 - repetitive trigger
void set_x393_camsync_trig_period (u32 d); // CAMSYNC trigger period
u32 get_x393_camsync_trig_period (void);
void set_x393_camsync_trig_delay (u32 d, int sens_chn); // CAMSYNC trigger delay
u32 get_x393_camsync_trig_delay (int sens_chn);
// Command sequencer control
// Controller is programmed through 32 locations. Each registers but the control require two writes:
// First write - register address (AXI_WR_ADDR_BITS bits), second - register data (32 bits)
// Writing to the contol register (0x1f) resets the first/second counter so the next write will be "first"
// 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame
// "just missed" - in that case data will go to the current frame.
// 0x10 - write seq commands to be sent ASAP
// 0x11 - write seq commands to be sent after the next frame starts
//
// 0x1e - write seq commands to be sent after the next 14 frame start pulses
// 0x1f - control register:
// [14] - reset all FIFO (takes 32 clock pulses), also - stops seq until run command
// [13:12] - 3 - run seq, 2 - stop seq , 1,0 - no change to run state
// [1:0] - 0: NOP, 1: clear IRQ, 2 - Clear IE, 3: set IE
void x393_cmdframeseq_ctrl (x393_cmdframeseq_mode_t d, int sens_chn); // CMDFRAMESEQ control register
void x393_cmdframeseq_abs (u32 d, int sens_chn, int offset); // CMDFRAMESEQ absolute frame address/command
void x393_cmdframeseq_rel (u32 d, int sens_chn, int offset); // CMDFRAMESEQ relative frame address/command
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
void set_x393_cmdseqmux_status_ctrl (x393_status_ctrl_t d); // CMDSEQMUX status control mode (status provides current frame numbers)
x393_status_ctrl_t get_x393_cmdseqmux_status_ctrl (void);
x393_cmdseqmux_status_t x393_cmdseqmux_status (void); // CMDSEQMUX status data (frame numbers and interrupts
// Event logger
// Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.
// Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.
// Register pages:
#define X393_LOGGER_PAGE_CONF 0x00000000 // Logger configuration page
#define X393_LOGGER_PAGE_IMU 0x00000003 // Logger IMU parameters page
#define X393_LOGGER_PAGE_GPS 0x00000001 // Logger GPS parameters page
#define X393_LOGGER_PAGE_MSG 0x00000002 // Logger MSG (odometer) parameters page
// Register configuration addresses (with X393_LOGGER_PAGE_CONF):
#define X393_LOGGER_PERIOD 0x00000000 // IMU period (in SPI clocks, high word 0xffff - use IMU ready)
#define X393_LOGGER_BIT_DURATION 0x00000001 // IMU SPI bit duration (in mclk == 50 ns periods?)
#define X393_LOGGER_BIT_HALF_PERIOD 0x00000002 // Logger rs232 half bit period (in mclk == 50 ns periods?)
#define X393_LOGGER_CONFIG 0x00000003 // Logger IMU parameters page
void set_x393_logger_status_ctrl (x393_status_ctrl_t d); // Logger status configuration (to report sample number)
x393_status_ctrl_t get_x393_logger_status_ctrl (void);
void x393_logger_data (x393_logger_data_t d); // Logger register write data
void x393_logger_address (x393_logger_address_t d); // Logger register write page/address
x393_logger_status_t x393_logger_status (void); // Logger status data (sequence number)
// MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger
void set_x393_mult_saxi_status_ctrl (x393_status_ctrl_t d); // MULT_SAXI status control mode (status provides current DWORD pointer)
x393_status_ctrl_t get_x393_mult_saxi_status_ctrl (void);
void x393_mult_saxi_buf_address (x393_mult_saxi_al_t d, int chn); // MULT_SAXI buffer start address in DWORDS
void x393_mult_saxi_buf_len (x393_mult_saxi_al_t d, int chn); // MULT_SAXI buffer length in DWORDS
x393_mult_saxi_al_t x393_mult_saxi_status (int chn); // MULT_SAXI current DWORD pointer
// MULTI_CLK - global clock generation PLLs. Interface provided for debugging, no interaction is needed for normal operation
void set_x393_multiclk_status_ctrl (x393_status_ctrl_t d); // MULTI_CLK status generation (do not use or do not set auto)
x393_status_ctrl_t get_x393_multiclk_status_ctrl (void);
void set_x393_multiclk_ctrl (x393_multiclk_ctl_t d); // MULTI_CLK reset and power down control
x393_multiclk_ctl_t get_x393_multiclk_ctrl (void);
x393_multiclk_status_t x393_multiclk_status (void); // MULTI_CLK lock and toggle state
// Debug ring module
// Debug ring module (when enabled with DEBUG_RING in system_defines.vh) provides low-overhead read/write access to internal test points
// To write data you need to write 32-bit data with x393_debug_shift(u32) multiple times to fill the ring register (length depends on
// implementation), skip this step if only reading from the modules under test is required.
// Exchange data with x393_debug_load(), the data from the ring shift register.
// Write 0xffffffff (or other "magic" data) if the ring length is unknown - this DWORD will appear on the output after the useful data
// Read all data, waiting for status sequence number to be incremented,status mode should be set to auto (3) wor each DWORD certain
// number of times or until the "magic" DWORD appears, writing "magic" to shift out next 32 bits.
void set_x393_debug_status_ctrl (x393_status_ctrl_t d); // Debug ring status generation - set to auto(3) if used
x393_status_ctrl_t get_x393_debug_status_ctrl (void);
void x393_debug_load (void); // Debug ring copy shift register to/from tested modules
void x393_debug_shift (u32 d); // Debug ring shift ring by 32 bits
x393_debug_status_t x393_debug_status (void); // Debug read status (watch sequence number)
u32 x393_debug_read (void); // Debug read DWORD form ring register
// Write-only addresses to program memory channel 3 (test channel)
void x393_mcntrl_chn3_scanline_mode (x393_mcntrl_mode_scan_t d); // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn3_scanline_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn3_scanline_status_cntrl(void);
void x393_mcntrl_chn3_scanline_startaddr (x393_mcntrl_window_frame_sa_t d); // Set frame start address
void x393_mcntrl_chn3_scanline_frame_size(x393_mcntrl_window_frame_sa_inc_t d); // Set frame size (address increment)
void x393_mcntrl_chn3_scanline_frame_last(x393_mcntrl_window_last_frame_num_t d); // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn3_scanline_frame_full_width(x393_mcntrl_window_full_width_t d); // Set frame full(padded) width
void x393_mcntrl_chn3_scanline_window_wh (x393_mcntrl_window_width_height_t d); // Set frame window size
void x393_mcntrl_chn3_scanline_window_x0y0(x393_mcntrl_window_left_top_t d); // Set frame position
void x393_mcntrl_chn3_scanline_startxy (x393_mcntrl_window_startx_starty_t d); // Set startXY register
// Write-only addresses to program memory channel 2 (test channel)
void x393_mcntrl_chn2_tiled_mode (x393_mcntrl_mode_scan_t d); // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn2_tiled_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn2_tiled_status_cntrl(void);
void x393_mcntrl_chn2_tiled_startaddr (x393_mcntrl_window_frame_sa_t d); // Set frame start address
void x393_mcntrl_chn2_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d); // Set frame size (address increment)
void x393_mcntrl_chn2_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d); // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn2_tiled_frame_full_width(x393_mcntrl_window_full_width_t d); // Set frame full(padded) width
void x393_mcntrl_chn2_tiled_window_wh (x393_mcntrl_window_width_height_t d); // Set frame window size
void x393_mcntrl_chn2_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d); // Set frame position
void x393_mcntrl_chn2_tiled_startxy (x393_mcntrl_window_startx_starty_t d); // Set startXY register
void x393_mcntrl_chn2_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d); // Set tile size/step (tiled mode only)
// Write-only addresses to program memory channel 4 (test channel)
void x393_mcntrl_chn4_tiled_mode (x393_mcntrl_mode_scan_t d); // Set mode register (write last after other channel registers are set)
void set_x393_mcntrl_chn4_tiled_status_cntrl(x393_status_ctrl_t d); // Set status control register (status update mode)
x393_status_ctrl_t get_x393_mcntrl_chn4_tiled_status_cntrl(void);
void x393_mcntrl_chn4_tiled_startaddr (x393_mcntrl_window_frame_sa_t d); // Set frame start address
void x393_mcntrl_chn4_tiled_frame_size (x393_mcntrl_window_frame_sa_inc_t d); // Set frame size (address increment)
void x393_mcntrl_chn4_tiled_frame_last (x393_mcntrl_window_last_frame_num_t d); // Set last frame number (number of frames in buffer minus 1)
void x393_mcntrl_chn4_tiled_frame_full_width(x393_mcntrl_window_full_width_t d); // Set frame full(padded) width
void x393_mcntrl_chn4_tiled_window_wh (x393_mcntrl_window_width_height_t d); // Set frame window size
void x393_mcntrl_chn4_tiled_window_x0y0 (x393_mcntrl_window_left_top_t d); // Set frame position
void x393_mcntrl_chn4_tiled_startxy (x393_mcntrl_window_startx_starty_t d); // Set startXY register
void x393_mcntrl_chn4_tiled_tile_whs (x393_mcntrl_window_tile_whs_t d); // Set tile size/step (tiled mode only)
py393/generated/x393_defs.h deleted 100644 → 0
View file @ 901020c6
/*******************************************************************************
* File: x393_defs.h
* Date: 2016-03-29
* Author: auto-generated file, see x393_export_c.py
* Description: Constants and hardware addresses definitions to access x393 hardware registers
*******************************************************************************/
// R/W addresses to set up memory arbiter priorities. For sensors (chn = 8..11), for compressors - 12..15
#define X393_MCNTRL_ARBITER_PRIORITY(chn) (0x40000180 + 0x4 * (chn)) // Set memory arbiter priority (currently r/w, may become just wo), chn = 0..15, data type: x393_arbite_pri_t (rw)
// Enable/disable memory channels (bits in a 16-bit word). For sensors (chn = 8..11), for compressors - 12..15
#define X393_MCNTRL_CHN_EN 0x400001c0 // Enable/disable memory channels (currently r/w, may become just wo), data type: x393_mcntr_chn_en_t (rw)
#define X393_MCNTRL_DQS_DQM_PATT 0x40000140 // Setup DQS and DQM patterns, data type: x393_mcntr_dqs_dqm_patt_t (rw)
#define X393_MCNTRL_DQ_DQS_TRI 0x40000144 // Setup DQS and DQ on/off sequence, data type: x393_mcntr_dqs_dqm_tri_t (rw)
// Following enable/disable addresses can be written with any data, only addresses matter
#define X393_MCNTRL_DIS 0x400000c0 // Disable DDR3 memory controller
#define X393_MCNTRL_EN 0x400000c4 // Enable DDR3 memory controller
#define X393_MCNTRL_REFRESH_DIS 0x400000c8 // Disable DDR3 memory refresh
#define X393_MCNTRL_REFRESH_EN 0x400000cc // Enable DDR3 memory refresh
#define X393_MCNTRL_SDRST_DIS 0x40000098 // Disable DDR3 memory reset
#define X393_MCNTRL_SDRST_EN 0x4000009c // Enable DDR3 memory reset
#define X393_MCNTRL_CKE_DIS 0x400000a0 // Disable DDR3 memory CKE
#define X393_MCNTRL_CKE_EN 0x400000a4 // Enable DDR3 memory CKE
#define X393_MCNTRL_CMDA_DIS 0x40000090 // Disable DDR3 memory command/address lines
#define X393_MCNTRL_CMDA_EN 0x40000094 // Enable DDR3 memory command/address lines
// Set DDR3 memory controller I/O delays and other timing parameters (should use individually calibrated values)
#define X393_MCNTRL_DQ_ODLY0(chn) (0x40000200 + 0x4 * (chn)) // Lane0 DQ output delays , chn = 0..7, data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_ODLY1(chn) (0x40000280 + 0x4 * (chn)) // Lane1 DQ output delays , chn = 0..7, data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY0(chn) (0x40000240 + 0x4 * (chn)) // Lane0 DQ input delays , chn = 0..7, data type: x393_dly_t (rw)
#define X393_MCNTRL_DQ_IDLY1(chn) (0x400002c0 + 0x4 * (chn)) // Lane1 DQ input delays , chn = 0..7, data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_ODLY0 0x40000220 // Lane0 DQS output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_ODLY1 0x400002a0 // Lane1 DQS output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_IDLY0 0x40000260 // Lane0 DQS input delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DQS_IDLY1 0x400002e0 // Lane1 DQS input delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DM_ODLY0 0x40000224 // Lane0 DM output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DM_ODLY1 0x400002a4 // Lane1 DM output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY(chn) (0x40000300 + 0x4 * (chn)) // Address, bank and commands delays, chn = 0..31, data type: x393_dly_t (rw)
#define X393_MCNTRL_PHASE 0x40000380 // Clock phase, data type: x393_dly_t (rw)
#define X393_MCNTRL_DLY_SET 0x40000080 // Set all pre-programmed delays
#define X393_MCNTRL_WBUF_DLY 0x40000148 // Set write buffer delay, data type: x393_wbuf_dly_t (rw)
// Write-only addresses to program memory channels for sensors (chn = 0..3), memory channels 8..11
#define X393_SENS_MCNTRL_SCANLINE_MODE(chn) (0x40001a00 + 0x40 * (chn)) // Set mode register (write last after other channel registers are set), chn = 0..3, data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL(chn) (0x40001a04 + 0x40 * (chn)) // Set status control register (status update mode), chn = 0..3, data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_SCANLINE_STARTADDR(chn) (0x40001a08 + 0x40 * (chn)) // Set frame start address, chn = 0..3, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_SIZE(chn) (0x40001a0c + 0x40 * (chn)) // Set frame size (address increment), chn = 0..3, data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_LAST(chn) (0x40001a10 + 0x40 * (chn)) // Set last frame number (number of frames in buffer minus 1), chn = 0..3, data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_FRAME_FULL_WIDTH(chn) (0x40001a14 + 0x40 * (chn)) // Set frame full(padded) width, chn = 0..3, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_WH(chn) (0x40001a18 + 0x40 * (chn)) // Set frame window size, chn = 0..3, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_WINDOW_X0Y0(chn) (0x40001a1c + 0x40 * (chn)) // Set frame position, chn = 0..3, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_SCANLINE_STARTXY(chn) (0x40001a20 + 0x40 * (chn)) // Set startXY register, chn = 0..3, data type: x393_mcntrl_window_startx_starty_t (wo)
// Write-only addresses to program memory channels for compressors (chn = 0..3), memory channels 12..15
#define X393_SENS_MCNTRL_TILED_MODE(chn) (0x40001b00 + 0x40 * (chn)) // Set mode register (write last after other channel registers are set), chn = 0..3, data type: x393_mcntrl_mode_scan_t (wo)
#define X393_SENS_MCNTRL_TILED_STATUS_CNTRL(chn) (0x40001b04 + 0x40 * (chn)) // Set status control register (status update mode), chn = 0..3, data type: x393_status_ctrl_t (rw)
#define X393_SENS_MCNTRL_TILED_STARTADDR(chn) (0x40001b08 + 0x40 * (chn)) // Set frame start address, chn = 0..3, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_SIZE(chn) (0x40001b0c + 0x40 * (chn)) // Set frame size (address increment), chn = 0..3, data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_LAST(chn) (0x40001b10 + 0x40 * (chn)) // Set last frame number (number of frames in buffer minus 1), chn = 0..3, data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_SENS_MCNTRL_TILED_FRAME_FULL_WIDTH(chn) (0x40001b14 + 0x40 * (chn)) // Set frame full(padded) width, chn = 0..3, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_WH(chn) (0x40001b18 + 0x40 * (chn)) // Set frame window size, chn = 0..3, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_SENS_MCNTRL_TILED_WINDOW_X0Y0(chn) (0x40001b1c + 0x40 * (chn)) // Set frame position, chn = 0..3, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_SENS_MCNTRL_TILED_STARTXY(chn) (0x40001b20 + 0x40 * (chn)) // Set startXY register, chn = 0..3, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_SENS_MCNTRL_TILED_TILE_WHS(chn) (0x40001b24 + 0x40 * (chn)) // Set tile size/step (tiled mode only), chn = 0..3, data type: x393_mcntrl_window_tile_whs_t (wo)
// Write-only addresses to program memory channel for membridge, memory channel 1
#define X393_MEMBRIDGE_SCANLINE_MODE 0x40000480 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MEMBRIDGE_SCANLINE_STATUS_CNTRL 0x40000484 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MEMBRIDGE_SCANLINE_STARTADDR 0x40000488 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_SIZE 0x4000048c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_LAST 0x40000490 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MEMBRIDGE_SCANLINE_FRAME_FULL_WIDTH 0x40000494 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MEMBRIDGE_SCANLINE_WINDOW_WH 0x40000498 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MEMBRIDGE_SCANLINE_WINDOW_X0Y0 0x4000049c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MEMBRIDGE_SCANLINE_STARTXY 0x400004a0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_MEMBRIDGE_CTRL 0x40000800 // Issue membridge command, data type: x393_membridge_cmd_t (wo)
#define X393_MEMBRIDGE_STATUS_CNTRL 0x40000804 // Set membridge status control register, data type: x393_status_ctrl_t (rw)
#define X393_MEMBRIDGE_LO_ADDR64 0x40000808 // start address of the system memory range in QWORDs (4 LSBs==0), data type: u29_t (wo)
#define X393_MEMBRIDGE_SIZE64 0x4000080c // size of the system memory range in QWORDs (4 LSBs==0), rolls over, data type: u29_t (wo)
#define X393_MEMBRIDGE_START64 0x40000810 // start of transfer offset to system memory range in QWORDs (4 LSBs==0), data type: u29_t (wo)
#define X393_MEMBRIDGE_LEN64 0x40000814 // Full length of transfer in QWORDs, data type: u29_t (wo)
#define X393_MEMBRIDGE_WIDTH64 0x40000818 // Frame width in QWORDs (last xfer in each line may be partial), data type: u29_t (wo)
#define X393_MEMBRIDGE_MODE 0x4000081c // AXI cache mode, data type: x393_membridge_mode_t (wo)
// Write-only addresses to PS PIO (Software generated DDR3 memory access sequences)
#define X393_MCNTRL_PS_EN_RST 0x40000400 // Set PS PIO enable and reset, data type: x393_ps_pio_en_rst_t (wo)
#define X393_MCNTRL_PS_CMD 0x40000404 // Set PS PIO commands, data type: x393_ps_pio_cmd_t (wo)
#define X393_MCNTRL_PS_STATUS_CNTRL 0x40000408 // Set PS PIO status control register (status update mode), data type: x393_status_ctrl_t (rw)
// Write-only addresses to to program status report mode for memory controller
#define X393_MCONTR_PHY_STATUS_CNTRL 0x40000150 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCONTR_TOP_16BIT_STATUS_CNTRL 0x4000014c // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
// Write-only addresses to to program status report mode for test channels
#define X393_MCNTRL_TEST01_CHN2_STATUS_CNTRL 0x400003d4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_TEST01_CHN3_STATUS_CNTRL 0x400003dc // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_TEST01_CHN4_STATUS_CNTRL 0x400003e4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
// Write-only addresses for test channels commands
#define X393_MCNTRL_TEST01_CHN2_MODE 0x400003d0 // Set command for test01 channel 2, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN3_MODE 0x400003d8 // Set command for test01 channel 3, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN4_MODE 0x400003e0 // Set command for test01 channel 4, data type: x393_test01_mode_t (wo)
// Read-only addresses for status information
#define X393_MCONTR_PHY_STATUS 0x40002000 // Status register for MCNTRL PHY, data type: x393_status_mcntrl_phy_t (ro)
#define X393_MCONTR_TOP_STATUS 0x40002004 // Status register for MCNTRL requests, data type: x393_status_mcntrl_top_t (ro)
#define X393_MCNTRL_PS_STATUS 0x40002008 // Status register for MCNTRL software R/W, data type: x393_status_mcntrl_ps_t (ro)
#define X393_MCNTRL_CHN1_STATUS 0x40002010 // Status register for MCNTRL CHN1 (membridge), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN3_STATUS 0x40002018 // Status register for MCNTRL CHN3 (scanline), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN2_STATUS 0x40002014 // Status register for MCNTRL CHN2 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN4_STATUS 0x4000201c // Status register for MCNTRL CHN4 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_TEST01_CHN2_STATUS 0x400020f4 // Status register for test channel 2, data type: x393_status_mcntrl_testchn_t (ro)
#define X393_TEST01_CHN3_STATUS 0x400020f8 // Status register for test channel 3, data type: x393_status_mcntrl_testchn_t (ro)
#define X393_TEST01_CHN4_STATUS 0x400020fc // Status register for test channel 4, data type: x393_status_mcntrl_testchn_t (ro)
#define X393_MEMBRIDGE_STATUS 0x400020ec // Status register for membridge, data type: x393_status_membridge_t (ro)
// Write-only control of the sensor channels
#define X393_SENS_MODE(sens_num) (0x40001000 + 0x100 * (sens_num)) // Write sensor channel mode, sens_num = 0..3, data type: x393_sens_mode_t (wo)
#define X393_SENSI2C_CTRL(sens_num) (0x40001008 + 0x100 * (sens_num)) // Control sensor i2c, write i2c LUT, sens_num = 0..3, data type: x393_i2c_ctltbl_t (wo)
#define X393_SENSI2C_STATUS_CTRL(sens_num) (0x4000100c + 0x100 * (sens_num)) // Setup sensor i2c status report mode, sens_num = 0..3, data type: x393_status_ctrl_t (rw)
#define X393_SENS_SYNC_MULT(sens_num) (0x40001018 + 0x100 * (sens_num)) // Configure frames combining, sens_num = 0..3, data type: x393_sens_sync_mult_t (wo)
#define X393_SENS_SYNC_LATE(sens_num) (0x4000101c + 0x100 * (sens_num)) // Configure frame sync delay, sens_num = 0..3, data type: x393_sens_sync_late_t (wo)
#define X393_SENSIO_CTRL(sens_num) (0x40001020 + 0x100 * (sens_num)) // Configure sensor I/O port, sens_num = 0..3, data type: x393_sensio_ctl_t (wo)
#define X393_SENSIO_STATUS_CNTRL(sens_num) (0x40001024 + 0x100 * (sens_num)) // Set status control for SENSIO module, sens_num = 0..3, data type: x393_status_ctrl_t (rw)
#define X393_SENSIO_JTAG(sens_num) (0x40001028 + 0x100 * (sens_num)) // Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS), sens_num = 0..3, data type: x393_sensio_jpag_t (wo)
#define X393_SENSIO_WIDTH(sens_num) (0x4000102c + 0x100 * (sens_num)) // Set sensor line in pixels (0 - use line sync from the sensor), sens_num = 0..3, data type: x393_sensio_width_t (rw)
#define X393_SENSIO_TIM0(sens_num) (0x40001030 + 0x100 * (sens_num)) // Sensor port i/o timing configuration, register 0, sens_num = 0..3, data type: x393_sensio_tim0_t (rw)
#define X393_SENSIO_TIM1(sens_num) (0x40001034 + 0x100 * (sens_num)) // Sensor port i/o timing configuration, register 1, sens_num = 0..3, data type: x393_sensio_tim1_t (rw)
#define X393_SENSIO_TIM2(sens_num) (0x40001038 + 0x100 * (sens_num)) // Sensor port i/o timing configuration, register 2, sens_num = 0..3, data type: x393_sensio_tim2_t (rw)
#define X393_SENSIO_TIM3(sens_num) (0x4000103c + 0x100 * (sens_num)) // Sensor port i/o timing configuration, register 3, sens_num = 0..3, data type: x393_sensio_tim3_t (rw)
// I2C command sequencer, block of 16 DWORD slots for absolute frame numbers (modulo 16) and 15 slots for relative ones
// 0 - ASAP, 1 next frame, 14 -14-th next.
// Data written depends on context:
// 1 - I2C register write: index page (MSB), 3 payload bytes. Payload bytes are used according to table and sent
// after the slave address and optional high address byte. Other bytes are sent in descending order (LSB- last).
// If less than 4 bytes are programmed in the table the high bytes (starting with the one from the table) are
// skipped.
// If more than 4 bytes are programmed in the table for the page (high byte), one or two next 32-bit words
// bypass the index table and all 4 bytes are considered payload ones. If less than 4 extra bytes are to be
// sent for such extra word, only the lower bytes are sent.
//
// 2 - I2C register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
// in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
// read address in the table is programmed to be a single-byte one
#define X393_SENSI2C_ABS(sens_num,offset) (0x40001040)+ 0x40 * (sens_num)+ 0x1 * (offset)) // Write sensor i2c sequencer, sens_num = 0..3, offset = 0..15, data type: u32 (wo)
#define X393_SENSI2C_REL(sens_num,offset) (0x40001080)+ 0x40 * (sens_num)+ 0x1 * (offset)) // Write sensor i2c sequencer, sens_num = 0..3, offset = 0..15, data type: u32 (wo)
// Lens vignetting correction (for each sub-frame separately)
#define X393_LENS_HEIGHT0_M1(sens_num) (0x400010f0 + 0x100 * (sens_num)) // Subframe 0 height minus 1, sens_num = 0..3, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT1_M1(sens_num) (0x400010f4 + 0x100 * (sens_num)) // Subframe 1 height minus 1, sens_num = 0..3, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_HEIGHT2_M1(sens_num) (0x400010f8 + 0x100 * (sens_num)) // Subframe 2 height minus 1, sens_num = 0..3, data type: x393_lens_height_m1_t (rw)
#define X393_LENS_CORR_CNH_ADDR_DATA(sens_num) (0x400010fc + 0x100 * (sens_num)) // Combined address/data to write lens vignetting correction coefficients, sens_num = 0..3, data type: x393_lens_corr_t (wo)
// Lens vignetting coefficient addresses - use with x393_lens_corr_wo_t (X393_LENS_CORR_CNH_ADDR_DATA)
#define X393_LENS_AX 0x00000000 // Address of correction parameter Ax
#define X393_LENS_AX_MASK 0x000000f8 // Correction parameter Ax mask
#define X393_LENS_AY 0x00000008 // Address of correction parameter Ay
#define X393_LENS_AY_MASK 0x000000f8 // Correction parameter Ay mask
#define X393_LENS_C 0x00000010 // Address of correction parameter C
#define X393_LENS_C_MASK 0x000000f8 // Correction parameter C mask
#define X393_LENS_BX 0x00000020 // Address of correction parameter Bx
#define X393_LENS_BX_MASK 0x000000e0 // Correction parameter Bx mask
#define X393_LENS_BY 0x00000040 // Address of correction parameter By
#define X393_LENS_BY_MASK 0x000000e0 // Correction parameter By mask
#define X393_LENS_SCALE0 0x00000060 // Address of correction parameter scale0
#define X393_LENS_SCALE1 0x00000062 // Address of correction parameter scale1
#define X393_LENS_SCALE2 0x00000064 // Address of correction parameter scale2
#define X393_LENS_SCALE3 0x00000066 // Address of correction parameter scale3
#define X393_LENS_SCALES_MASK 0x000000f8 // Common mask for scales
#define X393_LENS_FAT0_IN 0x00000068 // Address of input fat zero parameter (to subtract from input)
#define X393_LENS_FAT0_IN_MASK 0x000000ff // Mask for fat zero input parameter
#define X393_LENS_FAT0_OUT 0x00000069 // Address of output fat zero parameter (to add to output)
#define X393_LENS_FAT0_OUT_MASK 0x000000ff // Mask for fat zero output parameters
#define X393_LENS_POST_SCALE 0x0000006a // Address of post scale (shift output) parameter
#define X393_LENS_POST_SCALE_MASK 0x000000ff // Mask for post scale parameter
// Sensor gamma conversion control (See Python code for examples of the table data generation)
#define X393_SENS_GAMMA_CTRL(sens_num) (0x400010e0 + 0x100 * (sens_num)) // Gamma module control, sens_num = 0..3, data type: x393_gamma_ctl_t (rw)
#define X393_SENS_GAMMA_TBL(sens_num) (0x400010e4 + 0x100 * (sens_num)) // Write sensor gamma table address/data (with autoincrement), sens_num = 0..3, data type: x393_gamma_tbl_t (wo)
#define X393_SENS_GAMMA_HEIGHT01M1(sens_num) (0x400010e8 + 0x100 * (sens_num)) // Gamma module subframes 0,1 heights minus 1, sens_num = 0..3, data type: x393_gamma_height01m1_t (rw)
#define X393_SENS_GAMMA_HEIGHT2M1(sens_num) (0x400010ec + 0x100 * (sens_num)) // Gamma module subframe 2 height minus 1, sens_num = 0..3, data type: x393_gamma_height2m1_t (rw)
// Windows for histogram subchannels
#define X393_HISTOGRAM_LT0(sens_num) (0x400010c0 + 0x100 * (sens_num)) // Specify histogram 0 left/top, sens_num = 0..3, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH0(sens_num) (0x400010c4 + 0x100 * (sens_num)) // Specify histogram 0 width/height, sens_num = 0..3, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT1(sens_num) (0x400010c8 + 0x100 * (sens_num)) // Specify histogram 1 left/top, sens_num = 0..3, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH1(sens_num) (0x400010cc + 0x100 * (sens_num)) // Specify histogram 1 width/height, sens_num = 0..3, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT2(sens_num) (0x400010d0 + 0x100 * (sens_num)) // Specify histogram 2 left/top, sens_num = 0..3, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH2(sens_num) (0x400010d4 + 0x100 * (sens_num)) // Specify histogram 2 width/height, sens_num = 0..3, data type: x393_hist_width_height_m1_t (rw)
#define X393_HISTOGRAM_LT3(sens_num) (0x400010d8 + 0x100 * (sens_num)) // Specify histogram 3 left/top, sens_num = 0..3, data type: x393_hist_left_top_t (rw)
#define X393_HISTOGRAM_WH3(sens_num) (0x400010dc + 0x100 * (sens_num)) // Specify histogram 3 width/height, sens_num = 0..3, data type: x393_hist_width_height_m1_t (rw)
// DMA control for the histograms. Subchannel here is 4*sensor_port+ histogram_subchannel
#define X393_HIST_SAXI_MODE 0x40001440 // Histogram DMA operation mode, data type: x393_hist_saxi_mode_t (rw)
#define X393_HIST_SAXI_ADDR(subchannel) (0x40001400 + 0x4 * (subchannel)) // Histogram DMA addresses (in 4096 byte pages), subchannel = 0..15, data type: x393_hist_saxi_addr_t (rw)
// Read-only addresses for sensors status information
#define X393_SENSI2C_STATUS(sens_num) (0x40002080 + 0x8 * (sens_num)) // Status of the sensors i2c, sens_num = 0..3, data type: x393_status_sens_i2c_t (ro)
#define X393_SENSIO_STATUS(sens_num) (0x40002084 + 0x8 * (sens_num)) // Status of the sensor ports I/O pins, sens_num = 0..3, data type: x393_status_sens_io_t (ro)
// Compressor bitfields values
#define X393_CMPRS_CBIT_RUN_RST 0x00000000 // Reset compressor, stop immediately
#define X393_CMPRS_CBIT_RUN_DISABLE 0x00000001 // Disable compression of the new frames, finish any already started
#define X393_CMPRS_CBIT_RUN_STANDALONE 0x00000002 // Enable compressor, compress single frame from memory (async)
#define X393_CMPRS_CBIT_RUN_ENABLE 0x00000003 // Enable synchronous compression mode
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0 3x3 de-bayer core
#define X393_CMPRS_CBIT_CMODE_MONO6 0x00000001 // Mono 4:2:0 (6 blocks)
#define X393_CMPRS_CBIT_CMODE_JP46 0x00000002 // jp4, 6 blocks, original
#define X393_CMPRS_CBIT_CMODE_JP46DC 0x00000003 // jp4, 6 blocks, DC-improved
#define X393_CMPRS_CBIT_CMODE_JPEG20 0x00000004 // Color 4:2:0 with 5x5 de-bayer (not implemented)
#define X393_CMPRS_CBIT_CMODE_JP4 0x00000005 // jp4, 4 blocks
#define X393_CMPRS_CBIT_CMODE_JP4DC 0x00000006 // jp4, 4 blocks, DC-improved
#define X393_CMPRS_CBIT_CMODE_JP4DIFF 0x00000007 // jp4, 4 blocks, differential
#define X393_CMPRS_CBIT_CMODE_JP4DIFFHDR 0x00000008 // jp4, 4 blocks, differential, hdr
#define X393_CMPRS_CBIT_CMODE_JP4DIFFDIV2 0x00000009 // jp4, 4 blocks, differential, divide by 2
#define X393_CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 0x0000000a // jp4, 4 blocks, differential, hdr,divide by 2
#define X393_CMPRS_CBIT_CMODE_MONO1 0x0000000b // Mono JPEG (not yet implemented)
#define X393_CMPRS_CBIT_CMODE_MONO4 0x0000000e // Mono, 4 blocks (2x2 macroblocks)
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0
#define X393_CMPRS_CBIT_CMODE_JPEG18 0x00000000 // Color 4:2:0
#define X393_CMPRS_CBIT_FRAMES_SINGLE 0x00000000 // Use single-frame buffer
#define X393_CMPRS_CBIT_FRAMES_MULTI 0x00000001 // Use multi-frame buffer
// Compressor control
#define X393_CMPRS_CONTROL_REG(cmprs_chn) (0x40001800 + 0x40 * (cmprs_chn)) // Program compressor channel operation mode, cmprs_chn = 0..3, data type: x393_cmprs_mode_t (wo)
#define X393_CMPRS_STATUS(cmprs_chn) (0x40001804 + 0x40 * (cmprs_chn)) // Setup compressor status report mode, cmprs_chn = 0..3, data type: x393_status_ctrl_t (rw)
#define X393_CMPRS_FORMAT(cmprs_chn) (0x40001808 + 0x40 * (cmprs_chn)) // Compressor frame format, cmprs_chn = 0..3, data type: x393_cmprs_frame_format_t (rw)
#define X393_CMPRS_COLOR_SATURATION(cmprs_chn) (0x4000180c + 0x40 * (cmprs_chn)) // Compressor color saturation, cmprs_chn = 0..3, data type: x393_cmprs_colorsat_t (rw)
#define X393_CMPRS_CORING_MODE(cmprs_chn) (0x40001810 + 0x40 * (cmprs_chn)) // Select coring mode, cmprs_chn = 0..3, data type: x393_cmprs_coring_mode_t (rw)
#define X393_CMPRS_INTERRUPTS(cmprs_chn) (0x40001814 + 0x40 * (cmprs_chn)) // Compressor interrupts control (1 - clear, 2 - disable, 3 - enable), cmprs_chn = 0..3, data type: x393_cmprs_interrupts_t (wo)
// Compressor tables load control
// Several tables can be loaded to the compressor, there are 4 types of them:
// 0:quantization tables - 8 pairs can be loaded and switched at run time,
// 1:coring tables - 8 pairs can be loaded and switched at run time,
// 2:focusing tables - 15 tables can be loaded and switched at run time (16-th table address space
// is used to program other focusing mode parameters,
// 3:Huffman tables - 1 pair tables can be loaded
// Default tables are loaded with the bitstream file (100% quality for quantization table 0
// Loading a table requires to load address of the beginning of data, it includes table type and optional offset
// when multiple tables of the same type are used. Next the data should be written to the same register address,
// the table address is auto-incremented,
// Data for the tables 0..2 should be combined: two items into a single 32-bit DWORD (little endian), treating
// each item as a 16-bit word. The Huffman table is one item per DWORD. Address offset is calculated in DWORDs
// Compressor table types
#define X393_TABLE_QUANTIZATION_TYPE 0x00000000 // Quantization table type
#define X393_TABLE_CORING_TYPE 0x00000001 // Coring table type
#define X393_TABLE_FOCUS_TYPE 0x00000002 // Focus table type
#define X393_TABLE_HUFFMAN_TYPE 0x00000003 // Huffman table type
// Compressor tables control
#define X393_CMPRS_TABLES_DATA(cmprs_chn) (0x40001818 + 0x40 * (cmprs_chn)) // Compressor tables data, cmprs_chn = 0..3, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS(cmprs_chn) (0x4000181c + 0x40 * (cmprs_chn)) // Compressor tables type/address, cmprs_chn = 0..3, data type: x393_cmprs_table_addr_t (wo)
// Compressor channel status)
#define X393_CMPRS_STATUS(chn) (0x40002040 + 0x4 * (chn)) // Status of the compressor channel (incl. interrupt, chn = 0..3, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_HIFREQ(chn) (0x40002050 + 0x4 * (chn)) // Focus helper high-frequency amount, chn = 0..3, data type: u32 (ro)
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
// serving all 4 compressor channels through its input ports. Below afi_port (0..3) references to one of the 4 ports of each. Control
// for two AXI HP channels is implemented as separate functions. Currently only the first channel is used
#define X393_AFIMUX0_EN 0x40001900 // AFI MUX 0 global/port run/pause control, data type: x393_afimux_en_t (wo)
#define X393_AFIMUX0_RST 0x40001904 // AFI MUX 0 per-port resets, data type: x393_afimux_rst_t (rw)
#define X393_AFIMUX0_REPORT_MODE 0x40001908 // AFI MUX 0 readout pointer report mode, data type: x393_afimux_report_t (wo)
#define X393_AFIMUX0_STATUS_CONTROL 0x40001910 // AFI MUX 0 status report mode, data type: x393_status_ctrl_t (rw)
#define X393_AFIMUX0_SA(afi_port) (0x40001920 + 0x4 * (afi_port)) // AFI MUX 0 DMA buffer start address in 32-byte blocks, afi_port = 0..3, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX0_LEN(afi_port) (0x40001930 + 0x4 * (afi_port)) // AFI MUX 0 DMA buffer length in 32-byte blocks, afi_port = 0..3, data type: x393_afimux_len_t (rw)
// Same for the second AXI HP channel (not currently used)
#define X393_AFIMUX1_EN 0x40001940 // AFI MUX 1 global/port run/pause control, data type: x393_afimux_en_t (wo)
#define X393_AFIMUX1_RST 0x40001944 // AFI MUX 1 per-port resets, data type: x393_afimux_rst_t (rw)
#define X393_AFIMUX1_REPORT_MODE 0x40001948 // AFI MUX 1 readout pointer report mode, data type: x393_afimux_report_t (wo)
#define X393_AFIMUX1_STATUS_CONTROL 0x40001950 // AFI MUX 1 status report mode, data type: x393_status_ctrl_t (rw)
#define X393_AFIMUX1_SA(afi_port) (0x40001960 + 0x4 * (afi_port)) // AFI MUX 1 DMA buffer start address in 32-byte blocks, afi_port = 0..3, data type: x393_afimux_sa_t (rw)
#define X393_AFIMUX1_LEN(afi_port) (0x40001970 + 0x4 * (afi_port)) // AFI MUX 1 DMA buffer length in 32-byte blocks, afi_port = 0..3, data type: x393_afimux_len_t (rw)
// Read-only sensors status information (pointer offset and last sequence number)
#define X393_AFIMUX0_STATUS(afi_port) (0x40002060 + 0x4 * (afi_port)) // Status of the AFI MUX 0 (including image pointer), afi_port = 0..3, data type: x393_afimux_status_t (ro)
#define X393_AFIMUX1_STATUS(afi_port) (0x40002070 + 0x4 * (afi_port)) // Status of the AFI MUX 1 (including image pointer), afi_port = 0..3, data type: x393_afimux_status_t (ro)
//
// GPIO contol. Each of the 10 pins can be controlled by the software - individually or simultaneously or from any of the 3 masters (other FPGA modules)
// Currently these modules are;
// A - camsync (intercamera synchronization), uses up to 4 pins
// B - reserved (not yet used) and
// C - logger (IMU, GPS, images), uses 6 pins, including separate i2c available on extension boards
// If several enabled ports try to contol the same bit, highest priority has port C, lowest - software controlled
#define X393_GPIO_SET_PINS 0x40001c00 // State of the GPIO pins and seq. number, data type: x393_gpio_set_pins_t (wo)
#define X393_GPIO_STATUS_CONTROL 0x40001c04 // GPIO status control mode, data type: x393_status_ctrl_t (rw)
// Read-only GPIO pins state
#define X393_GPIO_STATUS 0x400020c0 // State of the GPIO pins and seq. number, data type: x393_gpio_status_t (ro)
// RTC control
#define X393_RTC_USEC 0x40001c10 // RTC microseconds, data type: x393_rtc_usec_t (rw)
#define X393_RTC_SEC_SET 0x40001c14 // RTC seconds and set clock, data type: x393_rtc_sec_t (rw)
#define X393_RTC_CORR 0x40001c18 // RTC correction (+/- 1/256 full scale), data type: x393_rtc_corr_t (rw)
#define X393_RTC_SET_STATUS 0x40001c1c // RTC status control mode, write makes a snapshot to be read out, data type: x393_status_ctrl_t (rw)
// Read-only RTC state
#define X393_RTC_STATUS 0x400020c4 // RTC status reg, data type: x393_rtc_status_t (ro)
#define X393_RTC_STATUS_SEC 0x400020c8 // RTC snapshot seconds, data type: x393_rtc_sec_t (ro)
#define X393_RTC_STATUS_USEC 0x400020cc // RTC snapshot microseconds, data type: x393_rtc_usec_t (ro)
// CAMSYNC control
#define X393_CAMSYNC_MODE 0x40001c20 // CAMSYNC mode, data type: x393_camsync_mode_t (wo)
#define X393_CAMSYNC_TRIG_SRC 0x40001c24 // CAMSYNC trigger source, data type: x393_camsync_io_t (wo)
#define X393_CAMSYNC_TRIG_DST 0x40001c28 // CAMSYNC trigger destination, data type: x393_camsync_io_t (wo)
// Trigger period has special value for small (<255) values written to this register
// d == 0 - disable (stop periodic mode)
// d == 1 - single trigger
// d == 2..255 - set output pulse / input-output serial bit duration (no start generated)
// d >= 256 - repetitive trigger
#define X393_CAMSYNC_TRIG_PERIOD 0x40001c2c // CAMSYNC trigger period, data type: u32 (rw)
#define X393_CAMSYNC_TRIG_DELAY(sens_chn) (0x40001c30 + 0x4 * (sens_chn)) // CAMSYNC trigger delay, sens_chn = 0..3, data type: u32 (rw)
// Command sequencer control
// Controller is programmed through 32 locations. Each registers but the control require two writes:
// First write - register address (AXI_WR_ADDR_BITS bits), second - register data (32 bits)
// Writing to the contol register (0x1f) resets the first/second counter so the next write will be "first"
// 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame
// "just missed" - in that case data will go to the current frame.
// 0x10 - write seq commands to be sent ASAP
// 0x11 - write seq commands to be sent after the next frame starts
//
// 0x1e - write seq commands to be sent after the next 14 frame start pulses
// 0x1f - control register:
// [14] - reset all FIFO (takes 32 clock pulses), also - stops seq until run command
// [13:12] - 3 - run seq, 2 - stop seq , 1,0 - no change to run state
// [1:0] - 0: NOP, 1: clear IRQ, 2 - Clear IE, 3: set IE
#define X393_CMDFRAMESEQ_CTRL(sens_chn) (0x40001e7c + 0x80 * (sens_chn)) // CMDFRAMESEQ control register, sens_chn = 0..3, data type: x393_cmdframeseq_mode_t (wo)
#define X393_CMDFRAMESEQ_ABS(sens_chn,offset) (0x40001e00)+ 0x20 * (sens_chn)+ 0x1 * (offset)) // CMDFRAMESEQ absolute frame address/command, sens_chn = 0..3, offset = 0..15, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL(sens_chn,offset) (0x40001e40)+ 0x20 * (sens_chn)+ 0x1 * (offset)) // CMDFRAMESEQ relative frame address/command, sens_chn = 0..3, offset = 0..14, data type: u32 (wo)
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
#define X393_CMDSEQMUX_STATUS_CTRL 0x40001c08 // CMDSEQMUX status control mode (status provides current frame numbers), data type: x393_status_ctrl_t (rw)
#define X393_CMDSEQMUX_STATUS 0x400020e0 // CMDSEQMUX status data (frame numbers and interrupts, data type: x393_cmdseqmux_status_t (ro)
// Event logger
// Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.
// Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.
// Register pages:
#define X393_LOGGER_PAGE_CONF 0x00000000 // Logger configuration page
#define X393_LOGGER_PAGE_IMU 0x00000003 // Logger IMU parameters page
#define X393_LOGGER_PAGE_GPS 0x00000001 // Logger GPS parameters page
#define X393_LOGGER_PAGE_MSG 0x00000002 // Logger MSG (odometer) parameters page
// Register configuration addresses (with X393_LOGGER_PAGE_CONF):
#define X393_LOGGER_PERIOD 0x00000000 // IMU period (in SPI clocks, high word 0xffff - use IMU ready)
#define X393_LOGGER_BIT_DURATION 0x00000001 // IMU SPI bit duration (in mclk == 50 ns periods?)
#define X393_LOGGER_BIT_HALF_PERIOD 0x00000002 // Logger rs232 half bit period (in mclk == 50 ns periods?)
#define X393_LOGGER_CONFIG 0x00000003 // Logger IMU parameters page
#define X393_LOGGER_STATUS_CTRL 0x40001c88 // Logger status configuration (to report sample number), data type: x393_status_ctrl_t (rw)
#define X393_LOGGER_DATA 0x40001c80 // Logger register write data, data type: x393_logger_data_t (wo)
#define X393_LOGGER_ADDRESS 0x40001c84 // Logger register write page/address, data type: x393_logger_address_t (wo)
#define X393_LOGGER_STATUS 0x400020e4 // Logger status data (sequence number), data type: x393_logger_status_t (ro)
// MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger
#define X393_MULT_SAXI_STATUS_CTRL 0x40001ce0 // MULT_SAXI status control mode (status provides current DWORD pointer), data type: x393_status_ctrl_t (rw)
#define X393_MULT_SAXI_BUF_ADDRESS(chn) (0x40001cc0 + 0x8 * (chn)) // MULT_SAXI buffer start address in DWORDS, chn = 0..3, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_BUF_LEN(chn) (0x40001cc4 + 0x8 * (chn)) // MULT_SAXI buffer length in DWORDS, chn = 0..3, data type: x393_mult_saxi_al_t (wo)
#define X393_MULT_SAXI_STATUS(chn) (0x400020d0 + 0x4 * (chn)) // MULT_SAXI current DWORD pointer, chn = 0..3, data type: x393_mult_saxi_al_t (ro)
// MULTI_CLK - global clock generation PLLs. Interface provided for debugging, no interaction is needed for normal operation
#define X393_MULTICLK_STATUS_CTRL 0x40001ca4 // MULTI_CLK status generation (do not use or do not set auto), data type: x393_status_ctrl_t (rw)
#define X393_MULTICLK_CTRL 0x40001ca0 // MULTI_CLK reset and power down control, data type: x393_multiclk_ctl_t (rw)
#define X393_MULTICLK_STATUS 0x400020e8 // MULTI_CLK lock and toggle state, data type: x393_multiclk_status_t (ro)
// Debug ring module
// Debug ring module (when enabled with DEBUG_RING in system_defines.vh) provides low-overhead read/write access to internal test points
// To write data you need to write 32-bit data with x393_debug_shift(u32) multiple times to fill the ring register (length depends on
// implementation), skip this step if only reading from the modules under test is required.
// Exchange data with x393_debug_load(), the data from the ring shift register.
// Write 0xffffffff (or other "magic" data) if the ring length is unknown - this DWORD will appear on the output after the useful data
// Read all data, waiting for status sequence number to be incremented,status mode should be set to auto (3) wor each DWORD certain
// number of times or until the "magic" DWORD appears, writing "magic" to shift out next 32 bits.
#define X393_DEBUG_STATUS_CTRL 0x40001c48 // Debug ring status generation - set to auto(3) if used, data type: x393_status_ctrl_t (rw)
#define X393_DEBUG_LOAD 0x40001c44 // Debug ring copy shift register to/from tested modules
#define X393_DEBUG_SHIFT 0x40001c40 // Debug ring shift ring by 32 bits, data type: u32 (wo)
#define X393_DEBUG_STATUS 0x400023f0 // Debug read status (watch sequence number), data type: x393_debug_status_t (ro)
#define X393_DEBUG_READ 0x400023f4 // Debug read DWORD form ring register, data type: u32 (ro)
// Write-only addresses to program memory channel 3 (test channel)
#define X393_MCNTRL_CHN3_SCANLINE_MODE 0x400004c0 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_STATUS_CNTRL 0x400004c4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN3_SCANLINE_STARTADDR 0x400004c8 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_SIZE 0x400004cc // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_LAST 0x400004d0 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_FRAME_FULL_WIDTH 0x400004d4 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_WINDOW_WH 0x400004d8 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_WINDOW_X0Y0 0x400004dc // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN3_SCANLINE_STARTXY 0x400004e0 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
// Write-only addresses to program memory channel 2 (test channel)
#define X393_MCNTRL_CHN2_TILED_MODE 0x40000500 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN2_TILED_STATUS_CNTRL 0x40000504 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN2_TILED_STARTADDR 0x40000508 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_SIZE 0x4000050c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_LAST 0x40000510 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN2_TILED_FRAME_FULL_WIDTH 0x40000514 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN2_TILED_WINDOW_WH 0x40000518 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN2_TILED_WINDOW_X0Y0 0x4000051c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN2_TILED_STARTXY 0x40000520 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_MCNTRL_CHN2_TILED_TILE_WHS 0x40000524 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
// Write-only addresses to program memory channel 4 (test channel)
#define X393_MCNTRL_CHN4_TILED_MODE 0x40000540 // Set mode register (write last after other channel registers are set), data type: x393_mcntrl_mode_scan_t (wo)
#define X393_MCNTRL_CHN4_TILED_STATUS_CNTRL 0x40000544 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
#define X393_MCNTRL_CHN4_TILED_STARTADDR 0x40000548 // Set frame start address, data type: x393_mcntrl_window_frame_sa_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_SIZE 0x4000054c // Set frame size (address increment), data type: x393_mcntrl_window_frame_sa_inc_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_LAST 0x40000550 // Set last frame number (number of frames in buffer minus 1), data type: x393_mcntrl_window_last_frame_num_t (wo)
#define X393_MCNTRL_CHN4_TILED_FRAME_FULL_WIDTH 0x40000554 // Set frame full(padded) width, data type: x393_mcntrl_window_full_width_t (wo)
#define X393_MCNTRL_CHN4_TILED_WINDOW_WH 0x40000558 // Set frame window size, data type: x393_mcntrl_window_width_height_t (wo)
#define X393_MCNTRL_CHN4_TILED_WINDOW_X0Y0 0x4000055c // Set frame position, data type: x393_mcntrl_window_left_top_t (wo)
#define X393_MCNTRL_CHN4_TILED_STARTXY 0x40000560 // Set startXY register, data type: x393_mcntrl_window_startx_starty_t (wo)
#define X393_MCNTRL_CHN4_TILED_TILE_WHS 0x40000564 // Set tile size/step (tiled mode only), data type: x393_mcntrl_window_tile_whs_t (wo)
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/*******************************************************************************
* File: x393_types.h
* Date: 2016-03-29
* Author: auto-generated file, see x393_export_c.py
* Description: typedef definitions for the x393 hardware registers
*******************************************************************************/
// Status generation control
typedef union {
struct {
u32 seq_num: 6; // [ 5: 0] (0) 6-bit sequence number to be used with the next status response
u32 mode: 2; // [ 7: 6] (3) Status report mode: 0 - disable, 1 - single, 2 - auto, keep sequence number, 3 - auto, inc. seq. number
u32 :24;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_ctrl_t;
// Memory channel operation mode
typedef union {
struct {
u32 enable: 1; // [ 0] (1) enable requests from this channel ( 0 will let current to finish, but not raise want/need)
u32 chn_nreset: 1; // [ 1] (1) 0: immediately reset all the internal circuitry
u32 write_mem: 1; // [ 2] (0) 0 - read from memory, 1 - write to memory
u32 extra_pages: 2; // [ 4: 3] (0) 2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
u32 keep_open: 1; // [ 5] (0) for 8 or less rows - do not close page between accesses (not used in scanline mode)
u32 byte32: 1; // [ 6] (1) 32-byte columns (0 - 16-byte), not used in scanline mode
u32 : 1;
u32 reset_frame: 1; // [ 8] (0) reset frame number
u32 single: 1; // [ 9] (0) run single frame
u32 repetitive: 1; // [ 10] (1) run repetitive frames
u32 disable_need: 1; // [ 11] (0) disable 'need' generation, only 'want' (compressor channels)
u32 skip_too_late: 1; // [ 12] (0) Skip over missed blocks to preserve frame structure (increment pointers)
u32 :19;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_mode_scan_t;
// Memory channel window tile size/step (tiled only)
typedef union {
struct {
u32 tile_width: 6; // [ 5: 0] (2) tile width in 8-bursts (16 bytes)
u32 : 2;
u32 tile_height: 6; // [13: 8] (0x12) tile height in lines (0 means 64 lines)
u32 : 2;
u32 vert_step: 8; // [23:16] (0x10) Tile vertical step to control tile overlap
u32 : 8;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_tile_whs_t;
// Memory channel window size
typedef union {
struct {
u32 width:13; // [12: 0] (0) 13-bit window width - in 8*16=128 bit bursts
u32 : 3;
u32 height:16; // [31:16] (0) 16-bit window height in scan lines
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_width_height_t;
// Memory channel window position
typedef union {
struct {
u32 left:13; // [12: 0] (0) 13-bit window left margin in 8-bursts (16 bytes)
u32 : 3;
u32 top:16; // [31:16] (0) 16-bit window top margin in scan lines
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_left_top_t;
// Memory channel scan start (debug feature)
typedef union {
struct {
u32 start_x:13; // [12: 0] (0) 13-bit window start X relative to window left margin (debug feature, set = 0)
u32 : 3;
u32 start_y:16; // [31:16] (0) 16-bit window start Y relative to window top margin (debug feature, set = 0)
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_startx_starty_t;
// Memory channel window full (padded) width
typedef union {
struct {
u32 full_width:13; // [12: 0] (0) 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
u32 :19;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_full_width_t;
// Memory channel last frame number in a buffer (number of frames minus 1)
typedef union {
struct {
u32 last_frame_num:16; // [15: 0] (0) 16-bit number of the last frame in a buffer (1 for a 2-frame ping-pong one)
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_last_frame_num_t;
// Memory channel frame start address increment (for next frame in a buffer)
typedef union {
struct {
u32 frame_sa_inc:22; // [21: 0] (0) 22-bit frame start address increment (3 CA LSBs==0. BA==0)
u32 :10;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_frame_sa_inc_t;
// Memory channel frame start address for the first frame in a buffer
typedef union {
struct {
u32 frame_sa:22; // [21: 0] (0) 22-bit frame start address (3 CA LSBs==0. BA==0)
u32 :10;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntrl_window_frame_sa_t;
// PS PIO (software-programmed DDR3) access sequences enable and reset
typedef union {
struct {
u32 nrst: 1; // [ 0] (1) Active-low reset for programmed DDR3 memory sequences
u32 en: 1; // [ 1] (1) Enable PS_PIO channel. Only influences request for arbitration, started transactions will finish if disabled
u32 :30;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_ps_pio_en_rst_t;
// PS PIO (software-programmed DDR3) access sequences control
typedef union {
struct {
u32 seq_addr:10; // [ 9: 0] (0) Sequence start address
u32 page: 2; // [11:10] (0) Buffer page number
u32 urgent: 1; // [ 12] (0) high priority request (only for competition with other channels, will not pass in this FIFO)
u32 chn: 1; // [ 13] (0) channel buffer to use: 0 - memory read, 1 - memory write
u32 wait_complete: 1; // [ 14] (0) Do not request a new transaction from the scheduler until previous memory transaction is finished
u32 :17;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_ps_pio_cmd_t;
// x393 generic status register
typedef union {
struct {
u32 status24:24; // [23: 0] (0) 24-bit status payload ([25:2] in Verilog
u32 status2: 2; // [25:24] (0) 2-bit status payload (2 LSB in Verilog)
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_t;
// Memory PHY status
typedef union {
struct {
u32 ps_out: 8; // [ 7: 0] (0) Current MMCM phase shift
u32 run_busy: 1; // [ 8] (0) Controller sequence in progress
u32 locked_pll: 1; // [ 9] (0) PLL is locked
u32 locked_mmcm: 1; // [ 10] (0) MMCM is locked
u32 dci_ready: 1; // [ 11] (0) DCI calibration is ready
u32 dly_ready: 1; // [ 12] (0) I/O delays calibration is ready
u32 :11;
u32 ps_rdy: 1; // [ 24] (0) Phase change is done
u32 locked: 1; // [ 25] (0) Both PLL and MMCM are locked
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_mcntrl_phy_t;
// Memory controller requests status
typedef union {
struct {
u32 chn_want:16; // [15: 0] (0) Bit mask of the channels that request memory access
u32 : 8;
u32 want_some: 1; // [ 24] (0) At least one channel requests memory access (normal priority)
u32 need_some: 1; // [ 25] (0) At least one channel requests urgent memory access (high priority)
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_mcntrl_top_t;
// Memory software access status
typedef union {
struct {
u32 :24;
u32 cmd_half_full: 1; // [ 24] (0) MCNTRL software access pending commands FIFO is half full
u32 cmd_nempty_busy: 1; // [ 25] (0) MCNTRL software access pending commands FIFO is not empty or command is running
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_mcntrl_ps_t;
// Memory test channels access status
typedef union {
struct {
u32 :24;
u32 busy: 1; // [ 24] (0) Channel is busy (started and some memory accesses are pending)
u32 frame_finished: 1; // [ 25] (0) Channel completed all memory accesses
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_mcntrl_lintile_t;
// Memory test channels status
typedef union {
struct {
u32 line_unfinished:16; // [15: 0] (0) Current unfinished frame line
u32 page: 4; // [19:16] (0) Current page number read/written through a channel (low bits)
u32 : 4;
u32 frame_busy: 1; // [ 24] (0) Channel is busy (started and some memory accesses are pending)
u32 frame_finished: 1; // [ 25] (0) Channel completed all memory accesses
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_mcntrl_testchn_t;
// Membridge channel status
typedef union {
struct {
u32 wresp_conf: 8; // [ 7: 0] (0) Number of 64-bit words confirmed through axi b channel (low bits)
u32 axi_arw_requested: 8; // [15: 8] (0) Number of 64-bit words to be read/written over axi queued to AR/AW channels (low bits)
u32 : 8;
u32 busy: 1; // [ 24] (0) Membridge operation in progress
u32 done: 1; // [ 25] (0) Membridge operation finished
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_membridge_t;
// Sensor/multiplexer I/O pins status
typedef union {
struct {
u32 ps_out: 8; // [ 7: 0] (0) Sensor MMCM current phase
u32 ps_rdy: 1; // [ 8] (0) Sensor MMCM phase ready
u32 xfpgadone: 1; // [ 9] (0) Multiplexer FPGA DONE output
u32 clkfb_pxd_stopped_mmcm: 1; // [ 10] (0) Sensor MMCM feedback clock stopped
u32 clkin_pxd_stopped_mmcm: 1; // [ 11] (0) Sensor MMCM input clock stopped
u32 locked_pxd_mmcm: 1; // [ 12] (0) Sensor MMCM locked
u32 hact_alive: 1; // [ 13] (0) HACT signal from the sensor (or internal) is toggling (N/A for HiSPI
u32 hact_ext_alive: 1; // [ 14] (0) HACT signal from the sensor is toggling (N/A for HiSPI)
u32 vact_alive: 1; // [ 15] (0) VACT signal from the sensor is toggling (N/A for HiSPI)
u32 : 8;
u32 senspgmin: 1; // [ 24] (0) senspgm pin state
u32 xfpgatdo: 1; // [ 25] (0) Multiplexer FPGA TDO output
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_sens_io_t;
// Sensor/multiplexer i2c status
typedef union {
struct {
u32 i2c_fifo_dout: 8; // [ 7: 0] (0) I2c byte read from the device through FIFO
u32 i2c_fifo_nempty: 1; // [ 8] (0) I2C read FIFO has data
u32 i2c_fifo_cntrl: 1; // [ 9] (0) I2C FIFO byte counter (odd/even bytes)
u32 busy: 1; // [ 10] (0) I2C sequencer busy
u32 alive_fs: 1; // [ 11] (0) Sensor generated frame sync since last status update
u32 frame_num: 4; // [15:12] (0) I2C sequencer frame number
u32 req_clr: 1; // [ 16] (0) Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)
u32 reset_on: 1; // [ 17] (0) Reset in progress
u32 : 6;
u32 scl_in: 1; // [ 24] (0) SCL pin state
u32 sda_in: 1; // [ 25] (0) SDA pin state
u32 seq_num: 6; // [31:26] (0) Sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_status_sens_i2c_t;
// Command bits for test01 module (test frame memory accesses)
typedef union {
struct {
u32 frame_start: 1; // [ 0] (0) start frame command
u32 next_page: 1; // [ 1] (0) Next page command
u32 suspend: 1; // [ 2] (0) Suspend command
u32 :29;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_test01_mode_t;
// Command for membridge
typedef union {
struct {
u32 enable: 1; // [ 0] (0) enable membridge
u32 start_reset: 2; // [ 2: 1] (0) 1 - start (from current address), 3 - start from reset address
u32 :29;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_membridge_cmd_t;
// Cache mode for membridge
typedef union {
struct {
u32 axi_cache: 4; // [ 3: 0] (3) AXI CACHE value (ignored by Zynq)
u32 debug_cache: 1; // [ 4] (0) 0 - normal operation, 1 debug (replace data)
u32 :27;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_membridge_mode_t;
// Address in 64-bit words
typedef union {
struct {
u32 addr64:29; // [28: 0] (0) Address/length in 64-bit words (<<3 to get byte address
u32 : 3;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} u29_t;
// I2C contol/table data
typedef union {
struct {
u32 tbl_addr: 8; // [ 7: 0] (0) Address/length in 64-bit words (<<3 to get byte address
u32 :20;
u32 tbl_mode: 2; // [29:28] (3) Should be 3 to select table address write mode
u32 : 2;
};
struct {
u32 rah: 8; // [ 7: 0] (0) High byte of the i2c register address
u32 rnw: 1; // [ 8] (0) Read/not write i2c register, should be 0 here
u32 sa: 7; // [15: 9] (0) Slave address in write mode
u32 nbwr: 4; // [19:16] (0) Number of bytes to write (1..10)
u32 dly: 8; // [27:20] (0) Bit delay - number of mclk periods in 1/4 of the SCL period
u32 /*tbl_mode*/: 2; // [29:28] (2) Should be 2 to select table data write mode
u32 : 2;
};
struct {
u32 /*rah*/: 8; // [ 7: 0] (0) High byte of the i2c register address
u32 /*rnw*/: 1; // [ 8] (0) Read/not write i2c register, should be 1 here
u32 : 7;
u32 nbrd: 3; // [18:16] (0) Number of bytes to read (1..18, 0 means '8')
u32 nabrd: 1; // [ 19] (0) Number of address bytes for read (0 - one byte, 1 - two bytes)
u32 /*dly*/: 8; // [27:20] (0) Bit delay - number of mclk periods in 1/4 of the SCL period
u32 /*tbl_mode*/: 2; // [29:28] (2) Should be 2 to select table data write mode
u32 : 2;
};
struct {
u32 sda_drive_high: 1; // [ 0] (0) Actively drive SDA high during second half of SCL==1 (valid with drive_ctl)
u32 sda_release: 1; // [ 1] (0) Release SDA early if next bit ==1 (valid with drive_ctl)
u32 drive_ctl: 1; // [ 2] (0) 0 - nop, 1 - set sda_release and sda_drive_high
u32 next_fifo_rd: 1; // [ 3] (0) Advance I2C read FIFO pointer
u32 : 8;
u32 cmd_run: 2; // [13:12] (0) Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run
u32 reset: 1; // [ 14] (0) Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
u32 :13;
u32 /*tbl_mode*/: 2; // [29:28] (0) Should be 0 to select controls
u32 : 2;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_i2c_ctltbl_t;
// Write sensor channel mode register
typedef union {
struct {
u32 hist_en: 4; // [ 3: 0] (0xf) Enable subchannel histogram modules (may be less than 4)
u32 hist_nrst: 4; // [ 7: 4] (0xf) Reset off for histograms subchannels (may be less than 4)
u32 chn_en: 1; // [ 8] (1) Enable this sensor channel
u32 bit16: 1; // [ 9] (0) 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
u32 :22;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sens_mode_t;
// Write number of sensor frames to combine into one virtual (linescan mode)
typedef union {
struct {
u32 mult_frames:16; // [15: 0] (0) Number of frames to combine into one minus 1 (0 - single,1 - two frames...)
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sens_sync_mult_t;
// Write sensor number of lines to delay frame sync
typedef union {
struct {
u32 mult_frames:16; // [15: 0] (0) Number of lines to delay late frame sync
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sens_sync_late_t;
// Configure memory controller priorities
typedef union {
struct {
u32 priority:16; // [15: 0] (0) Channel priority (the larger the higher)
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_arbite_pri_t;
// Enable/disable memory controller channels
typedef union {
struct {
u32 chn_en:16; // [15: 0] (0) Enabled memory channels
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntr_chn_en_t;
// DQS and DQM patterns (DQM - 0, DQS 0xaa or 0x55)
typedef union {
struct {
u32 dqs_patt: 8; // [ 7: 0] (0xaa) DQS pattern: 0xaa/0x55
u32 dqm_patt: 8; // [15: 8] (0) DQM pattern: 0x0
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntr_dqs_dqm_patt_t;
// DQ and DQS tristate control when turning on and off
typedef union {
struct {
u32 dq_tri_first: 4; // [ 3: 0] (3) DQ tristate start (0x3,0x7,0xf); early, nominal, late
u32 dq_tri_last: 4; // [ 7: 4] (0xe) DQ tristate end (0xf,0xe,0xc); early, nominal, late
u32 dqs_tri_first: 4; // [11: 8] (1) DQS tristate start (0x1,0x3,0x7); early, nominal, late
u32 dqs_tri_last: 4; // [15:12] (0xc) DQS tristate end (0xe,0xc,0x8); early, nominal, late
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mcntr_dqs_dqm_tri_t;
// DDR3 memory controller I/O delay
typedef union {
struct {
u32 dly: 8; // [ 7: 0] (0) 8-bit delay value: 5MSBs(0..31) and 3LSBs(0..4)
u32 :24;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_dly_t;
// Extra delay in mclk (fDDR/2) cycles) to data write buffer
typedef union {
struct {
u32 wbuf_dly: 4; // [ 3: 0] (9) Extra delay in mclk (fDDR/2) cycles) to data write buffer
u32 :28;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_wbuf_dly_t;
// Control for the gamma-conversion module
typedef union {
struct {
u32 bayer: 2; // [ 1: 0] (0) Bayer color shift (pixel to gamma table)
u32 page: 1; // [ 2] (0) Table page (only available if SENS_GAMMA_BUFFER in Verilog)
u32 en: 1; // [ 3] (1) Enable module
u32 repet: 1; // [ 4] (1) Repetitive (normal) mode. Set 0 for testing of the single-frame mode
u32 trig: 1; // [ 5] (0) Single trigger used when repetitive mode is off (self clearing bit)
u32 :26;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gamma_ctl_t;
// Write gamma table address/data
typedef union {
struct {
u32 addr: 8; // [ 7: 0] (0) Start address in a gamma page (normally 0)
u32 color: 2; // [ 9: 8] (0) Color channel
u32 sub_chn: 2; // [11:10] (0) Sensor sub-channel (multiplexed to the same port)
u32 : 8;
u32 a_n_d: 1; // [ 20] (1) Address/not data, should be set to 1 here
u32 :11;
};
struct {
u32 base:10; // [ 9: 0] (0) Knee point value (to be interpolated between)
char diff: 7; // [16:10] (0) Difference to next (signed, -64..+63)
u32 diff_scale: 1; // [ 17] (0) Difference scale: 0 - keep diff, 1- multiply diff by 16
u32 :14;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gamma_tbl_t;
// Heights of the first two subchannels frames
typedef union {
struct {
u32 height0m1:16; // [15: 0] (0) Height of subchannel 0 frame minus 1
u32 height1m1:16; // [31:16] (0) Height of subchannel 1 frame minus 1
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gamma_height01m1_t;
// Height of the third subchannel frame
typedef union {
struct {
u32 height2m1:16; // [15: 0] (0) Height of subchannel 2 frame minus 1
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gamma_height2m1_t;
// Sensor port I/O control
typedef union {
struct {
u32 mrst: 1; // [ 0] (0) MRST signal level to the sensor (0 - low(active), 1 - high (inactive)
u32 mrst_set: 1; // [ 1] (0) when set to 1, MRST is set to the 'mrst' field value
u32 arst: 1; // [ 2] (0) ARST signal to the sensor
u32 arst_set: 1; // [ 3] (0) ARST set to the 'arst' field
u32 aro: 1; // [ 4] (0) ARO signal to the sensor
u32 aro_set: 1; // [ 5] (0) ARO set to the 'aro' field
u32 mmcm_rst: 1; // [ 6] (0) MMCM (for sensor clock) reset signal
u32 mmcm_rst_set: 1; // [ 7] (0) MMCM reset set to 'mmcm_rst' field
u32 ext_clk: 1; // [ 8] (0) MMCM clock input: 0: clock to the sensor, 1 - clock from the sensor
u32 ext_clk_set: 1; // [ 9] (0) Set MMCM clock input to 'ext_clk' field
u32 set_dly: 1; // [ 10] (0) Set all pre-programmed delays to the sensor port input delays
u32 : 1;
u32 quadrants: 6; // [17:12] (1) 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
u32 : 2;
u32 quadrants_set: 1; // [ 20] (0) Set 'quadrants' values
u32 :11;
};
struct {
u32 /*mrst*/: 1; // [ 0] (0) MRST signal level to the sensor (0 - low(active), 1 - high (inactive)
u32 /*mrst_set*/: 1; // [ 1] (0) when set to 1, MRST is set to the 'mrst' field value
u32 /*arst*/: 1; // [ 2] (0) ARST signal to the sensor
u32 /*arst_set*/: 1; // [ 3] (0) ARST set to the 'arst' field
u32 /*aro*/: 1; // [ 4] (0) ARO signal to the sensor
u32 /*aro_set*/: 1; // [ 5] (0) ARO set to the 'aro' field
u32 /*mmcm_rst*/: 1; // [ 6] (0) MMCM (for sensor clock) reset signal
u32 /*mmcm_rst_set*/: 1; // [ 7] (0) MMCM reset set to 'mmcm_rst' field
u32 ign_embed: 1; // [ 8] (0) Ignore embedded data (non-image pixel lines
u32 ign_embed_set: 1; // [ 9] (0) Set mode to 'ign_embed' field
u32 /*set_dly*/: 1; // [ 10] (0) Set all pre-programmed delays to the sensor port input delays
u32 : 1;
u32 gp0: 1; // [ 12] (0) GP0 multipurpose signal to the sensor
u32 gp0_set: 1; // [ 13] (0) Set GP0 to 'gp0' value
u32 gp1: 1; // [ 14] (0) GP1 multipurpose signal to the sensor
u32 gp1_set: 1; // [ 15] (0) Set GP1 to 'gp1' value
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_ctl_t;
// Programming interface for multiplexer FPGA
typedef union {
struct {
u32 tdi: 1; // [ 0] (0) JTAG TDI level
u32 tdi_set: 1; // [ 1] (0) JTAG TDI set to 'tdi' field
u32 tms: 1; // [ 2] (0) JTAG TMS level
u32 tms_set: 1; // [ 3] (0) JTAG TMS set to 'tms' field
u32 tck: 1; // [ 4] (0) JTAG TCK level
u32 tck_set: 1; // [ 5] (0) JTAG TCK set to 'tck' field
u32 prog: 1; // [ 6] (0) Sensor port PROG level
u32 prog_set: 1; // [ 7] (0) Sensor port PROG set to 'prog' field
u32 pgmen: 1; // [ 8] (0) Sensor port PGMEN level
u32 pgmen_set: 1; // [ 9] (0) Sensor port PGMEN set to 'pgmen' field
u32 :22;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_jpag_t;
// Sensor i/o timing register 0 (different meanings for different sensor types)
typedef union {
struct {
u32 pxd0: 8; // [ 7: 0] (0) PXD0 input delay (3 LSB not used)
u32 pxd1: 8; // [15: 8] (0) PXD1 input delay (3 LSB not used)
u32 pxd2: 8; // [23:16] (0) PXD2 input delay (3 LSB not used)
u32 pxd3: 8; // [31:24] (0) PXD3 input delay (3 LSB not used)
};
struct {
u32 fifo_lag: 4; // [ 3: 0] (7) FIFO delay to start output
u32 :28;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_tim0_t;
// Sensor i/o timing register 1 (different meanings for different sensor types)
typedef union {
struct {
u32 pxd4: 8; // [ 7: 0] (0) PXD4 input delay (3 LSB not used)
u32 pxd5: 8; // [15: 8] (0) PXD5 input delay (3 LSB not used)
u32 pxd6: 8; // [23:16] (0) PXD6 input delay (3 LSB not used)
u32 pxd7: 8; // [31:24] (0) PXD7 input delay (3 LSB not used)
};
struct {
u32 phys_lane0: 2; // [ 1: 0] (1) Physical lane for logical lane 0
u32 phys_lane1: 2; // [ 3: 2] (2) Physical lane for logical lane 1
u32 phys_lane2: 2; // [ 5: 4] (3) Physical lane for logical lane 2
u32 phys_lane3: 2; // [ 7: 6] (0) Physical lane for logical lane 3
u32 :24;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_tim1_t;
// Sensor i/o timing register 2 (different meanings for different sensor types)
typedef union {
struct {
u32 pxd8: 8; // [ 7: 0] (0) PXD8 input delay (3 LSB not used)
u32 pxd9: 8; // [15: 8] (0) PXD9 input delay (3 LSB not used)
u32 pxd10: 8; // [23:16] (0) PXD10 input delay (3 LSB not used)
u32 pxd11: 8; // [31:24] (0) PXD11 input delay (3 LSB not used)
};
struct {
u32 dly_lane0: 8; // [ 7: 0] (0) lane 0 (phys) input delay (3 LSB not used)
u32 dly_lane1: 8; // [15: 8] (0) lane 1 (phys) input delay (3 LSB not used)
u32 dly_lane2: 8; // [23:16] (0) lane 2 (phys) input delay (3 LSB not used)
u32 dly_lane3: 8; // [31:24] (0) lane 3 (phys) input delay (3 LSB not used)
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_tim2_t;
// Sensor i/o timing register 3 (different meanings for different sensor types)
typedef union {
struct {
u32 hact: 8; // [ 7: 0] (0) HACT input delay (3 LSB not used)
u32 vact: 8; // [15: 8] (0) VACT input delay (3 LSB not used)
u32 bpf: 8; // [23:16] (0) BPF (clock from sensor) input delay (3 LSB not used)
u32 phase_p: 8; // [31:24] (0) MMCM phase
};
struct {
u32 phase_h: 8; // [ 7: 0] (0) MMCM phase
u32 :24;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_tim3_t;
// Set sensor frame width (0 - use received)
typedef union {
struct {
u32 sensor_width:16; // [15: 0] (0) Sensor frame width (0 - use line sync signals from the sensor)
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_sensio_width_t;
// Lens vignetting parameter (write address first, then data that may overlap som address bits)
typedef union {
struct {
u32 :16;
u32 addr: 8; // [23:16] (0) Lens correction address, should be written first (overlaps with data)
u32 sub_chn: 2; // [25:24] (0) Sensor subchannel
u32 : 6;
};
struct {
u32 ax:19; // [18: 0] (0x20000) Coefficient Ax
u32 :13;
};
struct {
u32 ay:19; // [18: 0] (0x20000) Coefficient Ay
u32 :13;
};
struct {
u32 bx:21; // [20: 0] (0x180000) Coefficient Bx
u32 :11;
};
struct {
u32 by:21; // [20: 0] (0x180000) Coefficient By
u32 :11;
};
struct {
u32 c:19; // [18: 0] (0x8000) Coefficient C
u32 :13;
};
struct {
u32 scale:17; // [16: 0] (0x8000) Scale (4 per-color values)
u32 :15;
};
struct {
u32 fatzero_in:16; // [15: 0] (0) 'Fat zero' on the input (subtract from the input)
u32 :16;
};
struct {
u32 fatzero_out:16; // [15: 0] (0) 'Fat zero' on the output (add to the result)
u32 :16;
};
struct {
u32 post_scale: 4; // [ 3: 0] (1) Shift result (bits)
u32 :28;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_lens_corr_t;
// Height of the subchannel frame for vignetting correction
typedef union {
struct {
u32 height_m1:16; // [15: 0] (0) Height of subframe minus 1
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_lens_height_m1_t;
// Histogram window left/top margins
typedef union {
struct {
u32 left:16; // [15: 0] (0) Histogram window left margin
u32 top:16; // [31:16] (0) Histogram window top margin
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_hist_left_top_t;
// Histogram window width and height minus 1 (0 use full)
typedef union {
struct {
u32 width_m1:16; // [15: 0] (0) Width of the histogram window minus 1. If 0 - use frame right margin (end of HACT)
u32 height_m1:16; // [31:16] (0) Height of he histogram window minus 1. If 0 - use frame bottom margin (end of VACT)
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_hist_width_height_m1_t;
// Histograms DMA mode
typedef union {
struct {
u32 en: 1; // [ 0] (1) Enable histograms DMA
u32 nrst: 1; // [ 1] (1) 0 - reset histograms DMA
u32 confirm: 1; // [ 2] (1) 1 - wait for confirmation that histogram was written to the system memory
u32 : 1;
u32 cache: 4; // [ 7: 4] (3) AXI cache mode (normal - 3), ignored by Zynq?
u32 :24;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_hist_saxi_mode_t;
// Histograms DMA addresses
typedef union {
struct {
u32 page:20; // [19: 0] (0) Start address of the subchannel histogram (in pages = 4096 bytes
u32 :12;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_hist_saxi_addr_t;
// Compressor mode control
typedef union {
struct {
u32 run: 2; // [ 1: 0] (0) Run mode
u32 run_set: 1; // [ 2] (0) Set 'run'
u32 qbank: 3; // [ 5: 3] (0) Quantization table bank
u32 qbank_set: 1; // [ 6] (0) Set 'qbank'
u32 dcsub: 1; // [ 7] (0) Subtract DC enable
u32 dcsub_set: 1; // [ 8] (0) Set 'qbank'
u32 cmode: 4; // [12: 9] (0) Color format
u32 cmode_set: 1; // [ 13] (0) Set 'cmode'
u32 multiframe: 1; // [ 14] (0) Multi/single frame mode
u32 multiframe_set: 1; // [ 15] (0) Set 'multiframe'
u32 : 2;
u32 bayer: 2; // [19:18] (0) Bayer shift
u32 bayer_set: 1; // [ 20] (0) Set 'bayer'
u32 focus: 2; // [22:21] (0) Focus mode
u32 focus_set: 1; // [ 23] (0) Set 'focus'
u32 : 8;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_mode_t;
// Compressor coring mode (table number)
typedef union {
struct {
u32 coring_table: 3; // [ 2: 0] (0) Select coring table pair number
u32 :29;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_coring_mode_t;
// Compressor color saturation
typedef union {
struct {
u32 colorsat_blue:10; // [ 9: 0] (0x120) Color saturation for blue (0x90 - 100%)
u32 : 2;
u32 colorsat_red:10; // [21:12] (0x16c) Color saturation for red (0xb6 - 100%)
u32 :10;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_colorsat_t;
// Compressor frame format
typedef union {
struct {
u32 num_macro_cols_m1:13; // [12: 0] (0) Number of macroblock colums minus 1
u32 num_macro_rows_m1:13; // [25:13] (0) Number of macroblock rows minus 1
u32 left_margin: 5; // [30:26] (0) Left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
u32 : 1;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_frame_format_t;
// Compressor interrupts control
typedef union {
struct {
u32 interrupt_cmd: 2; // [ 1: 0] (0) 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt
u32 :30;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_interrupts_t;
// Compressor tables load control
typedef union {
struct {
u32 addr32:24; // [23: 0] (0) Table address to start writing to (autoincremented) for DWORDs
u32 type: 2; // [25:24] (0) 0: quantization, 1: coring, 2: focus, 3: huffman
u32 : 6;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_table_addr_t;
// Compressor channel status
typedef union {
struct {
u32 is: 1; // [ 0] (0) Compressor channel interrupt status
u32 im: 1; // [ 1] (0) Compressor channel interrupt mask
u32 reading_frame: 1; // [ 2] (0) Compressor channel is reading frame from memory (debug feature)
u32 stuffer_running: 1; // [ 3] (0) Compressor channel bit stuffer is running (debug feature)
u32 flushing_fifo: 1; // [ 4] (0) Compressor channel is flushing FIFO (debug feature)
u32 :21;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_status_t;
// Compressor DMA buffer address (in 32-byte blocks)
typedef union {
struct {
u32 sa256:27; // [26: 0] (0) System memory buffer start in multiples of 32 bytes (256 bits)
u32 : 5;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_sa_t;
// Compressor DMA buffer length (in 32-byte blocks)
typedef union {
struct {
u32 len256:27; // [26: 0] (0) System memory buffer length in multiples of 32 bytes (256 bits)
u32 : 5;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_len_t;
// Compressor DMA channels reset
typedef union {
struct {
u32 rst0: 1; // [ 0] (0) AXI HPx sub-channel0 reset (0 - normal operation, 1 - reset)
u32 rst1: 1; // [ 1] (0) AXI HPx sub-channel0 reset (0 - normal operation, 1 - reset)
u32 rst2: 1; // [ 2] (0) AXI HPx sub-channel0 reset (0 - normal operation, 1 - reset)
u32 rst3: 1; // [ 3] (0) AXI HPx sub-channel0 reset (0 - normal operation, 1 - reset)
u32 :28;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_rst_t;
// Compressor DMA enable (global and channels)
typedef union {
struct {
u32 en0: 1; // [ 0] (0) AXI HPx sub-channel0 enable value to set (0 - pause, 1 - run)
u32 en0_set: 1; // [ 1] (0) 0 - nop, 1 - set en0
u32 en1: 1; // [ 2] (0) AXI HPx sub-channel1 enable value to set (0 - pause, 1 - run)
u32 en1_set: 1; // [ 3] (0) 0 - nop, 1 - set en1
u32 en2: 1; // [ 4] (0) AXI HPx sub-channel2 enable value to set (0 - pause, 1 - run)
u32 en2_set: 1; // [ 5] (0) 0 - nop, 1 - set en2
u32 en3: 1; // [ 6] (0) AXI HPx sub-channel3 enable value to set (0 - pause, 1 - run)
u32 en3_set: 1; // [ 7] (0) 0 - nop, 1 - set en3
u32 en: 1; // [ 8] (0) AXI HPx global enable value to set (0 - pause, 1 - run)
u32 en_set: 1; // [ 9] (0) 0 - nop, 1 - set en
u32 :22;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_en_t;
// Compressor DMA report mode
typedef union {
struct {
u32 mode0: 2; // [ 1: 0] (0) channel0 report mode: 0 - EOF int, 1 - EOF confirmed, 2 - CP (current), 3 - CP confirmed
u32 mode0_set: 1; // [ 2] (0) 0 - nop, 1 - set mode0
u32 : 1;
u32 mode1: 2; // [ 5: 4] (0) channel0 report mode: 0 - EOF int, 1 - EOF confirmed, 2 - CP (current), 3 - CP confirmed
u32 mode1_set: 1; // [ 6] (0) 0 - nop, 1 - set mode0
u32 : 1;
u32 mode2: 2; // [ 9: 8] (0) channel0 report mode: 0 - EOF int, 1 - EOF confirmed, 2 - CP (current), 3 - CP confirmed
u32 mode2_set: 1; // [ 10] (0) 0 - nop, 1 - set mode0
u32 : 1;
u32 mode3: 2; // [13:12] (0) channel0 report mode: 0 - EOF int, 1 - EOF confirmed, 2 - CP (current), 3 - CP confirmed
u32 mode3_set: 1; // [ 14] (0) 0 - nop, 1 - set mode0
u32 :17;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_report_t;
// Compressor DMA status
typedef union {
struct {
u32 offset256:26; // [25: 0] (0) AFI MUX current/EOF pointer offset in 32-byte blocks
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_afimux_status_t;
// GPIO output control
typedef union {
struct {
u32 pin0: 2; // [ 1: 0] (0) Output control for pin 0: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin1: 2; // [ 3: 2] (0) Output control for pin 1: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin2: 2; // [ 5: 4] (0) Output control for pin 2: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin3: 2; // [ 7: 6] (0) Output control for pin 3: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin4: 2; // [ 9: 8] (0) Output control for pin 4: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin5: 2; // [11:10] (0) Output control for pin 5: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin6: 2; // [13:12] (0) Output control for pin 6: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin7: 2; // [15:14] (0) Output control for pin 7: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin8: 2; // [17:16] (0) Output control for pin 8: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 pin9: 2; // [19:18] (0) Output control for pin 0: 0 - nop, 1 - set low, 2 - set high, 3 - tristate
u32 : 4;
u32 soft: 2; // [25:24] (0) Enable pin software control: 0,1 - nop, 2 - disab;e, 3 - enable
u32 chn_a: 2; // [27:26] (0) Enable A channel (camsync): 0,1 - nop, 2 - disab;e, 3 - enable
u32 chn_b: 2; // [29:28] (0) Enable B channel (reserved): 0,1 - nop, 2 - disab;e, 3 - enable
u32 chn_c: 2; // [31:30] (0) Enable C channel (logger): 0,1 - nop, 2 - disab;e, 3 - enable
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gpio_set_pins_t;
// GPIO pins status
typedef union {
struct {
u32 pin0: 1; // [ 0] (0) GPIO pin 0 state
u32 pin1: 1; // [ 1] (0) GPIO pin 0 state
u32 pin2: 1; // [ 2] (0) GPIO pin 0 state
u32 pin3: 1; // [ 3] (0) GPIO pin 0 state
u32 pin4: 1; // [ 4] (0) GPIO pin 0 state
u32 pin5: 1; // [ 5] (0) GPIO pin 0 state
u32 pin6: 1; // [ 6] (0) GPIO pin 0 state
u32 pin7: 1; // [ 7] (0) GPIO pin 0 state
u32 pin8: 1; // [ 8] (0) GPIO pin 0 state
u32 pin9: 1; // [ 9] (0) GPIO pin 0 state
u32 :16;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_gpio_status_t;
// RTC seconds
typedef union {
struct {
u32 sec:32; // [31: 0] (0) RTC seconds
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_rtc_sec_t;
// RTC microseconds
typedef union {
struct {
u32 usec:20; // [19: 0] (0) RTC microseconds
u32 :12;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_rtc_usec_t;
// RTC correction
typedef union {
struct {
short corr:16; // [15: 0] (0) RTC correction, +/1 1/256 full scale
u32 :16;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_rtc_corr_t;
// RTC status
typedef union {
struct {
u32 :24;
u32 alt_snap: 1; // [ 24] (0) alternates 0/1 each time RTC timer makes a snapshot
u32 : 1;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_rtc_status_t;
// CAMSYNC I/O configuration
typedef union {
struct {
u32 line0: 2; // [ 1: 0] (1) line 0 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line1: 2; // [ 3: 2] (1) line 1 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line2: 2; // [ 5: 4] (1) line 2 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line3: 2; // [ 7: 6] (1) line 3 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line4: 2; // [ 9: 8] (1) line 4 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line5: 2; // [11:10] (1) line 5 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line6: 2; // [13:12] (1) line 6 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line7: 2; // [15:14] (1) line 7 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line8: 2; // [17:16] (1) line 8 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 line9: 2; // [19:18] (1) line 9 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high
u32 :12;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_camsync_io_t;
// CAMSYNC mode
typedef union {
struct {
u32 en: 1; // [ 0] (1) Enable CAMSYNC module
u32 en_snd: 1; // [ 1] (1) Enable sending timestamps (valid with 'en_snd_set')
u32 en_snd_set: 1; // [ 2] (0) Set 'en_snd'
u32 ext: 1; // [ 3] (1) Use external (received) timestamps, if available. O - use local timestamps
u32 ext_set: 1; // [ 4] (0) Set 'ext'
u32 trig: 1; // [ 5] (1) Sensor triggered mode (0 - free running sensor)
u32 trig_set: 1; // [ 6] (0) Set 'trig'
u32 master_chn: 2; // [ 8: 7] (0) master sensor channel (zero delay in internal trigger mode, delay used for flash output)
u32 master_chn_set: 1; // [ 9] (0) Set 'master_chn'
u32 ts_chns: 4; // [13:10] (1) Channels to generate timestmp messages (bit mask)
u32 ts_chns_set: 1; // [ 14] (0) Set 'ts_chns'
u32 :17;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_camsync_mode_t;
// CMDFRAMESEQ mode
typedef union {
struct {
u32 interrupt_cmd: 2; // [ 1: 0] (0) Interrupt command: 0-nop, 1 - clear is, 2 - disable, 3 - enable
u32 :10;
u32 run_cmd: 2; // [13:12] (0) Run command: 0,1 - nop, 2 - stop, 3 - run
u32 reset: 1; // [ 14] (0) 1 - reset, 0 - normal operation
u32 :17;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmdframeseq_mode_t;
// CMDFRAMESEQ mode
typedef union {
struct {
u32 frame_num0: 4; // [ 3: 0] (0) Frame number for sensor 0
u32 frame_num1: 4; // [ 7: 4] (0) Frame number for sensor 0
u32 frame_num2: 4; // [11: 8] (0) Frame number for sensor 0
u32 frame_num3: 4; // [15:12] (0) Frame number for sensor 0
u32 is: 4; // [19:16] (0) Interrupt status: 1 bit per sensor channel
u32 im: 4; // [23:20] (0) Interrupt enable: 1 bit per sensor channel
u32 : 2;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmdseqmux_status_t;
// Event logger status
typedef union {
struct {
u32 sample:24; // [23: 0] (0) Logger sample number
u32 : 2;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_logger_status_t;
// Event logger register address
typedef union {
struct {
u32 addr: 5; // [ 4: 0] (0) Register address (autoincrements in 32 DWORDs (page) range
u32 page: 2; // [ 6: 5] (0) Register page: configuration: 0, IMU: 3, GPS: 1, MSG: 2
u32 :25;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_logger_address_t;
// Event logger register data
typedef union {
struct {
u32 imu_slot: 2; // [ 1: 0] (0) IMU slot
u32 imu_set: 1; // [ 2] (0) Set 'imu_slot'
u32 gps_slot: 2; // [ 4: 3] (0) GPS slot
u32 gps_invert: 1; // [ 5] (0) GPS inpert 1pps signal
u32 gps_ext: 1; // [ 6] (0) GPS sync to 1 pps signal (0 - sync to serial message)
u32 gps_set: 1; // [ 7] (0) Set 'gps_*' fields
u32 msg_input: 4; // [11: 8] (0) MSG pin: GPIO pin number to accept external signal (0xf - disable)
u32 msg_invert: 1; // [ 12] (0) MSG input polarity - 0 - active high, 1 - active low
u32 msg_set: 1; // [ 13] (0) Set 'msg_*' fields
u32 log_sync: 4; // [17:14] (0) Log frame sync events (bit per sensor channel)
u32 log_sync_set: 1; // [ 18] (0) Set 'log_sync' fields
u32 :13;
};
struct {
u32 data:32; // [31: 0] (0) Other logger register data (context-dependent)
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_logger_data_t;
// MULT_SAXI DMA addresses/lengths in 32-bit DWORDS
typedef union {
struct {
u32 addr32:30; // [29: 0] (0) SAXI sddress/length in DWORDs
u32 : 2;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_mult_saxi_al_t;
// MULTICLK reset/power down controls
typedef union {
struct {
u32 rst_clk0: 1; // [ 0] (0) Reset PLL for xclk(240MHz), hclk(150MHz)
u32 rst_clk1: 1; // [ 1] (0) Reset PLL for pclk (sensors, from ffclk0)
u32 rst_clk2: 1; // [ 2] (0) reserved
u32 rst_clk3: 1; // [ 3] (0) reserved
u32 pwrdwnclk0: 1; // [ 4] (0) Power down PLL for xclk(240MHz), hclk(150MHz)
u32 pwrdwn_clk1: 1; // [ 5] (0) Power down for pclk (sensors, from ffclk0)
u32 pwrdwn_clk2: 1; // [ 6] (0) reserved
u32 pwrdwn_clk3: 1; // [ 7] (0) reserved
u32 rst_memclk: 1; // [ 8] (0) reset memclk (external in for memory) toggle FF
u32 rst_ffclk0: 1; // [ 9] (0) reset ffclk0 (external in for sensors) toggle FF
u32 rst_ffclk1: 1; // [ 10] (0) reset ffclk1 (exteranl in, not yet used) toggle FF
u32 :21;
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_multiclk_ctl_t;
// MULTICLK status
typedef union {
struct {
u32 locked0: 1; // [ 0] (0) Locked PLL for xclk(240MHz), hclk(150MHz)
u32 locked1: 1; // [ 1] (0) Locked PLL for pclk (sensors, from ffclk0)
u32 locked2: 1; // [ 2] (0) ==1, reserved
u32 locked3: 1; // [ 3] (0) ==1, reserved
u32 tgl_memclk: 1; // [ 4] (0) memclk (external in for memory) toggle FF
u32 tgl_ffclk0: 1; // [ 5] (0) ffclk0 (external in for sensors) toggle FF
u32 tgl_ffclk1: 1; // [ 6] (0) ffclk1 (exteranl in, not yet used) toggle FF
u32 :17;
u32 idelay_rdy: 1; // [ 24] (0) idelay_ctrl_rdy (juct to prevent from optimization)
u32 : 1;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_multiclk_status_t;
// DEBUG status
typedef union {
struct {
u32 :24;
u32 tgl: 1; // [ 24] (0) Toggles for each DWORD received
u32 : 1;
u32 seq_num: 6; // [31:26] (0) Status sequence number
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_debug_status_t;
py393/init_jtag.sh 0 → 100755
View file @ d3767c2c
#!/bin/sh
#mkdir -p /lib/modules
#ln -sf /usr/local/lib /lib/modules/4.0.0-xilinx
#insmod /usr/local/lib/fpgajtag.ko
#mknod -m 0666 /dev/fjtag c 132 2
mknod -m 0666 /dev/fpgaresetjtag c 132 0
mknod -m 0666 /dev/jtagraw c 132 0
mknod -m 0666 /dev/fpgaconfjtag c 132 1
mknod -m 0666 /dev/sfpgaconfjtag c 132 2
mknod -m 0666 /dev/afpgaconfjtag c 132 3
#mknod -m 0666 /dev/fpgabscan c 132 5
#mknod -m 0666 /dev/sfpgabscan c 132 6
#mknod -m 0666 /dev/afpgabscan c 132 7
mknod -m 0666 /dev/sfpgaconfjtag0 c 132 8
mknod -m 0666 /dev/sfpgaconfjtag1 c 132 9
mknod -m 0666 /dev/sfpgaconfjtag2 c 132 10
mknod -m 0666 /dev/sfpgaconfjtag3 c 132 11
mknod -m 0666 /dev/sfpgabscan0 c 132 12
mknod -m 0666 /dev/sfpgabscan1 c 132 13
mknod -m 0666 /dev/sfpgabscan2 c 132 14
mknod -m 0666 /dev/sfpgabscan3 c 132 15
# @$(MKNOD) -m 0666 $(DEV)/fpgaresetjtag c 132 0
# @$(MKNOD) -m 0666 $(DEV)/jtagraw c 132 0
# @$(MKNOD) -m 0666 $(DEV)/fpgaconfjtag c 132 1
# @$(MKNOD) -m 0666 $(DEV)/sfpgaconfjtag c 132 2
# @$(MKNOD) -m 0666 $(DEV)/afpgaconfjtag c 132 3
# @$(MKNOD) -m 0666 $(DEV)/fpgabscan c 132 5
# @$(MKNOD) -m 0666 $(DEV)/sfpgabscan c 132 6
# @$(MKNOD) -m 0666 $(DEV)/afpgabscan c 132 7
py393/vrlg.py
View file @ d3767c2c
...@@ -263,6 +263,7 @@ SENS_PHASE_WIDTH = int ...@@ -263,6 +263,7 @@ SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str SENS_LENS_RADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL = int
CAMSYNC_PRE_MAGIC__TYPE = str CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int DEBUG_LOAD = int
...@@ -345,6 +346,7 @@ MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str ...@@ -345,6 +346,7 @@ MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str LAST_FRAME_BITS__RAW = str
SENS_DIVCLK_DIVIDE = int SENS_DIVCLK_DIVIDE = int
NEWPAR = int NEWPAR = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str SENS_LENS_COEFF__RAW = str
CMPRS_CONTROL_REG = int CMPRS_CONTROL_REG = int
GPIO_STATUS_REG_ADDR = int GPIO_STATUS_REG_ADDR = int
...@@ -1393,6 +1395,7 @@ NUM_CYCLES_04 = int ...@@ -1393,6 +1395,7 @@ NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str SENS_LENS_C__TYPE = str
MCONTR_PHY_16BIT_EXTRA__TYPE = str MCONTR_PHY_16BIT_EXTRA__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str CAMSYNC_TRIGGERED_BIT__RAW = str
SENSI2C_CMD_SOFT_SCL__RAW = str
CMPRS_CSAT_CR__TYPE = str CMPRS_CSAT_CR__TYPE = str
SENS_LENS_POST_SCALE__RAW = str SENS_LENS_POST_SCALE__RAW = str
DLY_LANE1_IDELAY = long DLY_LANE1_IDELAY = long
...@@ -1582,6 +1585,7 @@ CLK_STATUS__TYPE = str ...@@ -1582,6 +1585,7 @@ CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str CMPRS_COLOR20__TYPE = str
T_REFI__TYPE = str T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str MCONTR_CMD_WR_ADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int CMPRS_CSAT_CR_BITS = int
HIST_SAXI_ADDR_REL__TYPE = str HIST_SAXI_ADDR_REL__TYPE = str
...@@ -1629,6 +1633,7 @@ CMPRS_AFIMUX_MASK__RAW = str ...@@ -1629,6 +1633,7 @@ CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str MCNTRL_TILED_WINDOW_X0Y0__RAW = str
SENS_GAMMA_MODE_PAGE__TYPE = str SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str CMPRS_COLOR_SATURATION__TYPE = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_TAND = int SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str SENS_CTRL_QUADRANTS_EN__TYPE = str
...@@ -2040,6 +2045,7 @@ NUM_CYCLES_11__RAW = str ...@@ -2040,6 +2045,7 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSI2C_CMD_SOFT_SDA__RAW = str
SENSOR_CTRL_ADDR_MASK__RAW = str SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int NUM_CYCLES_LOW_BIT = int
......
py393/x393_axi_control_status.py
View file @ d3767c2c
...@@ -274,7 +274,7 @@ class X393AxiControlStatus(object): ...@@ -274,7 +274,7 @@ class X393AxiControlStatus(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param pattern 26-bit pattern to match @param pattern 26-bit pattern to match
@param mask 26-bit mask to enable pattern matching (0-s - ignore) @param mask 26-bit mask to enable pattern matching (0-s - ignore)
@param invert_match invert match (wait until matching condition becomes false) @param invert_match invert match (wait until matching condition becomes false)
...@@ -352,10 +352,10 @@ class X393AxiControlStatus(object): ...@@ -352,10 +352,10 @@ class X393AxiControlStatus(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
<seq_number> - 6-bit sequence number of the status message to be sent <seq_number> - 6-bit sequence number of the status message to be sent
""" """
self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f)) self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number & 0x3f))
def program_status_all( self, def program_status_all( self,
...@@ -367,7 +367,7 @@ class X393AxiControlStatus(object): ...@@ -367,7 +367,7 @@ class X393AxiControlStatus(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
......
py393/x393_cmprs.py
View file @ d3767c2c
...@@ -69,7 +69,7 @@ class X393Cmprs(object): ...@@ -69,7 +69,7 @@ class X393Cmprs(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
......
py393/x393_export_c.py
View file @ d3767c2c
...@@ -107,7 +107,10 @@ class X393ExportC(object): ...@@ -107,7 +107,10 @@ class X393ExportC(object):
* Author: auto-generated file, see %s * Author: auto-generated file, see %s
* Description: %s * Description: %s
*******************************************************************************/""" *******************************************************************************/"""
return header_template%(filename, datetime.date.today().isoformat(), os.path.basename(__file__), description) script_name = os.path.basename(__file__)
if script_name[-1] == "c":
script_name = script_name[:-1]
return header_template%(filename, datetime.date.today().isoformat(), script_name, description)
def save_typedefs(self, directory, filename): def save_typedefs(self, directory, filename):
description = 'typedef definitions for the x393 hardware registers' description = 'typedef definitions for the x393 hardware registers'
...@@ -125,7 +128,7 @@ class X393ExportC(object): ...@@ -125,7 +128,7 @@ class X393ExportC(object):
ld= self.define_macros() ld= self.define_macros()
ld+=self.define_other_macros() ld+=self.define_other_macros()
# Includes section # Includes section
txt = '\n#include "elphel/x393_types.h"\n' txt = '\n#include "x393_types.h"\n'
txt +='//#include "elphel/x393_defs.h // alternative variant"\n\n' txt +='//#include "elphel/x393_defs.h // alternative variant"\n\n'
txt +='// See elphel/x393_map.h for the ordered list of all I/O register addresses used\n' txt +='// See elphel/x393_map.h for the ordered list of all I/O register addresses used\n'
txt += '// init_mmio_ptr() should be called once before using any of the other declared functions\n\n' txt += '// init_mmio_ptr() should be called once before using any of the other declared functions\n\n'
...@@ -385,7 +388,7 @@ class X393ExportC(object): ...@@ -385,7 +388,7 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA", stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
data = self._enc_sensio_jtag(), data = self._enc_sensio_jtag(),
name = "x393_sensio_jpag", typ="wo", name = "x393_sensio_jtag", typ="wo",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
""" """
stypedefs += self.get_typedef32(comment = "Sensor delays (uses 4 DWORDs)", stypedefs += self.get_typedef32(comment = "Sensor delays (uses 4 DWORDs)",
...@@ -754,7 +757,7 @@ class X393ExportC(object): ...@@ -754,7 +757,7 @@ class X393ExportC(object):
(("X393_SENS_SYNC_LATE", c, vrlg.SENS_SYNC_RADDR + vrlg.SENS_SYNC_LATE + ba, ia, z3, "x393_sens_sync_late", "wo", "Configure frame sync delay")), (("X393_SENS_SYNC_LATE", c, vrlg.SENS_SYNC_RADDR + vrlg.SENS_SYNC_LATE + ba, ia, z3, "x393_sens_sync_late", "wo", "Configure frame sync delay")),
(("X393_SENSIO_CTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL + ba, ia, z3, "x393_sensio_ctl", "wo", "Configure sensor I/O port")), (("X393_SENSIO_CTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL + ba, ia, z3, "x393_sensio_ctl", "wo", "Configure sensor I/O port")),
(("X393_SENSIO_STATUS_CNTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_STATUS + ba, ia, z3, "x393_status_ctrl", "rw", "Set status control for SENSIO module")), (("X393_SENSIO_STATUS_CNTRL", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_STATUS + ba, ia, z3, "x393_status_ctrl", "rw", "Set status control for SENSIO module")),
(("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jpag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")), (("X393_SENSIO_JTAG", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_JTAG + ba, ia, z3, "x393_sensio_jtag", "wo", "Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
(("X393_SENSIO_WIDTH", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_WIDTH + ba, ia, z3, "x393_sensio_width", "rw", "Set sensor line in pixels (0 - use line sync from the sensor)")), (("X393_SENSIO_WIDTH", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_WIDTH + ba, ia, z3, "x393_sensio_width", "rw", "Set sensor line in pixels (0 - use line sync from the sensor)")),
# (("X393_SENSIO_DELAYS", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + ba, ia, z3, "x393_sensio_dly", "rw", "Sensor port input delays (uses 4 DWORDs)")), # (("X393_SENSIO_DELAYS", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + ba, ia, z3, "x393_sensio_dly", "rw", "Sensor port input delays (uses 4 DWORDs)")),
(("X393_SENSIO_TIM0", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + 0 + ba, ia, z3, "x393_sensio_tim0", "rw", "Sensor port i/o timing configuration, register 0")), (("X393_SENSIO_TIM0", c, vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS + 0 + ba, ia, z3, "x393_sensio_tim0", "rw", "Sensor port i/o timing configuration, register 0")),
...@@ -1681,7 +1684,7 @@ class X393ExportC(object): ...@@ -1681,7 +1684,7 @@ class X393ExportC(object):
dw=[] dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO")) dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data"))
dw.append(("i2c_fifo_cntrl", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)"))
dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("busy", 10, 1,0, "I2C sequencer busy"))
dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update")) dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update"))
dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number"))
...@@ -1717,7 +1720,7 @@ class X393ExportC(object): ...@@ -1717,7 +1720,7 @@ class X393ExportC(object):
def _enc_i2c_tbl_addr(self): def _enc_i2c_tbl_addr(self):
dw=[] dw=[]
dw.append(("tbl_addr", 0, 8,0, "Address/length in 64-bit words (<<3 to get byte address)")) dw.append(("tbl_addr", 0, 8,0, "I2C table index"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,3, "Should be 3 to select table address write mode")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,3, "Should be 3 to select table address write mode"))
return dw return dw
...@@ -1735,7 +1738,7 @@ class X393ExportC(object): ...@@ -1735,7 +1738,7 @@ class X393ExportC(object):
dw=[] dw=[]
dw.append(("rah", vrlg.SENSI2C_TBL_RAH, vrlg.SENSI2C_TBL_RAH_BITS, 0, "High byte of the i2c register address")) dw.append(("rah", vrlg.SENSI2C_TBL_RAH, vrlg.SENSI2C_TBL_RAH_BITS, 0, "High byte of the i2c register address"))
dw.append(("rnw", vrlg.SENSI2C_TBL_RNWREG, 1, 0, "Read/not write i2c register, should be 1 here")) dw.append(("rnw", vrlg.SENSI2C_TBL_RNWREG, 1, 0, "Read/not write i2c register, should be 1 here"))
dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..18, 0 means '8')")) dw.append(("nbrd", vrlg.SENSI2C_TBL_NBRD, vrlg.SENSI2C_TBL_NBRD_BITS,0, "Number of bytes to read (1..8, 0 means '8')"))
dw.append(("nabrd", vrlg.SENSI2C_TBL_NABRD, 1, 0, "Number of address bytes for read (0 - one byte, 1 - two bytes)")) dw.append(("nabrd", vrlg.SENSI2C_TBL_NABRD, 1, 0, "Number of address bytes for read (0 - one byte, 1 - two bytes)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period")) dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
...@@ -1747,6 +1750,10 @@ class X393ExportC(object): ...@@ -1747,6 +1750,10 @@ class X393ExportC(object):
dw.append(("sda_release", vrlg.SENSI2C_CMD_ACIVE_EARLY0, 1,0, "Release SDA early if next bit ==1 (valid with drive_ctl)")) dw.append(("sda_release", vrlg.SENSI2C_CMD_ACIVE_EARLY0, 1,0, "Release SDA early if next bit ==1 (valid with drive_ctl)"))
dw.append(("drive_ctl", vrlg.SENSI2C_CMD_ACIVE, 1,0, "0 - nop, 1 - set sda_release and sda_drive_high")) dw.append(("drive_ctl", vrlg.SENSI2C_CMD_ACIVE, 1,0, "0 - nop, 1 - set sda_release and sda_drive_high"))
dw.append(("next_fifo_rd", vrlg.SENSI2C_CMD_FIFO_RD, 1,0, "Advance I2C read FIFO pointer")) dw.append(("next_fifo_rd", vrlg.SENSI2C_CMD_FIFO_RD, 1,0, "Advance I2C read FIFO pointer"))
dw.append(("soft_scl", vrlg.SENSI2C_CMD_SOFT_SCL, 2,0, "Control SCL pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("soft_sda", vrlg.SENSI2C_CMD_SOFT_SDA, 2,0, "Control SDA pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
dw.append(("cmd_run", vrlg.SENSI2C_CMD_RUN-1, 2,0, "Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run ")) dw.append(("cmd_run", vrlg.SENSI2C_CMD_RUN-1, 2,0, "Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run "))
dw.append(("reset", vrlg.SENSI2C_CMD_RESET, 1,0, "Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command")) dw.append(("reset", vrlg.SENSI2C_CMD_RESET, 1,0, "Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,0, "Should be 0 to select controls")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2,0, "Should be 0 to select controls"))
......
py393/x393_gpio.py
View file @ d3767c2c
...@@ -66,7 +66,7 @@ class X393GPIO(object): ...@@ -66,7 +66,7 @@ class X393GPIO(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
......
py393/x393_jpeg.py
View file @ d3767c2c
...@@ -828,7 +828,7 @@ class X393Jpeg(object): ...@@ -828,7 +828,7 @@ class X393Jpeg(object):
y_quality = y_quality, #80, y_quality = y_quality, #80,
c_quality = c_quality, c_quality = c_quality,
portrait = portrait, portrait = portrait,
color_mode = window["cmode"], # # color_mode = window["cmode"], #
byrshift = byrshift, byrshift = byrshift,
verbose = verbose) verbose = verbose)
html_text += html_text_finish html_text += html_text_finish
...@@ -965,6 +965,72 @@ class X393Jpeg(object): ...@@ -965,6 +965,72 @@ class X393Jpeg(object):
ff d9 ff d9
""" """
""" """
################## 10359 ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12"
measure_all "*DI"
program_status_sensor_io all 1 0
print_status_sensor_io all
setup_all_sensors True None 0x4
################## Parallel ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12"
measure_all "*DI"
setup_all_sensors True None 0xf
#set quadrants
set_sensor_io_ctl 0 None None None None None 0 0xe
set_sensor_io_ctl 1 None None None None None 0 0xe
#set_sensor_io_ctl 2 None None None None None 0 0x4
set_sensor_io_ctl 2 None None None None None 0 0xe
set_sensor_io_ctl 3 None None None None None 0 0xe
# Set Bayer = 3 (probably #1 and #3 need different hact/pxd delays to use the same compressor bayer for all channels)
compressor_control all None None None None None 3
#Get rid of the corrupted last pixel column
#longer line (default 0xa1f)
write_sensor_i2c all 1 0 0x90040a23
#increase scanline write (memory controller) width in 16-bursts (was 0xa2)
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#Gamma 0.57
program_gamma all 0 0.57 0.04
#colors - outdoor
write_sensor_i2c all 1 0 0x9035000a
write_sensor_i2c all 1 0 0x902c000e
write_sensor_i2c all 1 0 0x902d000d
#colors indoor
write_sensor_i2c all 1 0 0x90350009
write_sensor_i2c all 1 0 0x902c000f
write_sensor_i2c all 1 0 0x902d000a
#exposure 0x100 lines (default was 0x797)
write_sensor_i2c all 1 0 0x90090100
#exposure 0x797 (default)
write_sensor_i2c all 1 0 0x90090797
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
#jpeg_write "img.jpeg" 0
jpeg_write "img.jpeg" All
#changing quality (example 85%):
set_qtables all 0 85
compressor_control all 2
#jpeg_write "img.jpeg" all 85
jpeg_write "img.jpeg" 0 85
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "HISPI" setupSensorsPower "HISPI"
measure_all "*DI" measure_all "*DI"
......
py393/x393_mcntrl_adjust.py
View file @ d3767c2c
...@@ -1530,7 +1530,9 @@ class X393McntrlAdjust(object): ...@@ -1530,7 +1530,9 @@ class X393McntrlAdjust(object):
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized") # raise Exception("Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized")
#disabling check 04.09.2016
print ("raise Exception Write levelling gave unexpected data, aborting (may be wrong command/address delay, incorrectly initialized. Phase: %d, cmda_odly_lin=%d"%(phase,cmda_odly_lin))
dqso_cache[dly] = wlev_rslt dqso_cache[dly] = wlev_rslt
if quiet < 1: if quiet < 1:
print ('measure_dqso(%d) - new measurement'%(dly)) print ('measure_dqso(%d) - new measurement'%(dly))
...@@ -3242,13 +3244,13 @@ class X393McntrlAdjust(object): ...@@ -3242,13 +3244,13 @@ class X393McntrlAdjust(object):
dqsi_safe_phase=dqsi_safe_phase, dqsi_safe_phase=dqsi_safe_phase,
ra = ra, # 0, ra = ra, # 0,
ba = ba, # 0, ba = ba, # 0,
quiet=quiet+1, #1, quiet=quiet, #+1, #1,
single=True) # single=False) single=True) # single=False)
pass2=self.measure_addr_odelay(safe_phase=safe_phase, #0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin pass2=self.measure_addr_odelay(safe_phase=safe_phase, #0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
dqsi_safe_phase=dqsi_safe_phase, dqsi_safe_phase=dqsi_safe_phase,
ra = ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1), # 0, ra = ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1), # 0,
ba = ba ^ ((1 << num_ba)-1), # 0, ba = ba ^ ((1 << num_ba)-1), # 0,
quiet=quiet+1, #1, quiet=quiet, #+1, #1,
single=True) # single=False) single=True) # single=False)
self.adjustment_state['addr_meas']=[pass1,pass2] self.adjustment_state['addr_meas']=[pass1,pass2]
if (quiet<4): if (quiet<4):
...@@ -3279,6 +3281,9 @@ class X393McntrlAdjust(object): ...@@ -3279,6 +3281,9 @@ class X393McntrlAdjust(object):
print ("?", end=" ") print ("?", end=" ")
print() print()
return [pass1,pass2] return [pass1,pass2]
if quiet<3:
print("Writing good data to ra=0x%x, ba = 0x%x" %(ra,ba))
dly_steps=self.x393_mcntrl_timing.get_dly_steps() dly_steps=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5) numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
...@@ -3297,6 +3302,10 @@ class X393McntrlAdjust(object): ...@@ -3297,6 +3302,10 @@ class X393McntrlAdjust(object):
inv_ra=ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1) inv_ra=ra ^ ((1 << vrlg.ADDRESS_NUMBER)-1)
ca= ra & ((1 << vrlg.COLADDR_NUMBER) -1) ca= ra & ((1 << vrlg.COLADDR_NUMBER) -1)
inv_ba=ba ^ ((1 << num_ba)-1) inv_ba=ba ^ ((1 << num_ba)-1)
print ("quiet=",quiet)
if quiet<4:
print("Writing good data to ra=0x%x, ba = 0x%x, ca = 0x%x, refresh will use: inv_ra = 0x%x, inv_ba=0x%x" %(ra,ba,ca,inv_ra,inv_ba))
if not "cmda_bspe" in self.adjustment_state: if not "cmda_bspe" in self.adjustment_state:
raise Exception ("No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first.") raise Exception ("No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first.")
#create a list of None/optimal cmda determined earlier #create a list of None/optimal cmda determined earlier
...@@ -3325,7 +3334,12 @@ class X393McntrlAdjust(object): ...@@ -3325,7 +3334,12 @@ class X393McntrlAdjust(object):
good_patt=0xaaaa good_patt=0xaaaa
bad_patt = good_patt ^ 0xffff bad_patt = good_patt ^ 0xffff
# find first suitable phase # find first suitable phase
for phase in range(numPhaseSteps): """
phase=0 seems to be bad (during wlev), ***temporarily*** just start from 90 degrees shift
"""
# for phase in range(numPhaseSteps):
for phase_tmp in range(numPhaseSteps):
phase = (phase_tmp + (numPhaseSteps//4)) % numPhaseSteps
try: try:
ph_dlys= self.get_all_delays(phase=phase, ph_dlys= self.get_all_delays(phase=phase,
filter_cmda= DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number> filter_cmda= DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number>
...@@ -3336,7 +3350,7 @@ class X393McntrlAdjust(object): ...@@ -3336,7 +3350,7 @@ class X393McntrlAdjust(object):
cost= None, cost= None,
forgive_missing=False, forgive_missing=False,
maxPhaseErrorsPS = maxPhaseErrorsPS, #CMDA, DQSI, DQSO maxPhaseErrorsPS = maxPhaseErrorsPS, #CMDA, DQSI, DQSO
quiet= quiet) quiet= quiet-1) # quiet)
if not ph_dlys is None: if not ph_dlys is None:
break break
except: except:
...@@ -3353,8 +3367,11 @@ class X393McntrlAdjust(object): ...@@ -3353,8 +3367,11 @@ class X393McntrlAdjust(object):
inv_ba, inv_ba,
0) # verbose=0 0) # verbose=0
# set usable timing, enable refresh # set usable timing, enable refresh
if quiet <3 : # if quiet <3 :
if quiet < 4 :
print ("+++ dqsi_safe_phase=",dqsi_safe_phase) print ("+++ dqsi_safe_phase=",dqsi_safe_phase)
print ("Setting all delays to write good/bad data, phase=",phase)
used_delays=self.set_delays(phase=phase, used_delays=self.set_delays(phase=phase,
filter_cmda=DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number> filter_cmda=DFLT_DLY_FILT, # may be special case: 'S<safe_phase_as_float_number>
filter_dqsi=DFLT_DLY_FILT, filter_dqsi=DFLT_DLY_FILT,
...@@ -3365,15 +3382,15 @@ class X393McntrlAdjust(object): ...@@ -3365,15 +3382,15 @@ class X393McntrlAdjust(object):
refresh=True, refresh=True,
forgive_missing=True, forgive_missing=True,
maxPhaseErrorsPS=maxPhaseErrorsPS, maxPhaseErrorsPS=maxPhaseErrorsPS,
quiet=quiet) quiet=0) # quiet) # To see what delays where used when writing
if used_delays is None: if used_delays is None:
raise Exception("measure_addr_odelay(): failed to set phase = %d"%(phase)) # raise Exception("measure_addr_odelay(): failed to set phase = %d"%(phase)) #
#Write 0xaaaa pattern to correct block (all used words), address number - to all with a single bit different #Write 0xaaaa pattern to correct block (all used words), address number - to all with a single bit different
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_wr) self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_wr)
#prepare and writ 'correct' block: #prepare and writ 'correct' block:
wdata16_good=(good_patt,)*(8*(nbursts+3)) wdata16_good=(good_patt,)*(8*(nbursts+7)) #3))
wdata32_good=convert_mem16_to_w32(wdata16_good) wdata32_good=convert_mem16_to_w32(wdata16_good)
wdata16_bad=(bad_patt,)*(8*(nbursts+3)) wdata16_bad=(bad_patt,)*(8*(nbursts+7)) #3))
wdata32_bad=convert_mem16_to_w32(wdata16_bad) wdata32_bad=convert_mem16_to_w32(wdata16_bad)
# comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 # comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
# comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 # comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
...@@ -3381,10 +3398,17 @@ class X393McntrlAdjust(object): ...@@ -3381,10 +3398,17 @@ class X393McntrlAdjust(object):
comp32_bad= wdata32_bad[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32 comp32_bad= wdata32_bad[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,quiet) # fill block memory (channel, page, number) # self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,quiet) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+3,extraTgl,sel_wr) # set sequence to write 'correct' block self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,0 ) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_rd) # set sequence to read block (will always be the same address) self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,0 ) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+7,extraTgl,sel_wr) # 3,extraTgl,sel_wr) # set sequence to write 'correct' block
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+7,extraTgl,sel_wr) #3,extraTgl,sel_wr)# set sequence to write 'correct' block ######
# self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+3,sel_rd) # set sequence to read block (will always be the same address)
self.x393_pio_sequences.set_read_block(ba,ra,ca,nbursts+7,sel_rd) # set sequence to read block (will always be the same address)
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write 'correct' block ################# Repeat
#prepare and write all alternative blocks (different by one address/bank #prepare and write all alternative blocks (different by one address/bank
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_bad,quiet) # fill block memory (channel, page, number) self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_bad,quiet) # fill block memory (channel, page, number)
raba_bits=[] raba_bits=[]
...@@ -3393,12 +3417,15 @@ class X393McntrlAdjust(object): ...@@ -3393,12 +3417,15 @@ class X393McntrlAdjust(object):
for addr_bit in range(vrlg.ADDRESS_NUMBER): for addr_bit in range(vrlg.ADDRESS_NUMBER):
raba_bits.append((addr_bit,None)) raba_bits.append((addr_bit,None))
ra_alt=ra ^ (1<<addr_bit) ra_alt=ra ^ (1<<addr_bit)
self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block # self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.set_write_block(ba,ra_alt,ca,nbursts+7,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block
for bank_bit in range(num_ba): for bank_bit in range(num_ba):
raba_bits.append((None,bank_bit)) raba_bits.append((None,bank_bit))
ba_alt=ra ^ (1<<bank_bit) # ba_alt=ra ^ (1<<bank_bit) # Bug? 04.10.2016
self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block ba_alt=ba ^ (1<<bank_bit)
# self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+3,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.set_write_block(ba_alt,ra,ca,nbursts+7,extraTgl,sel_wr,(0,1)[quiet<2]) # set sequence to write alternative (by one address bit) block
self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block self.x393_pio_sequences.write_block() #page= 0, wait_complete=1) # write alternative block
# For each valid phase, set valid delays, then find marginal delay for one bit (start with the longest available delay? # For each valid phase, set valid delays, then find marginal delay for one bit (start with the longest available delay?
# if got for one bit - try other bits in vicinity # if got for one bit - try other bits in vicinity
...@@ -3431,14 +3458,12 @@ class X393McntrlAdjust(object): ...@@ -3431,14 +3458,12 @@ class X393McntrlAdjust(object):
elif buf==comp32_bad: elif buf==comp32_bad:
meas=False meas=False
else: else:
print ("Inconclusive result for comparing read data for phase=%d, addr_bit=%s, bank_bit=%s dly=%d"%(phase,str(addr_bit),str(bank_bit),dly)) print ("Inconclusive result for comparing read data for phase=%d, addr_bit=%s, bank_bit=%s dly=%d"%(phase,str(addr_bit),str(bank_bit),dly), end = " ")
# print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")") # print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")")
print ("Data read from memory=%s(%s)"%(self.hex_list(buf),self.hex_list(convert_w32_to_mem16(buf)))) print ("Data read from memory=%s(%s)"%(self.hex_list(buf),self.hex_list(convert_w32_to_mem16(buf))))
#hex_list #hex_list
# print ("Expected 'good' data=",comp32_good, "(",convert_w32_to_mem16(comp32_good),")") # print ("Expected 'good' data=%s(%s)"%(self.hex_list(comp32_good),self.hex_list(convert_w32_to_mem16(comp32_good))))
print ("Expected 'good' data=%s(%s)"%(self.hex_list(comp32_good),self.hex_list(convert_w32_to_mem16(comp32_good)))) # print ("Expected 'bad' data=%s(%s)"%(self.hex_list(comp32_bad),self.hex_list(convert_w32_to_mem16(comp32_bad))))
# print ("Expected 'bad' data=", comp32_bad, "(",convert_w32_to_mem16(comp32_bad),")")
print ("Expected 'bad' data=%s(%s)"%(self.hex_list(comp32_bad),self.hex_list(convert_w32_to_mem16(comp32_bad))))
meas=None meas=None
meas_cache[dly]=meas meas_cache[dly]=meas
if not meas is None: if not meas is None:
...@@ -5727,6 +5752,10 @@ write_settings= { ...@@ -5727,6 +5752,10 @@ write_settings= {
Calculate finedelay corrections and finally optimal delay value for each line each phase Calculate finedelay corrections and finally optimal delay value for each line each phase
""" """
# self.load_hardcoded_data() # TODO: TEMPORARY - remove later # self.load_hardcoded_data() # TODO: TEMPORARY - remove later
quiet = 0 # 04.10.2016
try: try:
# addr_odelay=self.adjustment_state['addr_odelay_meas'] # addr_odelay=self.adjustment_state['addr_odelay_meas']
addr_odelay=self.adjustment_state['addr_meas'] addr_odelay=self.adjustment_state['addr_meas']
......
py393/x393_pio_sequences.py
View file @ d3767c2c
...@@ -1152,7 +1152,8 @@ class X393PIOSequences(object): ...@@ -1152,7 +1152,8 @@ class X393PIOSequences(object):
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
#calculate 1-s ratio for both lanes #calculate 1-s ratio for both lanes
rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1] # rslt=[0.0,0.0,0.0] # last word - number of "problem" bytes that have non-ones in bits [7:1]
rslt=[0.0,0.0,0.0,0.0] # last 2 words - number of "problem" bytes that have non-ones in bits [7:1] or byte is not the same
for i in range(0,numBufWords): for i in range(0,numBufWords):
rslt[i & 1] += ((buf[i] & 1) + rslt[i & 1] += ((buf[i] & 1) +
...@@ -1164,11 +1165,25 @@ class X393PIOSequences(object): ...@@ -1164,11 +1165,25 @@ class X393PIOSequences(object):
(0,1)[(buf[i] & 0xfe00) != 0]+ (0,1)[(buf[i] & 0xfe00) != 0]+
(0,1)[(buf[i] & 0xfe0000) != 0]+ (0,1)[(buf[i] & 0xfe0000) != 0]+
(0,1)[(buf[i] & 0xfe000000) != 0]) (0,1)[(buf[i] & 0xfe000000) != 0])
bm = buf[i] & 0x01010101
bm |= (bm << 1)
bm |= (bm << 2)
bm |= (bm << 4)
bm ^= buf[i]
rslt[3] += ((0,1)[(bm & 0xfe) != 0]+
(0,1)[(bm & 0xfe00) != 0]+
(0,1)[(bm & 0xfe0000) != 0]+
(0,1)[(bm & 0xfe000000) != 0])
for i in range(2): for i in range(2):
rslt[i]/=2*numBufWords rslt[i]/=2*numBufWords
rslt[2]/=4*numBufWords rslt[2]/=4*numBufWords
rslt[3]/=4*numBufWords
if quiet <1: if quiet <1:
print ("WLEV lanes ratios: %f %f, non 0x00/0x01 bytes: %f"%(rslt[0],rslt[1],rslt[2])) print ("WLEV lanes ratios: %f %f, non 0x00/0x01 byte: %f, non 0x00/0xffs: %f"%(rslt[0],rslt[1],rslt[2],rslt[3]))
if (rslt[3] < rslt[2]):
rslt[2] = rslt[3]
return rslt return rslt
def read_levelling(self, def read_levelling(self,
......
py393/x393_rtc.py
View file @ d3767c2c
...@@ -67,7 +67,7 @@ class X393Rtc(object): ...@@ -67,7 +67,7 @@ class X393Rtc(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
......
py393/x393_sens_cmprs.py
View file @ d3767c2c
...@@ -188,11 +188,18 @@ class X393SensCmprs(object): ...@@ -188,11 +188,18 @@ class X393SensCmprs(object):
print(voltage_mv, file = f) print(voltage_mv, file = f)
if quiet == 0: if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv)) print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1) time.sleep(0.1)
def setupSensorsPower(self, ifaceType, quiet=0): def setupSensorsPower(self, ifaceType, pairs = "all", quiet=0):
for sub_pair in (0,1): try:
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"]) if (pairs == all) or (pairs[0].upper() == "A"): #all is a built-in function
pairs = (0,1)
except:
pass
if not isinstance(pairs,(list,tuple)):
pairs = (pairs,)
for pair in pairs:
self.setSensorIfaceVoltagePower(pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0): def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
""" """
...@@ -208,16 +215,19 @@ class X393SensCmprs(object): ...@@ -208,16 +215,19 @@ class X393SensCmprs(object):
if self.DRY_MODE: if self.DRY_MODE:
print ("Not defined for simulation mode") print ("Not defined for simulation mode")
return return
if quiet == 0:
print ("Turning on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
time.sleep(0.2)
with open (POWER393_PATH + "/channels_en","w") as f: with open (POWER393_PATH + "/channels_en","w") as f:
print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f) print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
if quiet == 0: if quiet == 0:
print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair])) print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1) time.sleep(0.2)
with open (POWER393_PATH + "/channels_en","w") as f: with open (POWER393_PATH + "/channels_en","w") as f:
print(("vp33sens01", "vp33sens23")[sub_pair], file = f) print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
if quiet == 0: if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair])) print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1) time.sleep(0.2)
# for sub_pair in (0,1): # for sub_pair in (0,1):
# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"]) # self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
...@@ -1419,7 +1429,7 @@ class X393SensCmprs(object): ...@@ -1419,7 +1429,7 @@ class X393SensCmprs(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
......
py393/x393_sensor.py
View file @ d3767c2c
...@@ -32,6 +32,8 @@ __email__ = "andrey@elphel.com" ...@@ -32,6 +32,8 @@ __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
#import sys #import sys
#import pickle #import pickle
import struct
from x393_mem import X393Mem from x393_mem import X393Mem
import x393_axi_control_status import x393_axi_control_status
...@@ -81,7 +83,7 @@ class X393Sensor(object): ...@@ -81,7 +83,7 @@ class X393Sensor(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
...@@ -101,31 +103,57 @@ class X393Sensor(object): ...@@ -101,31 +103,57 @@ class X393Sensor(object):
0: disable status generation, 0: disable status generation,
1: single status request, 1: single status request,
2: auto status, keep specified seq number, 2: auto status, keep specified seq number,
4: auto, inc sequence number 3: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent @param seq_number - 6-bit sequence number of the status message to be sent
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.program_status_sensor_io (num_sensor = num_sensor,
mode = mode,
seq_num = seq_num)
return
except:
pass
self.x393_axi_tasks.program_status ( self.x393_axi_tasks.program_status (
vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSIO_RADDR, vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSIO_RADDR,
vrlg.SENSIO_STATUS, vrlg.SENSIO_STATUS,
mode, mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0, seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def get_status_sensor_io ( self, def get_status_sensor_io ( self,
num_sensor): num_sensor="All"):
""" """
Read sensor_io status word (no sync) Read sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3) @param num_sensor - number of the sensor port (0..3)
@return sesnor_io status @return sensor_io status
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
rslt = []
for num_sensor in range(4):
rslt.append(self.program_status_sensor_io (num_sensor = num_sensor))
return rslt
except:
pass
return self.x393_axi_tasks.read_status( return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL)) address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))
def print_status_sensor_io (self, def print_status_sensor_io (self,
num_sensor): num_sensor="All"):
""" """
Print sensor_io status word (no sync) Print sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3) @param num_sensor - number of the sensor port (0..3)
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
print ("\n ==== Sensor %d"%(num_sensor))
self.print_status_sensor_io (num_sensor = num_sensor)
return
except:
pass
status= self.get_status_sensor_io(num_sensor) status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor)) print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk #last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
...@@ -138,10 +166,17 @@ class X393Sensor(object): ...@@ -138,10 +166,17 @@ class X393Sensor(object):
print (" eof_mclk = %d"%((status>>18) & 1)) print (" eof_mclk = %d"%((status>>18) & 1))
print (" sof_mclk = %d"%((status>>17) & 1)) print (" sof_mclk = %d"%((status>>17) & 1))
print (" sol_mclk = %d"%((status>>16) & 1)) print (" sol_mclk = %d"%((status>>16) & 1))
"""
#Folowing 5 bits may be just temporarily available
print (" irst = %d"%((status>>20) & 1))
print ("async_prst_with_sens_mrst = %d"%((status>>19) & 1))
print (" imrst = %d"%((status>>18) & 1))
print (" rst_mmcm = %d"%((status>>17) & 1))
print (" pxd_out_pre[1] = %d"%((status>>16) & 1))
print (" vact_alive = %d"%((status>>15) & 1)) print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1)) print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1)) # print (" hact_alive = %d"%((status>>13) & 1))
"""
print (" hact_run = %d"%((status>>13) & 1)) print (" hact_run = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1)) print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1)) print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
...@@ -154,21 +189,37 @@ class X393Sensor(object): ...@@ -154,21 +189,37 @@ class X393Sensor(object):
print (" seq = %d"%((status>>26) & 0x3f)) print (" seq = %d"%((status>>26) & 0x3f))
#vact_alive, hact_ext_alive, hact_alive #vact_alive, hact_ext_alive, hact_alive
def get_status_sensor_i2c ( self, def get_status_sensor_i2c ( self,
num_sensor): num_sensor="All"):
""" """
Read sensor_i2c status word (no sync) Read sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3) @param num_sensor - number of the sensor port (0..3)
@return sesnor_io status @return sesnor_io status
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
rslt = []
for num_sensor in range(4):
rslt.append(self.get_status_sensor_i2c (num_sensor = num_sensor))
return rslt
except:
pass
return self.x393_axi_tasks.read_status( return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL)) address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL))
def print_status_sensor_i2c (self, def print_status_sensor_i2c (self,
num_sensor): num_sensor="All"):
""" """
Print sensor_i2c status word (no sync) Print sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3) @param num_sensor - number of the sensor port (0..3)
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
print ("\n ==== Sensor %d"%(num_sensor))
self.print_status_sensor_i2c (num_sensor = num_sensor)
return
except:
pass
status= self.get_status_sensor_i2c(num_sensor) status= self.get_status_sensor_i2c(num_sensor)
print ("print_status_sensor_i2c(%d):"%(num_sensor)) print ("print_status_sensor_i2c(%d):"%(num_sensor))
print (" reset_on = %d"%((status>> 7) & 1)) print (" reset_on = %d"%((status>> 7) & 1))
...@@ -210,6 +261,8 @@ class X393Sensor(object): ...@@ -210,6 +261,8 @@ class X393Sensor(object):
active_sda = None, active_sda = None,
early_release_0 = None, early_release_0 = None,
advance_FIFO = None, advance_FIFO = None,
sda = None,
scl = None,
verbose = 1): verbose = 1):
""" """
@param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command @param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
...@@ -217,12 +270,39 @@ class X393Sensor(object): ...@@ -217,12 +270,39 @@ class X393Sensor(object):
@param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible @param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible
@param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup) @param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup)
@param advance_FIFO - advance i2c read FIFO @param advance_FIFO - advance i2c read FIFO
@param sda - control SDA line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param scl - control SCL line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param verbose - verbose level @param verbose - verbose level
@return combined command word. @return combined command word.
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters) active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
""" """
if verbose>0: def parse_sda_scl(val):
print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", active_sda = ",active_sda,", early_release_0 = ",early_release_0) if val is None:
return 0
elif isinstance(val, (unicode,str)):
if not val:
return 0
if val[0] in "lL0":
return 1
elif val[0] in "hH1":
return 2
elif val[0] in "iI":
return 3
else:
print("Unrecognized value for SDA/SCL: %s, should be in lL0hH1iI (or None/ empty string)"%(val))
return 0
else:
if val == 0:
return 1
elif val == 1:
return 2
else:
return 3
if verbose>1:
print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", active_sda = ",active_sda,", early_release_0 = ",early_release_0,
", sda=",sda,", scl=",scl)
rslt = 0 rslt = 0
rslt |= (0,1)[rst_cmd] << vrlg.SENSI2C_CMD_RESET rslt |= (0,1)[rst_cmd] << vrlg.SENSI2C_CMD_RESET
if not run_cmd is None: if not run_cmd is None:
...@@ -234,6 +314,10 @@ class X393Sensor(object): ...@@ -234,6 +314,10 @@ class X393Sensor(object):
rslt |= 1 << vrlg.SENSI2C_CMD_ACIVE rslt |= 1 << vrlg.SENSI2C_CMD_ACIVE
if advance_FIFO: if advance_FIFO:
rslt |= 1 << vrlg.SENSI2C_CMD_FIFO_RD rslt |= 1 << vrlg.SENSI2C_CMD_FIFO_RD
rslt |= parse_sda_scl(sda) << vrlg.SENSI2C_CMD_SOFT_SDA
rslt |= parse_sda_scl(scl) << vrlg.SENSI2C_CMD_SOFT_SCL
if verbose>0:
print (" => 0x%x"%(rslt))
return rslt return rslt
...@@ -416,6 +500,8 @@ class X393Sensor(object): ...@@ -416,6 +500,8 @@ class X393Sensor(object):
active_sda = None, active_sda = None,
early_release_0 = None, early_release_0 = None,
advance_FIFO = None, advance_FIFO = None,
sda = None,
scl = None,
verbose = 1): verbose = 1):
""" """
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
...@@ -424,6 +510,8 @@ class X393Sensor(object): ...@@ -424,6 +510,8 @@ class X393Sensor(object):
@param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible @param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible
@param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup) @param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup)
@param advance_FIFO - advance i2c read FIFO @param advance_FIFO - advance i2c read FIFO
@param sda - control SDA line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param scl - control SCL line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param verbose - verbose level @param verbose - verbose level
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters) active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
...@@ -435,6 +523,8 @@ class X393Sensor(object): ...@@ -435,6 +523,8 @@ class X393Sensor(object):
active_sda = active_sda, active_sda = active_sda,
early_release_0 = early_release_0, early_release_0 = early_release_0,
advance_FIFO = advance_FIFO, advance_FIFO = advance_FIFO,
sda = sda,
scl = scl,
verbose = verbose)) verbose = verbose))
def set_sensor_i2c_table_reg_wr (self, def set_sensor_i2c_table_reg_wr (self,
...@@ -883,6 +973,505 @@ class X393Sensor(object): ...@@ -883,6 +973,505 @@ class X393Sensor(object):
tdi = tdi) tdi = tdi)
self.x393_axi_tasks.write_control_register(reg_addr, data) self.x393_axi_tasks.write_control_register(reg_addr, data)
# def jtag_prep_status(self, chn):
# seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f
# self.program_status_sensor_io(num_sensor = num_sensor,
# mode = 1, # input [1:0] mode;
# seq_num = seq_num) # input [5:0] seq_num;
# return seq_num
def jtag_get_tdo(self, chn):
seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f
self.program_status_sensor_io(num_sensor = chn,
mode = 1, # input [1:0] mode;
seq_num = seq_num) # input [5:0] seq_num;
for _ in range(10):
stat = self.get_status_sensor_io(num_sensor = chn)
if seq_num == ((stat >> 26) & 0x3f):
break
else:
print ("wait_sensio_status(): Failed to get seq_num== 0x%x, current is 0x%x"%(seq_num, (stat >> 26) & 0x3f))
return (stat >> 25) & 1
def jtag_send(self, chn, tms, ln, d):
i = ln & 7
if (i == 0):
i = 8
d &= 0xff;
r = 0
while i > 0:
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 0,
tms = tms,
tdi = ((d << 1) >> 8) & 1)
d <<= 1
r = (r << 1) + self.jtag_get_tdo(chn)
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 1,
tms = None,
tdi = None)
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 0,
tms = None,
tdi = None)
i -= 1
return r
def jtag_write_bits (self,
chn,
buf, # data to write
ln, # number of bits to write
# check, # compare readback data with previously written, abort on mismatch
last): # output last bit with TMS=1
# prev = None): # if null - don't use
rbuf = []
r = 0
for d0 in buf:
d=d0
for _ in range(8):
if ln >0:
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 0,
tms = (0,1)[(ln == 1) and last],
tdi = ((d << 1) >> 8) & 1)
d <<= 1
r = (r << 1) + self.jtag_get_tdo(chn)
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 1,
tms = None,
tdi = None)
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = None,
tck = 0,
tms = None,
tdi = None)
else:
r <<= 1
ln -= 1
rbuf.append(r & 0xff)
return rbuf
def jtag_set_pgm_mode(self,chn,en):
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = en,
prog = None,
tck = 0,
tms = None,
tdi = None)
def jtag_set_pgm(self,chn,en):
self.set_sensor_io_jtag (num_sensor = chn,
pgmen = None,
prog = en,
tck = 0,
tms = None,
tdi = None)
def JTAG_openChannel (self, chn):
self.jtag_set_pgm_mode (chn, 1);
self.jtag_set_pgm (chn, 1)
self.jtag_set_pgm (chn, 0)
time.sleep (0.01)
self.jtag_send (chn, 1, 5, 0 ) # set Test-Logic-Reset state
self.jtag_send (chn, 0, 1, 0 ) # set Run-Test-Idle state
def JTAG_EXTEST (self, chn, buf, ln):
# self.jtag_send(chn, 1, 5, 0 ) # step 1 - set Test-Logic-Reset state
# self.jtag_send(chn, 0, 1, 0 ) # step 2 - set Run-Test-Idle state
self.jtag_send(chn, 1, 2, 0 ) # step 3 - set SELECT-IR state
self.jtag_send(chn, 0, 2, 0 ) # step 4 - set SHIFT-IR state
self.jtag_send(chn, 0, 5, 0xf0) # step 5 - start of EXTEST
self.jtag_send(chn, 1, 1, 0 ) # step 6 - finish EXTEST
self.jtag_send(chn, 1, 2, 0 ) # step 7 - set SELECT-DR state
self.jtag_send(chn, 0, 2, 0 ) # step 8 - set CAPTURE-DR state
rbuf = self.jtag_write_bits (chn = chn,
buf = buf, # data to write
ln = ln, # number of bytes to write
last = 1)
self.jtag_send(chn, 1, 1, 0 ) #step 9 - set UPDATE-DR state
return rbuf
# /dev/sfpgabscan0
def readbscan(self, filename):
ffs=struct.pack("B",0xff)*97
with open(filename,'r+') as jtag:
jtag.write(ffs)
jtag.seek (0,0)
boundary= jtag.read(97)
return boundary
def checkSclSda(self, chn, verbose = 1):
'''
Check which board is connected to the sensor board
@param chn - sensor port number (0..3)
@param verbose - if >0, print debug output
@return - name of the FPGA-based board detected, "sensor" (grounded pad 7) or "" if none detected
'''
def print_i2c(chn):
self.program_status_sensor_i2c(num_sensor = chn, mode = 1, seq_num = 0)
status= self.get_status_sensor_i2c(num_sensor = chn)
sda_in =(status>>25) & 1
scl_in =(status>>24) & 1
print ("chn = %d, scl = %d, sda = %d"%(chn,scl_in, sda_in))
def print_bv(chn, boundary, value, key):
self.program_status_sensor_i2c(num_sensor = chn, mode = 1, seq_num = 0)
status= self.get_status_sensor_i2c(num_sensor = chn)
sda_in =(status>>25) & 1
scl_in =(status>>24) & 1
print ("%d: sda = %d, bit number SDA = %d, pin value SDA = %d"%(key, sda_in, value['sda'], (((ord(boundary[value['sda'] >> 3]) >> (7 -(value['sda'] & 7))) &1)) ))
print ("%d: scl = %d, bit number SCL = %d, pin value SCL = %d"%(key, scl_in, value['scl'], (((ord(boundary[value['scl'] >> 3]) >> (7 -(value['scl'] & 7))) &1)) ))
boards = [{'model':'10347', 'scl': 241,'sda': 199}, #// E4, C1
{'model':'10359', 'scl': 280,'sda': 296}] #// H6, J5
bscan_path=('/dev/sfpgabscan%d'%(chn))
self. program_status_sensor_io(num_sensor = chn, mode = 1, seq_num = 0)
status = self.get_status_sensor_io(num_sensor=chn)
senspgmin = (status >> 24) & 1
if not senspgmin:
print ("Some sensor board is connected to port # %d, not FPGA"%(chn))
return "sensor"
test = [1]*len(boards)
#Stop hardware i2c controller
self.set_sensor_i2c_command(num_sensor = chn, run_cmd = False)
#Set SCL=0, SDA=0 and read values:
self.set_sensor_i2c_command(num_sensor = chn, sda = 0, scl = 0)
if verbose > 0:
print_i2c(chn = chn)
boundary = self.readbscan(bscan_path)
for key, value in enumerate(boards):
test[key] &= ((((ord(boundary[value['sda'] >> 3]) >> (7 -(value['sda'] & 7))) &1) == 0) and
(((ord(boundary[value['scl'] >> 3]) >> (7 -(value['scl'] & 7))) &1) == 0))
if verbose >0:
print_bv(chn=chn, boundary = boundary, value = value, key=key)
#Set SCL=1, SDA=0 and read values:
self.set_sensor_i2c_command(num_sensor = chn, sda = 0, scl = 1)
boundary = self.readbscan(bscan_path)
for key, value in enumerate(boards):
test[key] &= ((((ord(boundary[value['sda'] >> 3]) >> (7 -(value['sda'] & 7))) &1) == 0) and
(((ord(boundary[value['scl'] >> 3]) >> (7 -(value['scl'] & 7))) &1) == 1))
if verbose >0:
print_bv(chn=chn, boundary = boundary, value = value, key=key)
#Set SCL=0, SDA=1 and read values:
self.set_sensor_i2c_command(num_sensor = chn, sda = 1, scl = 0)
boundary = self.readbscan(bscan_path)
for key, value in enumerate(boards):
test[key] &= ((((ord(boundary[value['sda'] >> 3]) >> (7 -(value['sda'] & 7))) &1) == 1) and
(((ord(boundary[value['scl'] >> 3]) >> (7 -(value['scl'] & 7))) &1) == 0))
if verbose >0:
print_bv(chn=chn, boundary = boundary, value = value, key=key)
#Set SCL=1, SDA=1 and read values:
self.set_sensor_i2c_command(num_sensor = chn, sda = 1, scl = 1)
boundary = self.readbscan(bscan_path)
for key, value in enumerate(boards):
test[key] &= ((((ord(boundary[value['sda'] >> 3]) >> (7 -(value['sda'] & 7))) &1) == 1) and
(((ord(boundary[value['scl'] >> 3]) >> (7 -(value['scl'] & 7))) &1) == 1))
if verbose >0:
print_bv(chn=chn, boundary = boundary, value = value, key=key)
for key, value in enumerate(boards):
if test[key]:
if verbose >0:
print ("Detected FPGA-based board :%s"%(value['model']))
return value['model']
return ""
"""
def set_sensor_i2c_command (self,
num_sensor,
rst_cmd = False,
run_cmd = None,
active_sda = None,
early_release_0 = None,
advance_FIFO = None,
sda = None,
scl = None,
verbose = 1):
@param num_sensor - sensor port number (0..3)
@param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
@param run_cmd - True - run i2c, False - stop i2c (needed before software i2c), None - no change
@param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible
@param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup)
@param advance_FIFO - advance i2c read FIFO
@param sda - control SDA line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param scl - control SCL line (stopped mode only): I<nput>, L<ow> or 0, High or 1
@param verbose - verbose level
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
def program_status_sensor_i2c( self,
num_sensor,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
def print_status_sensor_i2c (self,
num_sensor="All"):
Print sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
print ("\n ==== Sensor %d"%(num_sensor))
self.print_status_sensor_i2c (num_sensor = num_sensor)
return
except:
pass
status= self.get_status_sensor_i2c(num_sensor)
print ("print_status_sensor_i2c(%d):"%(num_sensor))
print (" reset_on = %d"%((status>> 7) & 1))
print (" req_clr = %d"%((status>> 6) & 1))
print (" alive_fs = %d"%((status>> 5) & 1))
print (" busy = %d"%((status>> 4) & 1))
print (" frame_num = %d"%((status>> 0) & 0xf))
print (" sda_in = %d"%((status>>25) & 1))
print (" scl_in = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
set_sensor_mode 0 0 0 1 0
set_sensor_mode 1 0 0 1 0
set_sensor_mode 2 0 0 1 0
set_sensor_mode 3 0 0 1 0
program_status_sensor_io all 1 0
print_status_sensor_io all
python
import struct
import time
def readbscan(filename):
ffs=struct.pack("B",0xff)*97
with open(filename,'r+') as jtag:
#time.sleep(5)
jtag.write(ffs)
#time.sleep(5)
jtag.seek (0,0)
#time.sleep(5)
boundary= jtag.read(97)
#time.sleep(5)
return boundary
b = readbscan('/dev/sfpgabscan1')
$boards=array (
'0' => array ('model' => '10347', 'scl' =>241,'sda' => 199), // E4, C1
'1' => array ('model' => '10359', 'scl' =>280,'sda' => 296) // H6, J5
);
#cd /usr/local/verilog/; test_mcntrl.py -x @hargs
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "PAR12"
measure_all "*DI"
program_status_sensor_io all 1 0
print_status_sensor_io all
setSensorClock
checkSclSda 1
cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1
#jtag_set_pgm_mode 0 1
#jtag_set_pgm_mode 1 1
#jtag_set_pgm_mode 2 1
#jtag_set_pgm_mode 3 1
#set_sensor_mode 0 0 0 1 0
#set_sensor_mode 1 0 0 1 0
#set_sensor_mode 2 0 0 1 0
#set_sensor_mode 3 0 0 1 0
set_sensor_io_ctl 1 0 #turn mrst off to enable clocked signal (and to read done!) TODO: Add to the driver
program_status_sensor_io all 1 0
print_status_sensor_io 1 # all
set_sensor_io_ctl (self,
num_sensor,
mrst = None,
arst = None,
aro = None,
mmcm_rst = None,
clk_sel = None,
set_delays = False,
quadrants = None):
set_sensor_io_jtag 1 None None None None 0
program_status_sensor_io all 1 0
print_status_sensor_io 1
get_status_sensor_io 1
x393 +0.001s--> set_sensor_io_jtag 1 None None None None 0
x393 +0.001s--> program_status_sensor_io all 1 0
x393 +0.002s--> print_status_sensor_io 1 # all
print_status_sensor_io(1):
irst = 0
async_prst_with_sens_mrst = 0
imrst = 1
rst_mmcm = 0
pxd_out_pre[1] = 0
vact_alive = 0
hact_ext_alive = 0
hact_run = 0
locked_pxd_mmcm = 1
clkin_pxd_stopped_mmcm = 0
clkfb_pxd_stopped_mmcm = 0
xfpgadone = 1
ps_rdy = 1
ps_out = 0
xfpgatdo = 0
senspgmin = 1
seq = 0
x393 +0.001s--> set_sensor_io_jtag 1 None None None None 1
x393 +0.001s--> program_status_sensor_io all 1 0
x393 +0.002s--> print_status_sensor_io 1 # all
print_status_sensor_io(1):
irst = 0
async_prst_with_sens_mrst = 0
imrst = 1
rst_mmcm = 0
pxd_out_pre[1] = 1
vact_alive = 0
hact_ext_alive = 0
hact_run = 0
locked_pxd_mmcm = 1
clkin_pxd_stopped_mmcm = 0
clkfb_pxd_stopped_mmcm = 0
xfpgadone = 1
ps_rdy = 1
ps_out = 0
xfpgatdo = 1
senspgmin = 1
seq = 0
#setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS", quiet = 0)
>>> b = readbscan('/dev/sfpgabscan0')
>>> b
b = '\x00\x00\x00\x00\x00\x00\x00\x00\x08\x00$\x82\x12I\t\x00\x80\x02\x00@\x00\x04\x00\x00@\x00\x00\x00\x00\x00@\x00\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00 \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
b = '\xff\xff\xff\xff\xff\xff\xff\xff\xf7\xff\xdb}\xed\xb6\xf6\xff\x7f\xfd\xff\xbf\xff\xfb\xff\xff\xbf\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfb\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xdf\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xf0'
b = '\xff\xff\xff\xff\xff\xff\xff\xff\xf7\xff\xdb}\xed\xb6\xf6\xff\x7f\xfd\xff\xbf\xff\xfb\xff\xff\xbf\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfb\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xdf\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xf0'
a='ffffffffff7fffffffffffffffffffffffffffffffffffffbfffffffffffffffffffff7fff7ffffffbffffffffffffffffffffffffffffffffffffffffdffffffffffffffffffffff6dfffffffffffffffedf7fdbfedff7ffff6fffeffffffbff0'
al = []
for i in range(len(a)/2):
al.append(int('0x'+a[2*i:2*i+2],0))
bl = []
for i in b:
bl.append(ord(i))
for i,x in enumerate(zip(al,bl)):
print ("%02x %02x %02x"%(i,x[0],x[1]))
fwrite returned 97<br/>
Boundary:
ffffffffff7fffffffffffffffffffffffffffffffffffffbfffffffffffffffffffffffff7ffffffbffffffffffffffffffffffffffffffffffffffffdffffffffffffffffffffff6dfffffffffffffffedf7fdbfedff7ffff6fffeffffffbff0
fwrite returned 97<br/>
Boundary:
ffffffffff7fffffffffffffffffffffffffffffffffffffbfffffffffffffffffffff7ffffffffffbffffffffffffffffffffffffffffffffffffffffdffffffffffffffffffffff6dfffffffffffffffedf7fdbfedff7ffff6fffeffffffbff0
fwrite returned 97<br/>
Boundary:
ffffffffff7fffffffffffffffffffffffffffffffffffffbffffffffffffffffffffffffffffffffbffffffffffffffffffffffffffffffffffffffffdffffffffffffffffffffff6dfffffffffffffffedf7fdbfedff7ffff6fffeffffffbff0
>>> b1 = readbscan('/dev/sfpgabscan0')
>>> b1
'\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xf0'
'\x00\x00\x00\x00\x00\x00\x00\x00\x08\x00$\x82\x12I\t\x00\x80\x02\x00@\x00\x04\x00\x00@\x00\x00\x00\x00\x00@\x00\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00 \x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
cd /sys/kernel/debug/dynamic_debug
root@elphel393:/sys/kernel/debug/dynamic_debug# cat control | grep fpga
drivers/elphel/fpgajtag353.c:655 [fpgajtag]fpga_jtag_lseek =_ "fpga_jtag_lseek, fsize= 0x%x\012"
drivers/elphel/fpgajtag353.c:679 [fpgajtag]fpga_jtag_lseek =_ "fpga_jtag_lseek, file->f_pos= 0x%x\012"
drivers/elphel/fpgajtag353.c:1405 [fpgajtag]fpga_jtag_init =_ "elphel test %s: MAJOR %d"
drivers/elphel/fpgajtag353.c:751 [fpgajtag]wait_sensio_status =_ "seq_num = %d received after %d wait cycles"
drivers/elphel/fpgajtag353.c:764 [fpgajtag]set_pgm_mode =_ "set_pgm_mode (%d,%d)\012"
drivers/elphel/fpgajtag353.c:789 [fpgajtag]set_pgm =_ "set_pgm (%d,%d)\012"
drivers/elphel/fpgajtag353.c:851 [fpgajtag]jtag_send =_ "jtag_send(0x%x, 0x%x, 0x%x, 0x%x)\015\012"
drivers/elphel/fpgajtag353.c:950 [fpgajtag]jtag_write_bits =_ "jtag_write_bits(0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\015\012"
drivers/elphel/fpgajtag353.c:1096 [fpgajtag]JTAG_configure =_ "JTAG_configure: chn=%x, wp=0x%x, rp=0x%x, len=0x%x\015\012"
drivers/elphel/fpgajtag353.c:1211 [fpgajtag]JTAG_openChannel =_ "JTAG_openChannel (%d)\012"
drivers/elphel/fpgajtag353.c:367 [fpgajtag]fpga_jtag_open =_ "fpga_jtag_open: minor=%x, channel=%x, buf=%p\015\012"
drivers/elphel/fpgajtag353.c:440 [fpgajtag]fpga_jtag_open =_ "fpga_jtag_open: chn=%x, JTAG_channels[chn].sizew=%x, JTAG_channels[chn].sizer=%x\015\012"
drivers/elphel/fpgajtag353.c:441 [fpgajtag]fpga_jtag_open =_ "fpga_jtag_open: chn=%x, JTAG_channels[chn].bitsw=%x, JTAG_channels[chn].bitsr=%x\015\012"
drivers/elphel/fpgajtag353.c:446 [fpgajtag]fpga_jtag_open =_ "fpga_jtag_open: inode->i_size=%x, chn=%x\015\012"
drivers/elphel/fpgajtag353.c:1231 [fpgajtag]JTAG_resetChannel =_ "JTAG_resetChannel (%d)\012"
drivers/elphel/fpgajtag353.c:1342 [fpgajtag]JTAG_CAPTURE =_ "\012"
drivers/elphel/fpgajtag353.c:1347 [fpgajtag]JTAG_CAPTURE =_ "\012"
drivers/elphel/fpgajtag353.c:1344 [fpgajtag]JTAG_CAPTURE =_ "%3x "
drivers/elphel/fpgajtag353.c:1345 [fpgajtag]JTAG_CAPTURE =_ "\012"
drivers/elphel/fpgajtag353.c:456 [fpgajtag]fpga_jtag_release =_ "fpga_jtag_release: p=%x,chn=%x, wp=0x%x, rp=0x%x\015\012"
drivers/elphel/fpgajtag353.c:497 [fpgajtag]fpga_jtag_release =_ "fpga_jtag_release: done\015\012"
drivers/elphel/fpgajtag353.c:509 [fpgajtag]fpga_jtag_write =_ "fpga_jtag_write: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, wp=%lx,size=0x%x\015\012"
drivers/elphel/fpgajtag353.c:562 [fpgajtag]fpga_jtag_write =_ "fpga_jtag_write end: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, wp=%lx,size=0x%x\015\012"
drivers/elphel/fpgajtag353.c:574 [fpgajtag]fpga_jtag_read =_ "fpga_jtag_read: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\015\012"
drivers/elphel/fpgajtag353.c:601 [fpgajtag]fpga_jtag_read =_ "fpga_jtag_read_01: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\015\012"
drivers/elphel/fpgajtag353.c:624 [fpgajtag]fpga_jtag_read =_ "fpga_jtag_read_01: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x\015\012"
drivers/elphel/fpgajtag353.c:635 [fpgajtag]fpga_jtag_read =_ "fpga_jtag_read_end: p=%x,chn=%x, buf address=%lx count=%lx *offs=%lx, rp=%lx,size=0x%x, mode=%x\015\012"
drivers/elphel/fpgajtag353.c:1416 [fpgajtag]fpga_jtag_exit =_ "unregistering driver"
root@elphel393:/sys/kernel/debug/dynamic_debug# echo 'file drivers/elphel/fpgajtag353.c +p' > control
afpgaconfjtag jtagraw memory_bandwidth mtd4ro ram2 stderr tty18 tty30 tty43 tty56 ttyS1
block kmem mmcblk0 mtdblock0 ram3 stdin tty19 tty31 tty44 tty57 ttyS2
char kmsg mmcblk0p1 mtdblock1 random stdout tty2 tty32 tty45 tty58 ttyS3
console log mmcblk0p2 mtdblock2 rtc0 tty tty20 tty33 tty46 tty59 ubi_ctrl
cpu_dma_latency loop-control mtab mtdblock3 sfpgabscan0 tty0 tty21 tty34 tty47 tty6 urandom
disk loop0 mtd0 mtdblock4 sfpgabscan1 tty1 tty22 tty35 tty48 tty60 vcs
fd loop1 mtd0ro network_latency sfpgabscan2 tty10 tty23 tty36 tty49 tty61 vcs1
fpgaconfjtag loop2 mtd1 network_throughput sfpgabscan3 tty11 tty24 tty37 tty5 tty62 vcsa
fpgaresetjtag loop3 mtd1ro null sfpgaconfjtag tty12 tty25 tty38 tty50 tty63 vcsa1
full loop4 mtd2 psaux sfpgaconfjtag0 tty13 tty26 tty39 tty51 tty7 watchdog
i2c-0 loop5 mtd2ro ptmx sfpgaconfjtag1 tty14 tty27 tty4 tty52 tty8 watchdog0
iio:device0 loop6 mtd3 pts sfpgaconfjtag2 tty15 tty28 tty40 tty53 tty9 xdevcfg
initctl loop7 mtd3ro ram0 sfpgaconfjtag3 tty16 tty29 tty41 tty54 ttyPS0 zero
input mem mtd4 ram1 shm tty17 tty3 tty42 tty55 ttyS0
fseek ($jtag,0);
$boundary= fread($jtag, 97);
fclose($jtag);
return $boundary;
packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData
"""
def set_sensor_io_width ( def set_sensor_io_width (
self, self,
num_sensor, num_sensor,
......
sensor/sens_parallel12.v
View file @ d3767c2c
...@@ -190,7 +190,9 @@ module sens_parallel12 #( ...@@ -190,7 +190,9 @@ module sens_parallel12 #(
wire [17:0] status; // wire [17:0] status;
// wire [18:0] status;
wire [22:0] status;
wire cmd_we; wire cmd_we;
wire [2:0] cmd_a; wire [2:0] cmd_a;
...@@ -228,7 +230,12 @@ module sens_parallel12 #( ...@@ -228,7 +230,12 @@ module sens_parallel12 #(
assign set_pxd_delay = set_idelay[2:0]; assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3]; assign set_other_delay = set_idelay[3];
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, // assign status = {pxd_out_pre[1],vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
// clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
// ps_rdy, ps_out, xfpgatdo, senspgmin};
assign status = {irst, async_prst_with_sens_mrst, imrst, rst_mmcm, pxd_out_pre[1],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone, clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin}; ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r; assign hact_out = hact_r;
...@@ -414,14 +421,16 @@ module sens_parallel12 #( ...@@ -414,14 +421,16 @@ module sens_parallel12 #(
status_generate #( status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG), .STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS) // .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH+1) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i ( ) status_generate_sens_io_i (
.rst (1'b0), // rst), // input .rst (1'b0), // rst), // input
.clk (mclk), // input .clk (mclk), // input
.srst (mclk_rst), // input .srst (mclk_rst), // input
.we (set_status_r), // input .we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0] .wd (data_r[7:0]), // input[7:0]
.status ({status_alive,status}), // input[25:0] // .status ({status_alive,status}), // input[25:0]
.status ({status}), // input[25:0]
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
...@@ -456,8 +465,27 @@ module sens_parallel12 #( ...@@ -456,8 +465,27 @@ module sens_parallel12 #(
.ld_idelay (ld_idelay), // input .ld_idelay (ld_idelay), // input
.quadrant (quadrants[1:0]) // input[1:0] .quadrant (quadrants[1:0]) // input[1:0]
); );
// debugging implementation // debugging implementation
//assign xfpgatdo = pxd_out[1]; //assign xfpgatdo = pxd_out[1];
/* Instance template for module iobuf */
//`define DEBUF_JTAG 1
`ifdef DEBUF_JTAG
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) pxd_pxd1_i (
.O (pxd_out_pre[1]), // output
.IO (pxd[1]), // inout
.I (1'b0), // input
.T (1'b1) // input
);
assign xfpgatdo = pxd_out_pre[1];
`else
wire n_xfpgatdo;
assign xfpgatdo = !n_xfpgatdo;
pxd_single #( pxd_single #(
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
...@@ -471,7 +499,7 @@ module sens_parallel12 #( ...@@ -471,7 +499,7 @@ module sens_parallel12 #(
.pxd (pxd[1]), // inout .pxd (pxd[1]), // inout
.pxd_out (1'b0), // input .pxd_out (1'b0), // input
.pxd_en (1'b0), // input .pxd_en (1'b0), // input
.pxd_async (xfpgatdo), // output .pxd_async (n_xfpgatdo), // output
.pxd_in (pxd_out_pre[1]), // output .pxd_in (pxd_out_pre[1]), // output
.ipclk (ipclk), // input .ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input .ipclk2x (ipclk2x), // input
...@@ -483,6 +511,10 @@ module sens_parallel12 #( ...@@ -483,6 +511,10 @@ module sens_parallel12 #(
.ld_idelay (ld_idelay), // input .ld_idelay (ld_idelay), // input
.quadrant (quadrants[1:0]) // input[1:0] .quadrant (quadrants[1:0]) // input[1:0]
); );
`endif
// bits 2..11 are just PXD inputs, instance them all together // bits 2..11 are just PXD inputs, instance them all together
generate generate
genvar i; genvar i;
......
sensor/sensor_channel.v
View file @ d3767c2c
...@@ -81,6 +81,8 @@ module sensor_channel#( ...@@ -81,6 +81,8 @@ module sensor_channel#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
...@@ -467,7 +469,10 @@ module sensor_channel#( ...@@ -467,7 +469,10 @@ module sensor_channel#(
`ifdef DEBUG_RING `ifdef DEBUG_RING
// reg vact_to_fifo_r; `ifdef HISPI
`else
reg vact_to_fifo_r;
`endif
reg hact_to_fifo_r; reg hact_to_fifo_r;
reg [15:0] debug_line_cntr; reg [15:0] debug_line_cntr;
reg [15:0] debug_lines; reg [15:0] debug_lines;
...@@ -611,6 +616,8 @@ module sensor_channel#( ...@@ -611,6 +616,8 @@ module sensor_channel#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET), .SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN), .SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS), .SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD), .SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE), .SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0), .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
......
sensor/sensor_i2c.v
View file @ d3767c2c
...@@ -48,7 +48,8 @@ module sensor_i2c#( ...@@ -48,7 +48,8 @@ module sensor_i2c#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
...@@ -112,16 +113,7 @@ module sensor_i2c#( ...@@ -112,16 +113,7 @@ module sensor_i2c#(
wire wen; wire wen;
wire [31:0] di; wire [31:0] di;
wire [3:0] wa; wire [3:0] wa;
// wire busy; // busy (do not use software i2i)
// reg [4:0] wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
// reg [3:0] wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
// reg [3:0] wad;
reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
// reg [15:0] di_1;
// reg [15:0] di_2;
// reg [15:0] di_3;
reg [3:0] wpage0; // FIFO page where ASAP writes go reg [3:0] wpage0; // FIFO page where ASAP writes go
reg [3:0] wpage_prev; // unused page, currently being cleared reg [3:0] wpage_prev; // unused page, currently being cleared
reg [3:0] page_r; // FIFO page where current i2c commands are taken from reg [3:0] page_r; // FIFO page where current i2c commands are taken from
...@@ -129,21 +121,15 @@ module sensor_i2c#( ...@@ -129,21 +121,15 @@ module sensor_i2c#(
reg [3:0] wpage_wr; // FIFO page where current write goes (reading from write address) reg [3:0] wpage_wr; // FIFO page where current write goes (reading from write address)
reg [1:0] wpage0_inc; // increment wpage0 (after frame sync or during reset) reg [1:0] wpage0_inc; // increment wpage0 (after frame sync or during reset)
reg reset_cmd; reg reset_cmd;
// reg dly_cmd;
// reg bytes_cmd;
reg run_cmd; reg run_cmd;
reg twe; reg twe;
reg active_cmd; reg active_cmd;
reg active_sda; reg active_sda;
reg early_release_0; reg early_release_0;
reg reset_on; // reset FIFO in progress reg reset_on; // reset FIFO in progress
// reg [1:0] i2c_bytes;
// reg [7:0] i2c_dly;
reg i2c_enrun; // enable i2c reg i2c_enrun; // enable i2c
reg we_fifo_wp; // enable writing to fifo write pointer memory reg we_fifo_wp; // enable writing to fifo write pointer memory
reg req_clr; // request for clearing fifo_wp (delay frame sync if previous is not yet sent out), also used for clearing all reg req_clr; // request for clearing fifo_wp (delay frame sync if previous is not yet sent out), also used for clearing all
// wire is_ctl= (wad[3:0]==4'hf);
// wire is_abs= (wad[3]==0);
wire pre_wpage0_inc; // ready to increment wire pre_wpage0_inc; // ready to increment
wire [3:0] frame_num=wpage0[3:0]; wire [3:0] frame_num=wpage0[3:0];
...@@ -165,7 +151,6 @@ module sensor_i2c#( ...@@ -165,7 +151,6 @@ module sensor_i2c#(
reg i2c_start; // initiate i2c register write sequence reg i2c_start; // initiate i2c register write sequence
wire i2c_run; // i2c sequence is in progress (early end) wire i2c_run; // i2c sequence is in progress (early end)
reg i2c_run_d; // i2c sequence is in progress (early end) reg i2c_run_d; // i2c sequence is in progress (early end)
// wire i2c_busy; // i2c sequence is in progress (until bus is free and stop finished)
wire [1:0] byte_number; // byte number to send next (3-2-1-0) wire [1:0] byte_number; // byte number to send next (3-2-1-0)
wire [1:0] seq_mem_re; wire [1:0] seq_mem_re;
wire [7:0] i2c_data; wire [7:0] i2c_data;
...@@ -182,9 +167,17 @@ module sensor_i2c#( ...@@ -182,9 +167,17 @@ module sensor_i2c#(
wire set_status_w; wire set_status_w;
reg [1:0] wen_r; reg [1:0] wen_r;
// reg [1:0] wen_fifo;
reg wen_fifo; // [1] was not used - we_fifo_wp was used instead reg wen_fifo; // [1] was not used - we_fifo_wp was used instead
reg scl_en_soft; // software i2c control signals (used when i2c controller is disabled)
reg scl_soft;
reg sda_en_soft;
reg sda_soft;
wire sda_hard;
wire sda_en_hard;
wire scl_hard;
assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0 assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
...@@ -196,7 +189,13 @@ module sensor_i2c#( ...@@ -196,7 +189,13 @@ module sensor_i2c#(
assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w? assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w?
assign scl_en = i2c_enrun; // assign scl_en = i2c_enrun;
assign scl_out = i2c_enrun? scl_hard: scl_soft ;
assign scl_en = i2c_enrun? 1'b1: scl_en_soft ;
assign sda_out = i2c_enrun? sda_hard: sda_soft ;
assign sda_en = i2c_enrun? sda_en_hard: sda_en_soft ;
reg alive_fs; reg alive_fs;
...@@ -287,6 +286,16 @@ module sensor_i2c#( ...@@ -287,6 +286,16 @@ module sensor_i2c#(
if (reset_cmd || mrst) i2c_enrun <= 1'b0; if (reset_cmd || mrst) i2c_enrun <= 1'b0;
else if (run_cmd) i2c_enrun <= di_r[SENSI2C_CMD_RUN - 1 -: SENSI2C_CMD_RUN_PBITS]; // [12]; else if (run_cmd) i2c_enrun <= di_r[SENSI2C_CMD_RUN - 1 -: SENSI2C_CMD_RUN_PBITS]; // [12];
if (i2c_enrun || mrst) scl_en_soft <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_en_soft <= di[SENSI2C_CMD_SOFT_SCL +:2] != 3;
if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_soft <= di[SENSI2C_CMD_SOFT_SCL + 1];
if (i2c_enrun || mrst) sda_en_soft <= 0;
else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_en_soft <= di[SENSI2C_CMD_SOFT_SDA +:2] != 3;
if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_soft <= di[SENSI2C_CMD_SOFT_SDA + 1];
if (active_cmd) begin if (active_cmd) begin
early_release_0 <= di_r[SENSI2C_CMD_ACIVE_EARLY0]; early_release_0 <= di_r[SENSI2C_CMD_ACIVE_EARLY0];
active_sda <= di_r[SENSI2C_CMD_ACIVE_SDA]; active_sda <= di_r[SENSI2C_CMD_ACIVE_SDA];
...@@ -377,9 +386,9 @@ module sensor_i2c#( ...@@ -377,9 +386,9 @@ module sensor_i2c#(
.td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0] .td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0]
.twe (twe), // input .twe (twe), // input
.sda_in (sda_in), // input .sda_in (sda_in), // input
.sda (sda_out), // output .sda (sda_hard), // output
.sda_en (sda_en), // output .sda_en (sda_en_hard), // output
.scl (scl_out), // output .scl (scl_hard), // output
.i2c_run (i2c_run), // output reg .i2c_run (i2c_run), // output reg
.i2c_busy (), //i2c_busy), // output reg .i2c_busy (), //i2c_busy), // output reg
.seq_mem_ra (byte_number), // output[1:0] reg .seq_mem_ra (byte_number), // output[1:0] reg
......
sensor/sensor_i2c_io.v
View file @ d3767c2c
...@@ -48,7 +48,8 @@ module sensor_i2c_io#( ...@@ -48,7 +48,8 @@ module sensor_i2c_io#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
...@@ -108,6 +109,8 @@ module sensor_i2c_io#( ...@@ -108,6 +109,8 @@ module sensor_i2c_io#(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET), .SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN), .SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS), .SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD), .SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE), .SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0), .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
......
sensor/sensors393.v
View file @ d3767c2c
...@@ -72,6 +72,8 @@ module sensors393 #( ...@@ -72,6 +72,8 @@ module sensors393 #(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
...@@ -479,6 +481,8 @@ module sensors393 #( ...@@ -479,6 +481,8 @@ module sensors393 #(
.SENSI2C_CMD_RESET (SENSI2C_CMD_RESET), .SENSI2C_CMD_RESET (SENSI2C_CMD_RESET),
.SENSI2C_CMD_RUN (SENSI2C_CMD_RUN), .SENSI2C_CMD_RUN (SENSI2C_CMD_RUN),
.SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS), .SENSI2C_CMD_RUN_PBITS (SENSI2C_CMD_RUN_PBITS),
.SENSI2C_CMD_SOFT_SDA (SENSI2C_CMD_SOFT_SDA),
.SENSI2C_CMD_SOFT_SCL (SENSI2C_CMD_SOFT_SCL),
.SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD), .SENSI2C_CMD_FIFO_RD (SENSI2C_CMD_FIFO_RD),
.SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE), .SENSI2C_CMD_ACIVE (SENSI2C_CMD_ACIVE),
.SENSI2C_CMD_ACIVE_EARLY0 (SENSI2C_CMD_ACIVE_EARLY0), .SENSI2C_CMD_ACIVE_EARLY0 (SENSI2C_CMD_ACIVE_EARLY0),
......
system_defines.vh
View file @ d3767c2c
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI // `define HISPI
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
......
x393.bit
View file @ d3767c2c
No preview for this file type
x393_timing.tcl
View file @ d3767c2c
...@@ -55,25 +55,11 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ] ...@@ -55,25 +55,11 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ] create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ] create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre] create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
if ($HISPI) { create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ] create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ] create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ] create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
} else {
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
}
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}] create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated #Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
...@@ -84,11 +70,7 @@ if ($HISPI) { ...@@ -84,11 +70,7 @@ if ($HISPI) {
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
} else { } else {
create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks #Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ] create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ] create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
...@@ -102,16 +84,16 @@ if ($HISPI) { ...@@ -102,16 +84,16 @@ if ($HISPI) {
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ] create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ] create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0} set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1} set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2} set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3} set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
} }
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary. # do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk} set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk} set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
......
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