generated boson version 0x0393401b

fpga_version.vh

@@ -35,7 +35,8 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-    parameter FPGA_VERSION = 32'h03931017;   // restoring both saxigp clocks to 150MHz (from 100 MHz)
+   parameter FPGA_VERSION = 32'h0393401b;   // same as 0393401a with updated histograms saxigp0 (not used, just testing it did not break)
+//    parameter FPGA_VERSION = 32'h03931017;   // restoring both saxigp clocks to 150MHz (from 100 MHz) - OK, pushed, xclk slightly timing not matched
 //    parameter FPGA_VERSION = 32'h03931016;   // debugging histograms - MOD_SAXI on, restore actual histogram data (works, pushed to git)
 //    parameter FPGA_VERSION = 32'h03931015;   // debugging histograms - MOD_SAXI on, fixed some bugs related to inactive cycle with page_ra == 8'hff - works?
 //    parameter FPGA_VERSION = 32'h03931014;   // debugging histograms - MOD_SAXI on, updates sim_saxi to match hardware (wlast disables wready, smaller fifo)

system_defines.vh

@@ -65,8 +65,8 @@
   `define DISPLAY_COMPRESSED_DATA
 // if specific sesnor is not defined, parallel sensor interface is used for all channels
 /*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
-// `define BO-SON 1
-// `define BO-SON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON"
+ `define BOSON 1
+ `define BOSON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON"
 
 // `define LWIR
 // `define HISPI