renamed signals

dct_tests_03.dtt_iv_8x8_i.out_we

dct_tests_03.dtt_iv_8x8_i.sub16

dct_tests_03.dtt_iv_8x8_i.inc16

dct_tests_03.dtt_iv_8x8_i.start64

dct_tests_03.dtt_iv_8x8_i.start_out

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@22

    wire                             out_we;

    wire                             sub16;

    wire                             inc16;

    wire                             start64;

    wire                             start_out;

    reg                 [ODEPTH-5:0] out_ram_cntr;

    reg                 [ODEPTH-5:0] out_ram_wah;

        if (out_we) out_ram[out_ram_wa] <= out_wd;

        if      (RST)         out_ram_ren <= 1'b0;

        else if (start64)     out_ram_ren <= 1'b1;

        else if (start_out)   out_ram_ren <= 1'b1;

        else if (&out_ram_ra) out_ram_ren <= 1'b0;

        out_ram_regen <= out_ram_ren;

        .clk  (CLK),           // input

        .rst  (RST),           // input

        .dly  (4'h1),          // input[3:0] 

        .din  (start64),       // input[0:0] 

        .din  (start_out),       // input[0:0] 

        .dout (out_pre_first)  // output[0:0] 

    );

        .out_we         (out_we),           // output reg 

        .sub16          (sub16),            // output reg 

        .inc16          (inc16),            // output reg 

        .start64        (start64)           // output reg 

        .start_out      (start_out)         // output reg 

    );

    output reg                       out_we,        //!< output data valid (write to external buffer 

    output reg                       sub16,         //!< Subtract 16 from the full output address when true

    output reg                       inc16,         //!< increment full output address by 16

    output reg                       start64);      //!< may start output readout, 1 entry per clock, vertically

    output reg                       start_out);    //!< may start output readout, 1 entry per clock, vertically

// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock

// 2. of the horizontal DCTs

    reg                              pre_dstv;  // 1 cycles before vertical output data is valid, 0 dct, 1 - dst

    reg                              dstv;      // when vertical output data is valid, 0 dct, 1 - dst

    wire                             start64_w = out_cntr[6:0] == 'h0d;

    wire                             start_out_w = out_cntr[6:0] == 'h0d;

    assign pre_last_in = pre_last_in_r;

        sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run;

        inc16 <= out_cntr[3:0] == 'he;

        out_we <= dctv_out_we[1];

        start64 <= start64_w;         

        start_out <= start_out_w;         

    end

    always @ (posedge clk) begin

    wire                             out_we;

    wire                             sub16;

    wire                             inc16;

    wire                             start64;

    wire                             start_out;

    reg                 [ODEPTH-5:0] out_ram_cntr;

    reg                 [ODEPTH-5:0] out_ram_wah;

        if (out_we) out_ram[out_ram_wa] <= out_wd;

        if      (rst)         out_ram_ren <= 1'b0;

        else if (start64)     out_ram_ren <= 1'b1;

        else if (start_out)     out_ram_ren <= 1'b1;

        else if (&out_ram_ra) out_ram_ren <= 1'b0;

        out_ram_regen <= out_ram_ren;

        .clk  (clk),           // input

        .rst  (rst),           // input

        .dly  (4'h1),          // input[3:0] 

        .din  (start64),       // input[0:0] 

        .din  (start_out),       // input[0:0] 

        .dout (pre_first_out)  // output[0:0] 

    );

        .out_we         (out_we),           // output reg 

        .sub16          (sub16),            // output reg 

        .inc16          (inc16),            // output reg 

        .start64        (start64)           // output reg 

        .start_out      (start_out)           // output reg 

    );