troubleshooting lack of DONE during loading of the bitfile

cd3ccb58 · Andrey Filippov · 6176aa7b · cd3ccb58 · cd3ccb58 · cd3ccb58
Commit cd3ccb58 authored Jun 07, 2014 by Andrey Filippov
20 changed files
--- a/.project
+++ b/.project
@@ -5,6 +5,11 @@
 	<projects>
 	</projects>
 	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
 		<buildCommand>
 			<name>com.elphel.vdt.veditor.simulateBuilder</name>
 			<arguments>
@@ -41,6 +46,7 @@
 	</buildSpec>
 	<natures>
 		<nature>com.elphel.vdt.veditor.HdlNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
 	</natures>
 	<linkedResources>
 		<link>
@@ -56,77 +62,77 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140602115135083.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140606182054344.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140602115135083.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140602122428009.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140602115135083.log</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140606182315739.log</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140602122428009.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140606182315739.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-place.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140602122428009.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140606182315739.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-route.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140602122428009.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140606182315739.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/eddr3-synth.dcp</name>
 			<type>1</type>
-			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140602115135083.dcp</location>
+			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140606171026321.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>
--- a/.settings/com.elphel.vdt.VivadoBitstream.prefs
+++ b/.settings/com.elphel.vdt.VivadoBitstream.prefs
+VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
 VivadoBitstream_105_force=true
-com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->
+com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
 eclipse.preferences.version=1
--- a/.settings/com.elphel.vdt.VivadoSynthesis.prefs
+++ b/.settings/com.elphel.vdt.VivadoSynthesis.prefs
 VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
+VivadoSynthesis_115_flatten_hierarchy=none
 VivadoSynthesis_95_ShowInfo=false
-com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
+com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->
 eclipse.preferences.version=1
--- a/ddrc_control.v
+++ b/ddrc_control.v
@@ -52,8 +52,13 @@ module  ddrc_control #(
    parameter DLY_RST_REL =           'h02c,  // address to activate('h82d)/deactivate('h82c) delay calibration circuitry  
    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry
    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)
-    parameter EXTRA_REL_MASK =        'h3ff   // address mask for extra parameters
+    parameter EXTRA_REL_MASK =        'h3ff,  // address mask for extra parameters
+    parameter REFRESH_EN_REL =        'h030,  // address to enable('h31) and disable ('h30) DDR refresh
+    parameter REFRESH_EN_REL_MASK =   'h3fe,  // address mask to enable/disable DDR refresh
+    parameter REFRESH_PER_REL =       'h032,  // address to set refresh period in 32 x tCK
+    parameter REFRESH_PER_REL_MASK =  'h3ff,  // address mask set refresh period
+    parameter REFRESH_ADDR_REL =      'h033,  // address to set sequencer start address for DDR refresh
+    parameter REFRESH_ADDR_REL_MASK = 'h3ff   // address mask set refresh sequencer address
 )(
    input                         clk,
    input                         mclk,
@@ -69,6 +74,17 @@ module  ddrc_control #(
    output                 [10:0] run_addr, // Start address of the physical sequencer (MSB = 0 - "manual", 1 -"auto")
    output                 [ 3:0] run_chn,  // channel number to use for I/O buffers
    output                        run_seq,  // single mclk pulse to start sequencer
+// simple arbitration (should not start if higher priority, busy or run_seq)
+    input                         run_seq_rq_in, // higher priority request to run sequence
+    output                        run_seq_rq_gen,// this wants to run sequencer
+    input                         run_seq_busy,  // sequencer is busy or access granted to other master (should be on staring nearest cycle)
+    output                 [10:0] refresh_address,
+    output                 [ 7:0] refresh_period,
+    output                        refresh_set,
+    output                        refresh_en,                   
+//    output                        run_seq_granted, // this module got sequencer access granted
 //    input                        run_done; // output - will go through other channel - sequencer done (add busy?)
 // control: delays and mmcm setup    
    output                 [ 7:0] dly_data, // 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
@@ -138,16 +154,37 @@ module  ddrc_control #(
    localparam EXTRA_ADDR =         CONTROL_ADDR |      EXTRA_REL;        // address to set extra parameters (currently just inv_clk_div)
    localparam EXTRA_ADDR_MASK =    CONTROL_ADDR_MASK | EXTRA_REL_MASK;   // address mask for extra parameters
+    localparam REFRESH_EN_ADDR =      CONTROL_ADDR |      REFRESH_EN_REL;        // address to enable('h31) and disable ('h30) DDR refresh
+    localparam REFRESH_EN_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_EN_REL_MASK;   // address mask to enable/disable DDR refresh
+    localparam REFRESH_PER_ADDR =      CONTROL_ADDR |      REFRESH_PER_REL;        // address to set refresh period in 32 x tCK
+    localparam REFRESH_PER_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_PER_REL_MASK;   // address mask set refresh period
+    localparam REFRESH_ADDR_ADDR =      CONTROL_ADDR |      REFRESH_ADDR_REL;        // address to set sequencer start address for DDR refresh
+    localparam REFRESH_ADDR_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_ADDR_REL_MASK;   // address mask set refresh sequencer address
+    reg                 [10:0] refresh_address_r;
+    reg                 [ 7:0] refresh_period_r;
+    reg                        refresh_set_r, refresh_set_r0;                   
+    reg                        refresh_ld_addr;                   
+    reg                        refresh_en_r;                   
+    wire                       refresh_set_w; // just decoded                    
+    assign refresh_address = refresh_address_r;
+    assign refresh_period =  refresh_period_r;
+    assign refresh_set =     refresh_set_r;
+    assign refresh_en =      refresh_en_r;
    reg busy_r=0;
    reg selected=0;
    reg selected_busy=0;
-//(* keep = "true" *)
    wire fifo_half_empty; // just debugging with (* keep = "true" *)
    wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;
    wire                 [31:0] wdata_fifo_out;
 //    reg                         fifo_re; // wrong, need to have (fifo!=1) || !re 
    wire                        fifo_nempty;
-    wire                        fifo_re=fifo_nempty; // try simpler
+    wire                        fifo_re;
    reg  [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out_r;
    reg                  [31:0] wdata_fifo_out_r;
    reg                         dly_ld_r=0;
@@ -170,6 +207,20 @@ module  ddrc_control #(
    reg                  [15:0] dqs_tri_pattern_r;
    reg                  [ 3:0] wbuf_delay_r;
+    wire                        decoded_run_seq;
+    assign refresh_set_w= fifo_re && (((waddr_fifo_out ^ REFRESH_PER_ADDR) & REFRESH_PER_ADDR_MASK)==0);
+//    reg                         this_granted;
+//    assign run_seq_granted=this_granted;
+    assign decoded_run_seq= (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0) && !ddr_rst; // without ddr_rst 'bx
+    assign run_seq_rq_gen=decoded_run_seq  && fifo_nempty ; // 
+//    assign                      fifo_re=fifo_nempty; // try simpler
+// need a way to reset if run_seq_busy is forever busy? Will it work to just repeat the same command w/o busy to overrun fifo?
+// ddr_rst_r should reset seqencer?
+// watch higher priority and busy for run_seq command, always ready - for others
+    assign                      fifo_re= fifo_nempty  && (decoded_run_seq? (!run_seq_rq_in && !run_seq_busy && !run_seq_r): 1'b1);
    assign wbuf_delay= wbuf_delay_r;
    assign {
        dqs_tri_off_pattern[3:0],
@@ -236,7 +287,8 @@ module  ddrc_control #(
        if (rst) dly_set_r <= 1'b0;
        else     dly_set_r <= fifo_re && (((waddr_fifo_out ^ DLY_SET_ADDR) & DLY_SET_ADDR_MASK)==0);
        if (rst) run_seq_r <= 1'b0;
-        else     run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
+//        else     run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
+        else     run_seq_r <=  fifo_nempty  && decoded_run_seq && !run_seq_rq_in && !run_seq_busy && !run_seq_r;
        if (rst) {dqm_pattern_r,dqs_pattern_r} <= 16'h0055;
        else if (fifo_re && (((waddr_fifo_out ^ PATTERNS_ADDR) & PATTERNS_ADDR_MASK)==0))
@@ -279,6 +331,26 @@ module  ddrc_control #(
        if (rst) wbuf_delay_r <= WBUF_DLY_DFLT;
        else if (fifo_re && (((waddr_fifo_out ^ WBUF_DELAY_ADDR) & WBUF_DELAY_ADDR_MASK)==0))
                 wbuf_delay_r <= wdata_fifo_out[3:0];
+        if (rst) refresh_en_r <= 1'b0;
+        else if (fifo_re && (((waddr_fifo_out ^ REFRESH_EN_ADDR) & REFRESH_EN_ADDR_MASK)==0))
+                 refresh_en_r <= waddr_fifo_out[0];
+        if (rst) refresh_address_r <= 0;
+        else if (refresh_ld_addr) refresh_address_r <= wdata_fifo_out_r[10:0];
+        if (rst) refresh_period_r <= 0;
+        else if (refresh_set_r0) refresh_period_r <= wdata_fifo_out_r[7:0];
+        if (rst) refresh_set_r0 <= 0;
+        else     refresh_set_r0 <= refresh_set_w;
+        if (rst) refresh_set_r <= 0;
+        else     refresh_set_r <= refresh_set_r0;
+        if (rst) refresh_ld_addr <= 0;
+        else     refresh_ld_addr <= fifo_re && (((waddr_fifo_out ^ REFRESH_ADDR_ADDR) & REFRESH_ADDR_ADDR_MASK)==0);
    end
    always @ (posedge mclk) begin
        waddr_fifo_out_r <= waddr_fifo_out;

--- a/ddrc_status.v
+++ b/ddrc_status.v
@@ -41,13 +41,16 @@ module  ddrc_status
 // status/readback signals
 //    input                         run_done,      // sequencer done (add busy?)
    input                         run_busy,       // sequencer busy
    input                         locked,        // MMCM and PLL locked
+    input                         locked_mmcm,
+    input                         locked_pll,
+    input                         dly_ready,
+    input                         dci_ready,
    input                         ps_rdy,        // MMCM phase shift control ready
    input                  [ 7:0] ps_out         // MMCM phase shift value (in 1/56 of the Fvco period)
 );
    assign busy=0;
-    assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};
+    assign rdata={17'b0,dly_ready,dci_ready, locked_mmcm, locked_pll, run_busy,locked,ps_rdy,ps_out[7:0]};
 endmodule

--- a/ddrc_test01.v
+++ b/ddrc_test01.v
@@ -94,7 +94,13 @@ module  ddrc_test01 #(
    parameter DLY_RST_REL =           'h02a,  // address to activate('h82d)/deactivate('h82c) delay calibration circuitry  
    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry
    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)
-    parameter EXTRA_REL_MASK =        'h3ff   // address mask for extra parameters
+    parameter EXTRA_REL_MASK =        'h3ff,  // address mask for extra parameters
+    parameter REFRESH_EN_REL =        'h030,  // address to enable('h31) and disable ('h30) DDR refresh
+    parameter REFRESH_EN_REL_MASK =   'h3fe,  // address mask to enable/disable DDR refresh
+    parameter REFRESH_PER_REL =       'h032,  // address to set refresh period in 32 x tCK
+    parameter REFRESH_PER_REL_MASK =  'h3ff,  // address mask set refresh period
+    parameter REFRESH_ADDR_REL =      'h033,  // address to set sequencer start address for DDR refresh
+    parameter REFRESH_ADDR_REL_MASK = 'h3ff   // address mask set refresh sequencer address
 )(
    // DDR3 interface
    output                       SDRST, // DDR3 reset (active low)
@@ -114,7 +120,10 @@ module  ddrc_test01 #(
    inout                        NDQSL, // ~LDQS I/O pad
    output                       SDDMU, // UDM  I/O pad (actually only output)
    inout                        DQSU,  // UDQS I/O pad
-    inout                        NDQSU // ~UDQS I/O pad
+    inout                        NDQSU,
+    output                       DUMMY_TO_KEEP,  // to keep PS7 signals from "optimization"
+    input                        MEMCLK
+     // ~UDQS I/O pad
    // AXI write (ps -> pl)
 );
    localparam ADDRESS_NUMBER=15;
@@ -202,9 +211,18 @@ module  ddrc_test01 #(
   wire        mclk;
   wire        en_cmd0_wr;
-   wire [10:0] run_addr; // input[10:0] 
+   wire [10:0] axi_run_addr; 
-   wire [ 3:0] run_chn;  // input[3:0] 
+   wire [ 3:0] axi_run_chn;  
-   wire        run_seq;  // input
+   wire        axi_run_seq; 
+   wire [10:0] run_addr; // multiplexed - from refresh or axi 
+   wire [ 3:0] run_chn;   // multiplexed - from refresh or axi
+   wire        run_seq; 
+   wire        run_seq_rq_in; // higher priority request to run sequence
+   wire        run_seq_rq_gen;// SuppressThisWarning VEditor : unused this wants to run sequencer 
+//   wire        run_seq_busy;  // sequencer is busy or access granted to other master
 //   wire        run_done; // output
   wire        run_busy; // TODO: add to ddrc_sequencer 
   wire [ 7:0] dly_data; // input[7:0] 
@@ -213,6 +231,18 @@ module  ddrc_test01 #(
   wire        set; // input
   wire        locked; // output
+   wire        locked_mmcm;
+   wire        locked_pll;
+   wire        dly_ready;
+   wire        dci_ready;
+   wire        phy_locked_mmcm;
+   wire        phy_locked_pll;
+   wire        phy_dly_ready;
+   wire        phy_dci_ready;
+   wire [ 7:0] tmp_debug; 
   wire        ps_rdy; // output
   wire [ 7:0] ps_out; // output[7:0] 
@@ -254,6 +284,11 @@ module  ddrc_test01 #(
   wire        port0_rd_match;
   reg         port0_rd_match_r; // rd address matched in previous cycle
+   wire [7:0] refresh_period;
+   wire [10:0] refresh_address;
+   wire       refresh_en;
+   wire       refresh_set;
   assign      port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);  
 //   assign en_cmd0_wr=     axiwr_bram_wen   && (axiwr_bram_waddr[11:10]==2'h1);
 //   assign en_port0_rd=    axird_bram_ren   && (axird_bram_raddr[11:10]==2'h0);
@@ -275,6 +310,7 @@ module  ddrc_test01 #(
   assign axird_bram_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
   assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
+   assign locked=locked_mmcm && locked_pll;
 always @ (posedge axi_aclk) begin
   port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
 end
@@ -294,6 +330,119 @@ always @ (negedge frst[0] or posedge axi_aclk) begin
    else          frst_inv <= 1'b0; 
 end
+    /* Instance template for module PULLDOWN */
+    PULLDOWN PULLDOWN_i (
+        .O(MEMCLK) // output 
+    );
+wire dbg_clk; // = fclk[1] ^ MEMCLK;
+//BUFG dbg_clk_ii (.O(dbg_clk),.I(fclk[1] ^ MEMCLK));
+BUFG dbg_clk_ii (.O(dbg_clk),.I(MEMCLK));
+//(* dont_touch = "true" *) 
+reg [7:0] dbg_toggle;
+//always @ (posedge axi_rst or posedge axi_aclk) begin
+wire dbg_rst=frst[1] && !frst[0]; 
+always @ (posedge dbg_rst or posedge dbg_clk) begin
+//always @ (posedge axi_rst or posedge dbg_clk) begin
+//always @ (posedge fclk[1]) begin
+   if   (dbg_rst) dbg_toggle <= 8'ha5;
+   else           dbg_toggle <= dbg_toggle+1; //dbg_toggle+1;
+end
+/*
+     dly_addr[1],
+    dly_addr[0],
+    clkin_stopped_mmcm,
+    clkfb_stopped_mmcm,
+    ddr_rst,
+    rst_in,
+    dci_rst,
+    dly_rst
+*/
+//MEMCLK
+wire [63:0] gpio_in;
+assign gpio_in={
+16'b0,
+    1'b1,              // 1
+    MEMCLK,            // 1/0? - external clock
+    dbg_rst,           // 1
+    fclk[1] ^ MEMCLK, //dbg_clk,           // 0/1 
+    frst[1],           // 1 (follows)
+    fclk[1:0],         // 2'bXX (toggle)
+    axird_dev_busy,    // 0
+{frst[2]?8'h5a:{
+    dbg_toggle[7:4],   // 4'b1111 -> 4'ha
+    dbg_toggle[3:0]}},   // 4'b1111 -> 4'ha
+    tmp_debug[7:4],    // 4'b0111 -> 4'bx00x
+                       //    dly_addr[1],
+                       //    dly_addr[0],
+                       //    clkin_stopped_mmcm,
+                       //    clkfb_stopped_mmcm,
+    tmp_debug[3:0],    // 4'b1100 -> 4'bxx00
+                       //    ddr_rst,
+                       //    rst_in,
+                       //    dci_rst,
+                       //    dly_rst
+    phy_locked_mmcm,   // 0 1
+    phy_locked_pll,    // 0 1
+    phy_dly_ready,     // 0 1
+    phy_dci_ready,     // 1 1
+    locked_mmcm,       // 0 1 
+    locked_pll,        // 0 1
+    dly_ready,         // 0 1
+    dci_ready,         // 0 1
+    ps_out[7:4],       // 4'b0 input[7:0] 4'b0
+    ps_out[3:0],       // 4'b0 input[7:0] 4'b0
+    run_busy, // input // 0 
+    locked, // input   // 0
+    ps_rdy, // input   // 0
+    axi_arready,       // 1
+    axi_awready,       // 1 
+    axi_wready,        // 1 
+    axi_aclk,          // 0/1 
+    axi_rst            // 0
+};
+/*
+  assign tmp_debug ={
+  1'b1,
+    clkin_stopped_mmcm,
+    clkfb_stopped_mmcm,
+    clk_in, // dbg_reg3,
+    dbg_reg2,
+    dbg_reg1,
+    rst_in,
+    dly_rst
+  };
+*/
+//assign DUMMY_TO_KEEP = ^gpio_in[63:0]; // to keep PS7 signals from "optimization"
+assign DUMMY_TO_KEEP = dbg_toggle[0];
+/*
+        .rdata            (status_rdata[31:0]), // output[31:0] 
+        .busy             (axird_dev_busy), // output
+//        .run_done         (run_done), // input
+        .run_busy         (run_busy), // input
+        .locked           (locked), // input
+        .ps_rdy           (ps_rdy), // input
+        .ps_out           (ps_out[7:0]) // input[7:0] 
+*/
 /*
 `ifndef IVERILOG
 (* dont_touch = "true" *)
@@ -302,7 +451,9 @@ end
 */
 //BUFG bufg_axi_rst_i  (.O(axi_rst),.I(~frst[0]));
-BUFG bufg_axi_rst_i  (.O(axi_rst),.I(frst_inv));
+//assign axi_rst=~frst[0];
+assign axi_rst=~frst[0] || frst[1]; // prevent releasing reset before explicit command 
+//BUFG bufg_axi_rst_i  (.O(axi_rst),.I(frst_inv));
 BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
    axibram_write #(
@@ -390,7 +541,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .CMDA_EN_REL           (CMDA_EN_REL),
        .CMDA_EN_REL_MASK      (CMDA_EN_REL_MASK),
        .SDRST_ACT_REL         (SDRST_ACT_REL),  
-        .SDRST_ACT_REL_MASK(SDRST_ACT_REL_MASK),
+        .SDRST_ACT_REL_MASK    (SDRST_ACT_REL_MASK),
        .CKE_EN_REL            (CKE_EN_REL),   
        .CKE_EN_REL_MASK       (CKE_EN_REL_MASK),
        .DCI_RST_REL           (DCI_RST_REL),
@@ -398,7 +549,14 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .DLY_RST_REL           (DLY_RST_REL),
        .DLY_RST_REL_MASK      (DLY_RST_REL_MASK),
        .EXTRA_REL             (EXTRA_REL),
-        .EXTRA_REL_MASK    (EXTRA_REL_MASK)
+        .EXTRA_REL_MASK        (EXTRA_REL_MASK),
+        .REFRESH_EN_REL        (REFRESH_EN_REL),
+        .REFRESH_EN_REL_MASK   (REFRESH_EN_REL_MASK),
+        .REFRESH_PER_REL       (REFRESH_PER_REL),
+        .REFRESH_PER_REL_MASK  (REFRESH_PER_REL_MASK),
+        .REFRESH_ADDR_REL      (REFRESH_ADDR_REL),
+        .REFRESH_ADDR_REL_MASK (REFRESH_ADDR_REL_MASK)
    ) ddrc_control_i (
        .clk                 (axiwr_bram_wclk),         // same as axi_aclk
        .mclk                (mclk),                    // input
@@ -409,9 +567,19 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .wr_en               (axiwr_bram_wen),          // input
        .wdata               (axiwr_bram_wdata[31:0]),  // input[31:0] (no input for wstb here) 
        .busy                (axiwr_dev_busy),          // output
-        .run_addr            (run_addr[10:0]),          // output[10:0] 
+        .run_addr            (axi_run_addr[10:0]),          // output[10:0] 
-        .run_chn             (run_chn[3:0]),            // output[3:0] 
+        .run_chn             (axi_run_chn[3:0]),            // output[3:0] 
-        .run_seq             (run_seq),                 // output
+        .run_seq             (axi_run_seq),                 // output
+        .run_seq_rq_in       (run_seq_rq_in),           // input
+        .run_seq_rq_gen      (run_seq_rq_gen),          // output
+        .run_seq_busy        (run_busy),                // input
+        .refresh_address     (refresh_address[10:0]), // output[10:0] 
+        .refresh_period      (refresh_period[7:0]), // output[7:0] 
+        .refresh_set         (refresh_set), // output
+        .refresh_en          (refresh_en), // output
        .dly_data            (dly_data[7:0]),           // output[7:0] 
        .dly_addr            (dly_addr[6:0]),           // output[6:0] 
        .ld_delay            (ld_delay),                // output
@@ -435,6 +603,43 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .port1_int_page      (port1_int_page[1:0])      // output[1:0] 
    );
+    assign run_addr = axi_run_seq ?  axi_run_addr[10:0] : refresh_address[10:0];
+    assign run_chn =  axi_run_seq ?  axi_run_chn[3:0] : 4'h0;
+    assign run_seq = axi_run_seq || refresh_grant;
+/*
+   wire        run_seq_rq_in; // higher priority request to run sequence
+   wire        run_seq_rq_gen;// SuppressThisWarning VEditor : unused this wants to run sequencer 
+//   wire        run_seq_busy;  // sequencer is busy or access granted to other master
+run_busy
+    wire [10:0] refresh_address;
+*/    
+//   assign run_seq_rq_in = 1'b0; // higher priority request input
+    wire       refresh_want;
+    wire       refresh_need;
+    reg        refresh_grant;
+   assign run_seq_rq_in = refresh_en && refresh_need; // higher priority request input
+    ddr_refresh ddr_refresh_i (
+        .rst              (axi_rst), // input
+        .clk              (mclk), // input
+        .refresh_period   (refresh_period[7:0]), // input[7:0] 
+        .set              (refresh_set), // input
+        .want             (refresh_want), // output
+        .need             (refresh_need), // output
+        .grant            (refresh_grant) // input
+    );
+    always @ (posedge axi_rst or  posedge mclk) begin
+         if (axi_rst) refresh_grant <= 0; 
+         refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need || (refresh_want && !run_seq_rq_gen)); 
+    end
    ddrc_status
 //     #(
 //        .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
@@ -456,6 +661,11 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
 //        .run_done         (run_done), // input
        .run_busy         (run_busy), // input
        .locked           (locked), // input
+        .locked_mmcm      (locked_mmcm), // input
+        .locked_pll       (locked_pll), // input
+        .dly_ready        (dly_ready), // input
+        .dci_ready        (dci_ready), // input
        .ps_rdy           (ps_rdy), // input
        .ps_out           (ps_out[7:0]) // input[7:0] 
    );
@@ -528,7 +738,18 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
        .dly_addr       (dly_addr[6:0]), // input[6:0] 
        .ld_delay       (ld_delay), // input
        .set            (set), // input
-        .locked         (locked), // output
+//        .locked         (locked), // output
+        .locked_mmcm     (locked_mmcm), // output
+        .locked_pll      (locked_pll), // output
+        .dly_ready       (dly_ready), // output
+        .dci_ready       (dci_ready), // output
+        .phy_locked_mmcm (phy_locked_mmcm), // output
+        .phy_locked_pll  (phy_locked_pll), // output
+        .phy_dly_ready   (phy_dly_ready), // output
+        .phy_dci_ready   (phy_dci_ready), // output
+        .tmp_debug       (tmp_debug[7:0]),
        .ps_rdy         (ps_rdy), // output
        .ps_out         (ps_out[7:0]), // output[7:0]
@@ -633,7 +854,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
    .EMIOENET1MDIOI(),           // MDIO 1 MD data input, input
  // EMIO GPIO
    .EMIOGPIOO(),                // EMIO GPIO Data out[63:0], output
-    .EMIOGPIOI(),                // EMIO GPIO Data in[63:0], input
+    .EMIOGPIOI(gpio_in[63:0]),   // EMIO GPIO Data in[63:0], input
    .EMIOGPIOTN(),               // EMIO GPIO OutputEnable[63:0], output
  // EMIO I2C 0  
    .EMIOI2C0SCLO(),             // I2C 0 SCL OUT, output // manual says input
@@ -819,7 +1040,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
    .FPGAIDLEN(1'b1),             //Idle PL AXI interfaces (active low), input
 // AXI PS Master GP0    
 // AXI PS Master GP0: Clock, Reset
-    .MAXIGP0ACLK(axi_aclk),       // AXI PS Master GP0 Clock , input
+//    .MAXIGP0ACLK(axi_aclk),       // AXI PS Master GP0 Clock , input
+    .MAXIGP0ACLK(fclk[0]),       // AXI PS Master GP0 Clock , input
+    //
    .MAXIGP0ARESETN(),            // AXI PS Master GP0 Reset, output
 // AXI PS Master GP0: Read Address    
    .MAXIGP0ARADDR  (axi_araddr[31:0]), // AXI PS Master GP0 ARADDR[31:0], output  

--- a/ddrc_test01.xdc
+++ b/ddrc_test01.xdc
@@ -203,6 +203,16 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}]
 set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
 set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
+#    output                      DUMMY_TO_KEEP,  // to keep PS7 signals from "optimization"
+set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
+set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
+#not yet used, just for debugging
+#    input                      MEMCLK,  // to keep PS7 signals from "optimization"
+set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
+set_property PACKAGE_PIN M5 [get_ports {MEMCLK}]
 # Global constraints

--- a/ddrc_test01_testbench.sav
+++ b/ddrc_test01_testbench.sav
 [*]
 [*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
-[*] Mon Jun  2 06:48:00 2014
+[*] Thu Jun  5 05:24:36 2014
 [*]
-[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140602003755521.lxt"
+[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140604231824572.lxt"
-[dumpfile_mtime] "Mon Jun  2 06:40:41 2014"
+[dumpfile_mtime] "Thu Jun  5 05:22:25 2014"
-[dumpfile_size] 76024228
+[dumpfile_size] 80462049
 [savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
-[timestart] 102360000
+[timestart] 0
 [size] 1920 1180
-[pos] 0 108
+[pos] -1 -1
-*-22.533184 131161875 114486875 114489375 114571875 114574375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-17.404953 635800 114486875 114489375 114571875 114574375 115289323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] ddrc_test01_testbench.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.
@@ -20,10 +20,8 @@
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.
-[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.
-[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].
@@ -36,10 +34,111 @@
 [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
 [treeopen] ddrc_test01_testbench.simul_axi_master_rdaddr_i.
 [treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.
-[sst_width] 334
+[sst_width] 551
-[signals_width] 403
+[signals_width] 367
 [sst_expanded] 1
-[sst_vpaned_height] 755
+[sst_vpaned_height] 370
+@c00200
+-PS7_AXI
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.FCLKRESETN[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RVALID[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARREADY[0]
+@200
+-
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BID[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BRESP[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BVALID[0]
+@200
+-
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WDATA[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WID[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WLAST[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WREADY[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WSTRB[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WVALID[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ACLK[0]
+@1401200
+-PS7_AXI
+@200
+-
+@c00200
+-MAXIGP0
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ACLK[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARADDR[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARBURST[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARCACHE[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARESETN[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARID[11:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARLEN[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARLOCK[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARPROT[2:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARQOS[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARSIZE[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0ARVALID[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWADDR[31:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWBURST[1:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWCACHE[3:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWID[11:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWLEN[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWLOCK[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWPROT[2:0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWQOS[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWSIZE[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0AWVALID[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BID[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BRESP[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0BVALID[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RDATA[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RID[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RLAST[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RREADY[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RRESP[1:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0RVALID[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WDATA[31:0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WID[11:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WLAST[0]
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WREADY[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WSTRB[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ps7_i.MAXIGP0WVALID[0]
+@1401200
+-MAXIGP0
 @28
 ddrc_test01_testbench.RST[0]
 ddrc_test01_testbench.CLK[0]
@@ -672,7 +771,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_bas
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.vcoflag[0]
 @1401200
 -plle2_adv_1
-@c00200
+@800200
 -phy_top_i
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
@@ -729,7 +828,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_data
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_data_l[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_delay[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ld_mmcm[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked_mmcm[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.locked_pll[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
@@ -740,13 +838,19 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ndqsu[0
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ps_out[7:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.ps_rdy[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst_in[0]
+@29
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
+@28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.set[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
-@1401200
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dbg_reg1[0]
+@200
+-
+@1000200
 -phy_top_i
 @c00200
 -mmcm_phase_cntr
@@ -1008,6 +1112,32 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0]
 @1000200
 -ddrc_status
+@800200
+-ddr_refresh
+@28
+ddrc_test01_testbench.ddrc_test01_i.refresh_en[0]
+ddrc_test01_testbench.ddrc_test01_i.refresh_grant[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.clk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.cry[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.grant[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.need[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.over[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.pending_rq[4:0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.period_cntr[7:0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.pre_div[3:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.refresh_due[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.refresh_period[7:0]
+@28
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.rst[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.set[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_refresh_i.want[0]
+@1000200
+-ddr_refresh
+@200
+-
 @c00200
 -fifo_cross_clocks
 @22
@@ -1110,9 +1240,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.dqs_tri_prev[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.inv_clk_div[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ld_delay[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ld_delay_r[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r1[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r2[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.mclk[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr[29:0]
@@ -1140,7 +1267,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dq_tri_in[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dqs_tri_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_locked[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_odt[1:0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_odt_in[0]
 @22
@@ -1250,7 +1376,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.dqs_pattern[7:0]
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.inv_clk_div[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.ld_delay[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.locked[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
 @22
@@ -1307,6 +1432,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0]
 -ddrc_sequencer
 @800200
 -ddr_sequencer_i_selected
+@c00200
 -tristate_control
 @28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0]
@@ -1335,12 +1461,33 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.dq_tri_prev[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dq_tri_in[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
-@28
+@1401200
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iobufs_dqs_i.T[0]
-@1000200
 -tristate_control
 @28
+ddrc_test01_testbench.ddrc_test01_i.refresh_need[0]
+ddrc_test01_testbench.ddrc_test01_i.refresh_en[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq_rq_in[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_re[0]
+ddrc_test01_testbench.ddrc_test01_i.ddr_rst[0]
+ddrc_test01_testbench.ddrc_test01_i.axi_run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.mclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq_busy[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq_rq_gen[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.run_seq_r[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.decoded_run_seq[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_nempty[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_re[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_half_empty[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
+@22
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_addr[10:0]
+ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_chn[3:0]
+@200
+-
+@28
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCLK[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCKE[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDBA[2:0]
@@ -1599,7 +1746,7 @@ ddrc_test01_testbench.ddrc_test01_i.set[0]
 ddrc_test01_testbench.ddrc_test01_i.status_rdata[31:0]
 @1401200
 -ddrc_test01
-@c00200
+@800200
 -axibram_write_i
 @28
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aclk[0]
@@ -1736,6 +1883,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
 @1401200
 -axibram_write_wdata
+@1000200
 -axibram_write_i
 @c00200
 -wresp_i
@@ -1827,7 +1975,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
 ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
 @1401200
 -wdata_i
-@c00200
+@800200
 -axibram_read_i
 @28
 ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.aclk[0]
@@ -1927,7 +2075,7 @@ ddrc_test01_testbench.SIMUL_AXI_FULL[0]
 ddrc_test01_testbench.rstb[0]
 @200
 -
-@1401200
+@1000200
 -axibram_read_i
 @c00200
 -ddrc_status
@@ -2255,11 +2403,8 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_la
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.rst[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.set_idelay[0]
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.set_odelay[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IDATAIN[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.tin[3:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.fdly[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_reg[4:0]
 @1401200
 -dqs1_i
 @800200
@@ -2285,11 +2430,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_la
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.set_odelay[0]
 @22
 ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.tin[3:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IDATAIN[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.fdly[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_reg[4:0]
 @1000200
 -dq0_i
 @200
@@ -2358,218 +2498,10 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_la
 -
 @c00200
 -dq1_idelay2
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CALC_TAPDELAY_FD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CALC_TAPDELAY_RD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CE[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CINVCTRL[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEIN[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEIN_INTEGER[31:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEOUT[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.C[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAIN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAOUT[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAOUT_reg[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DELAY_D[31:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.GSR[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IDATAIN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IFDLY[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INC[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INIT_DELAY_FD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INIT_DELAY_RD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.LDPIPEEN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.LD[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.REGRST[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.c_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.c_in_pre[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ce_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cinvctrl_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cntvaluein_in[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cntvalueout_pre[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.data_mux[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.datain_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_c[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ce[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_0[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_1[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_2[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_3[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_4[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_5[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_6[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_7[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_8[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_9[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_10[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_11[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_12[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_13[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_14[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_15[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_16[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_17[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_18[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_19[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_20[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_21[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_22[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_23[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_24[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_25[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_26[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_27[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_28[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_29[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_30[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_31[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_cinvctrl[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_cntvaluein[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_datain[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_idatain[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ifdly[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_inc[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ld[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ldpipeen[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_regrst[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_0[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_1[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_2[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_3[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_4[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_5[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.gsr_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.idatain_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.idelay_count[31:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ifdly_in[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.inc_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ld_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ldpipeen_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_mux[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_reg[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.regrst_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_fd[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_final[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_rd[0]
 @1401200
 -dq1_idelay2
 @c00200
 -dq0_idelay2
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-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CALC_TAPDELAY_FD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CALC_TAPDELAY_RD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CE[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CINVCTRL[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEIN[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEIN_INTEGER[31:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.CNTVALUEOUT[4:0]
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-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.C[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAIN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAOUT[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DATAOUT_reg[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.DELAY_D[31:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.GSR[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IDATAIN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.IFDLY[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INC[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INIT_DELAY_FD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.INIT_DELAY_RD
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.LDPIPEEN[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.LD[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.REGRST[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.c_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.c_in_pre[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ce_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cinvctrl_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cntvaluein_in[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.cntvalueout_pre[4:0]
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-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.data_mux[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.datain_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_c[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ce[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_0[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_1[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_2[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_3[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_4[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_5[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_6[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_7[0]
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-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_10[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_11[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_12[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_13[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_14[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_15[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_16[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_17[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_18[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_19[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_20[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_21[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_22[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_23[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_24[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_25[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_26[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_27[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_28[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_29[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_30[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_chain_31[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_cinvctrl[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_cntvaluein[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_datain[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_idatain[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ifdly[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_inc[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ld[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_ldpipeen[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.delay_regrst[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_0[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_1[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_2[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_3[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_4[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.fine_delay_5[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.gsr_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.idatain_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.idelay_count[31:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ifdly_in[2:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.inc_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ld_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.ldpipeen_in[0]
-@22
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_mux[4:0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.qcntvalueout_reg[4:0]
-@28
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.regrst_in[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_fd[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_final[0]
-ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dqs_in_dly_i.idelay2_finedelay_i.tap_out_rd[0]
 @1401200
 -dq0_idelay2
 [pattern_trace] 1

--- a/ddrc_test01_testbench.tf
+++ b/ddrc_test01_testbench.tf
@@ -95,6 +95,12 @@ module  ddrc_test01_testbench #(
    parameter DLY_RST_REL_MASK =      'h3fe,  // address mask for delay calibration circuitry
    parameter EXTRA_REL =             'h02e,  // address to set extra parameters (currently just inv_clk_div)
    parameter EXTRA_REL_MASK =        'h3ff,  // address mask for extra parameters
+    parameter REFRESH_EN_REL =        'h030,  // address to enable('h31) and disable ('h30) DDR refresh
+    parameter REFRESH_EN_REL_MASK =   'h3fe,  // address mask to enable/disable DDR refresh
+    parameter REFRESH_PER_REL =       'h032,  // address to set refresh period in 32 x tCK
+    parameter REFRESH_PER_REL_MASK =  'h3ff,  // address mask set refresh period
+    parameter REFRESH_ADDR_REL =      'h033,  // address to set sequencer start address for DDR refresh
+    parameter REFRESH_ADDR_REL_MASK = 'h3ff,  // address mask set refresh sequencer address
    // simulation-specific parameters
    parameter integer AXI_RDADDR_LATENCY=2,
@@ -141,6 +147,11 @@ module  ddrc_test01_testbench #(
 // SuppressWarnings VEditor
    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h02e, address to set extra parameters (currently just inv_clk_div)
+    localparam BASEADDR_REFRESH_EN =   BASEADDR_CTRL | (REFRESH_EN_REL<<2);    // address to enable('h31) and disable ('h30) DDR refresh
+    localparam BASEADDR_REFRESH_PER =   BASEADDR_CTRL | (REFRESH_PER_REL<<2);    // address ('h32) to set refresh period in 32 x tCK
+    localparam BASEADDR_REFRESH_ADDR =   BASEADDR_CTRL | (REFRESH_ADDR_REL<<2);    // address ('h33)to set sequencer start address for DDR refresh
    localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;  
    localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);  
    localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);  
@@ -181,7 +192,10 @@ module  ddrc_test01_testbench #(
    localparam WBUF_DLY_WLV=    4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
 //    localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
-    localparam WRITELEV_OFFSET=    'h20; // write leveling start address (in words)
+    localparam INITIALIZE_OFFSET=  'h00; // moemory initialization start address (in words) ..`h0c
+    localparam REFRESH_OFFSET=     'h10; // refresh start address (in words) ..`h13
+    localparam WRITELEV_OFFSET=    'h20; // write leveling start address (in words) ..`h2a
    localparam READ_PATTERN_OFFSET='h40; // read pattern to memory block sequence start address (in words) ..'h053 with 8x2*64 bits (variable)
    localparam WRITE_BLOCK_OFFSET= 'h100; // write block sequence start address (in words) ..'h14c
    localparam READ_BLOCK_OFFSET=  'h180; // read  block sequence start address (in words)
@@ -206,7 +220,8 @@ module  ddrc_test01_testbench #(
  wire        SDDMU;  // inout
  wire        DQSU;   // inout
  wire        NDQSU;  // inout
+  wire        DUMMY_TO_KEEP;  // output to keep PS7 signals from "optimization"
+  wire        MEMCLK;
  // Simulation signals
  reg [11:0] ARID_IN_r;
@@ -339,11 +354,15 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
  // SuppressWarnings VEditor : assigned in $readmem() system task
    $dumpvars(0,ddrc_test01_testbench);
    CLK <=1'b0;
-    RST <= 1'b1;
+    RST <= 1'bx;
    AR_SET_CMD_r <= 1'b0;
    AW_SET_CMD_r <= 1'b0;
    W_SET_CMD_r <= 1'b0;
-    #100000; // same as glbl
+    #500;
+    $display ("ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst=%d",ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst);
+    #500;
+    RST <= 1'b1;
+    #99000; // same as glbl
    repeat (20) @(posedge CLK) ;
    RST <=1'b0;
    axi_set_b_lag(0); //(1);
@@ -354,13 +373,22 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
    enable_cmda(1);
    repeat (16) @(posedge CLK) ;
    activate_sdrst(0); // was enabled at system reset
+    set_refresh(
+        50, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
+        16); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
    #5000; // actually 500 usec required
    repeat (16) @(posedge CLK) ;
    enable_cke(1);
    repeat (16) @(posedge CLK) ;
    set_mrs(1);
-    set_write_lev(16); // write leveling, 16 times   (full buffer - 128) 
+    run_sequence(0,INITIALIZE_OFFSET);
+    repeat (4) @(posedge CLK) ;
+//    wait_sequencer_ready(16);
+// enable refresh    
+    enable_refresh(1);
+    set_write_lev(16); // write leveling, 16 times   (full buffer - 128) 
    // set dq /dqs tristate on/off patterns
    axi_write_single(BASEADDR_PATTERNS_TRI, {16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
@@ -368,7 +396,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
    #100;
 //    $finish;
-    run_sequence(0,0);
+    run_sequence(0,INITIALIZE_OFFSET);
    wait_sequencer_ready(16);
    axi_write_single(BASEADDR_PATTERNS, 32'h0055); // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
@@ -379,6 +407,12 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 //axi_set_dqs_idelay_nominal;
    run_sequence(0,WRITELEV_OFFSET);
+// trying multiple run_sequence    
+    run_sequence(0,WRITELEV_OFFSET);
+    run_sequence(0,WRITELEV_OFFSET);
+    wait_sequencer_ready(16);
+    wait_sequencer_ready(16);
    wait_sequencer_ready(16);
 `ifdef use200Mhz
    axi_set_dly_single(0,8,'h78); // was 'h74 dqs lane 0, odelay    
@@ -483,7 +517,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 assign ddrc_test01_i.ps7_i.FCLKCLK=        {4{CLK}};
-assign ddrc_test01_i.ps7_i.FCLKRESETN=     {4{~RST}};
+assign ddrc_test01_i.ps7_i.FCLKRESETN=     {RST,~RST,RST,~RST};
 // Read address
 assign ddrc_test01_i.ps7_i.MAXIGP0ARADDR=  araddr;
 assign ddrc_test01_i.ps7_i.MAXIGP0ARVALID= arvalid;
@@ -598,7 +632,13 @@ assign bresp=                              ddrc_test01_i.ps7_i.MAXIGP0BRESP;
        .DLY_RST_REL           (DLY_RST_REL),
        .DLY_RST_REL_MASK      (DLY_RST_REL_MASK),
        .EXTRA_REL             (EXTRA_REL),
-        .EXTRA_REL_MASK        (EXTRA_REL_MASK)
+        .EXTRA_REL_MASK        (EXTRA_REL_MASK),
+        .REFRESH_EN_REL        (REFRESH_EN_REL),
+        .REFRESH_EN_REL_MASK   (REFRESH_EN_REL_MASK),
+        .REFRESH_PER_REL       (REFRESH_PER_REL),
+        .REFRESH_PER_REL_MASK  (REFRESH_PER_REL_MASK),
+        .REFRESH_ADDR_REL      (REFRESH_ADDR_REL),
+        .REFRESH_ADDR_REL_MASK (REFRESH_ADDR_REL_MASK)
    ) ddrc_test01_i (
        .SDRST   (SDRST), // DDR3 reset (active low)
        .SDCLK   (SDCLK), // output 
@@ -616,7 +656,9 @@ assign bresp=                              ddrc_test01_i.ps7_i.MAXIGP0BRESP;
        .NDQSL   (NDQSL), // inout
        .SDDMU   (SDDMU), // inout
        .DQSU    (DQSU), // inout
-        .NDQSU   (NDQSU) // inout
+        .NDQSU   (NDQSU), // inout
+        .DUMMY_TO_KEEP(DUMMY_TO_KEEP),  // to keep PS7 signals from "optimization"
+        .MEMCLK  (MEMCLK)
    );
 // Micron DDR3 memory model
    /* Instance of Micron DDR3 memory model */
@@ -991,6 +1033,15 @@ simul_axi_read simul_axi_read_i(
        //BASEADDR_CMDA_EN
        end
    endtask
+    task enable_refresh;
+        input en;
+        begin
+            if (en) 
+                axi_write_single(BASEADDR_REFRESH_EN+4, 0);
+            else 
+                axi_write_single(BASEADDR_REFRESH_EN, 0);
+        end
+    endtask
    task write_block_buf;
        integer i,j;
@@ -1788,7 +1839,12 @@ simul_axi_read simul_axi_read_i(
             cmd_addr <= cmd_addr + 4;
-             data <= encode_seq_skip(2,0,1,1); // Keep DCI and ODT active 
+//             data <= encode_seq_skip(1,0,1,1); // Keep DCI and ODT active 
+//             @(posedge CLK)
+//             axi_write_single(cmd_addr, data);
+//             cmd_addr <= cmd_addr + 4;
+//             
+             data <= encode_seq_skip(2,0,1,0); // Keep DCI (but not ODT) active  ODT should be off befor MRS
             @(posedge CLK)
             axi_write_single(cmd_addr, data);
             cmd_addr <= cmd_addr + 4;
@@ -1826,6 +1882,48 @@ simul_axi_read simul_axi_read_i(
        end
    endtask
+    task set_refresh;
+        input [ 9:0] t_rfc; // =50 for tCK=2.5ns
+        input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
+        reg [31:0] cmd_addr;
+        reg [31:0] data;
+        begin
+             cmd_addr <= BASEADDR_CMD0 + (REFRESH_OFFSET<<2);
+             @(posedge CLK)
+             data <=  encode_seq_word(
+                15'h0,              // [14:0] phy_addr_in;
+                3'b0,               // [ 2:0] phy_bank_in; //TODO: debug!
+                3'b110,             // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
+                1'b0,               //        phy_odt_in; // may be optimized?
+                1'b0,               // phy_cke_inv; // may be optimized?
+                1'b0,               // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
+                1'b0,               // phy_dq_en_in;
+                1'b0,               // phy_dqs_en_in;
+                1'b0,               // phy_dqs_toggle_en;
+                1'b0,               // phy_dci_en_in;      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                1'b0,               // phy_buf_wr;   // connect to external buffer
+                1'b0,               // phy_buf_rd;   // connect to external buffer
+                1'b0);              // add NOP after the current command, keep other data
+             @(posedge CLK)
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             data <= encode_seq_skip(t_rfc,0,0,0); // =50 tREFI=260 ns before next ACTIVATE or REFRESH, @2.5ns clock, @5ns cycle
+             @(posedge CLK)
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+// Ready for normal operation
+             data <= encode_seq_skip(0,1,0,0); // sequence done bit, skip length is ignored
+             @(posedge CLK)
+             axi_write_single(cmd_addr, data);
+             cmd_addr <= cmd_addr + 4;
+             axi_write_single(BASEADDR_REFRESH_ADDR, REFRESH_OFFSET);
+             axi_write_single(BASEADDR_REFRESH_PER, {24'h0,t_refi});
+        end
+    endtask         
    task set_mrs; // will also calibrate ZQ
        input reset_dll;

--- a/ddrc_test01_timing.xdc
+++ b/ddrc_test01_timing.xdc
@@ -32,11 +32,49 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
 #clkfb_ref    10.00000  {0.00000 5.00000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
 #clk_ref_pre  3.33333   {0.00000 1.66667}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
-create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
+#Each list contains 2 elements - warning later in DRC
-create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
+#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
-create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
+#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
-create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
-create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
+#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
+#Not available initially
+#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
+#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
+#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
+# try use first from list - seems that 2 are created from the same name 
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
+# lindex is not supported in xdc
+#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
+#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
+##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
+create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
+create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
+create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
+create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
+create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
+#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical *sdclk_pre ]
+#create_generated_clock -name ddr3_clk [get_nets -hierarchical *clk_pre ]
+#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical *clk_div_pre ]
+#create_generated_clock -name ddr3_mclk [get_nets -hierarchical *mclk_pre ]
+#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical *clk_ref_pre ]
 # do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
 set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
--- a/phy/cmda_single.v
+++ b/phy/cmda_single.v
--- a/phy/ddrc_sequencer.v
+++ b/phy/ddrc_sequencer.v
@@ -90,7 +90,17 @@ module  ddrc_sequencer   #(
    input                  [6:0] dly_addr, // select which delay to program
    input                        ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
    input                        set,       // clk_div synchronous set all delays from previously loaded values
-    output                       locked,
+//    output                       locked,
+    output                       locked_mmcm,
+    output                       locked_pll,
+    output                       dly_ready,
+    output                       dci_ready,
+    output                       phy_locked_mmcm,
+    output                       phy_locked_pll,
+    output                       phy_dly_ready,
+    output                       phy_dci_ready,
+    output               [7:0]   tmp_debug,
    output                       ps_rdy,
    output     [PHASE_WIDTH-1:0] ps_out, 
 // read port 0
@@ -162,6 +172,18 @@ module  ddrc_sequencer   #(
    reg                   [3:0]  run_chn_d;
    reg                          run_seq_d; 
+//    reg tmp_dbg7=0;
+    wire [7:0] tmp_debug_a;
+    /*
+    always @ (posedge clk_in) begin
+        tmp_dbg7 <= ~tmp_dbg7;
+    end
+    assign tmp_debug[7:0] = {tmp_dbg7,tmp_debug_a[6:0]};
+    */
+    assign tmp_debug[7:0] = tmp_debug_a[7:0];
+ //   clk_in
    assign run_done=sequence_done;
    assign run_busy=cmd_busy[0]; //earliest
    assign  pause=cmd_fetch? (phy_cmd_add_pause || (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
@@ -174,6 +196,8 @@ module  ddrc_sequencer   #(
    always @ (posedge mclk or posedge rst) begin
        if (rst)                cmd_busy <= 0;
 //        else if (sequence_done) cmd_busy <= 0;
+        else if (ddr_rst) cmd_busy <= 0; // *************** reset sequencer with DDR reset
        else if (sequence_done &&  cmd_busy[2]) cmd_busy <= 0;
        else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]}; 
        // Pause counter
@@ -364,7 +388,19 @@ module  ddrc_sequencer   #(
        .dly_addr            (dly_addr[6:0]), // input[6:0] 
        .ld_delay            (ld_delay), // input
        .set                 (set), // input
-        .locked              (locked), // output
+//        .locked              (locked), // output
+        .locked_mmcm         (locked_mmcm), // output
+        .locked_pll          (locked_pll), // output
+        .dly_ready           (dly_ready), // output
+        .dci_ready           (dci_ready), // output
+        .phy_locked_mmcm     (phy_locked_mmcm), // output
+        .phy_locked_pll      (phy_locked_pll), // output
+        .phy_dly_ready       (phy_dly_ready), // output
+        .phy_dci_ready       (phy_dci_ready), // output
+        .tmp_debug           (tmp_debug_a[7:0]),
        .ps_rdy              (ps_rdy), // output
        .ps_out              (ps_out[7:0]), // output[7:0]
 /// debugging

--- a/phy/dm_single.v
+++ b/phy/dm_single.v
@@ -19,10 +19,10 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .
 *******************************************************************************/
 `timescale 1ns/1ps
+//`define use_iobuf 1
 module  dm_single #(
    parameter IODELAY_GRP ="IODELAY_MEMORY",
-    parameter IBUF_LOW_PWR ="TRUE",
+    parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
    parameter IOSTANDARD = "SSTL15_T_DCI",
    parameter SLEW = "SLOW",
    parameter real REFCLK_FREQUENCY = 300.0,
@@ -60,7 +60,7 @@ odelay_fine_pipe # (
    .DELAY_VALUE(0),
    .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
    .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
-) dqs_out_dly_i(
+) dm_out_dly_i(
    .clk(clk_div),
    .rst(rst),
    .set(set_odelay),
@@ -69,14 +69,14 @@ odelay_fine_pipe # (
    .data_in(d_ser),
    .data_out(dq_data_dly)
 );
+`ifdef use_iobuf
 IOBUF_DCIEN #(
    .IBUF_LOW_PWR(IBUF_LOW_PWR), //
    .IOSTANDARD(IOSTANDARD),
    .SLEW(SLEW),
    .USE_IBUFDISABLE("FALSE")
 // SuppressWarnings VivadoSynthesis : VivadoSynthesis: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed 
-) iobufs_dqs_i (
+) iobufs_dm_i (
 //    .O(dq_di),
    .O(),
    .IO(dm),
@@ -84,5 +84,18 @@ IOBUF_DCIEN #(
    .IBUFDISABLE(1'b0),
    .I(dq_data_dly), //dqs_data),
    .T(dq_tri));
+`else    
+    /* Instance template for module OBUFT_DCIEN */
+    OBUFT_DCIEN #(
+        .IOSTANDARD(IOSTANDARD),
+        .SLEW(SLEW)
+    ) iobufs_dm_i (
+        .O(dm), // output 
+        .DCITERMDISABLE(dci_disable), // input 
+        .I(dq_data_dly), // input 
+        .T(dq_tri) // input 
+    );
+`endif    
 endmodule
--- a/phy/dq_single.v
+++ b/phy/dq_single.v
@@ -71,7 +71,7 @@ odelay_fine_pipe # (
    .DELAY_VALUE(0),
    .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
    .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
-) dqs_out_dly_i(
+) dq_out_dly_i(
    .clk(clk_div),
    .rst(rst),
    .set(set_odelay),
@@ -86,7 +86,7 @@ IOBUF_DCIEN #(
    .IOSTANDARD(IOSTANDARD),
    .SLEW(SLEW),
    .USE_IBUFDISABLE("FALSE")
-) iobufs_dqs_i (
+) iobufs_dq_i (
    .O(dq_di),
    .IO(dq),
    .DCITERMDISABLE(dci_disable),
@@ -99,7 +99,7 @@ idelay_fine_pipe # (
    .DELAY_VALUE(0),
    .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
    .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
-) dqs_in_dly_i(
+) dq_in_dly_i(
    .clk(clk_div),
    .rst(rst),
    .set(set_idelay),

--- a/phy/dqs_single.v
+++ b/phy/dqs_single.v
@@ -19,7 +19,6 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .
 *******************************************************************************/
 `timescale 1ns/1ps
 module  dqs_single #(
    parameter IODELAY_GRP ="IODELAY_MEMORY",
    parameter IBUF_LOW_PWR ="TRUE",
@@ -34,6 +33,9 @@ module  dqs_single #(
    input       clk_div,
    input       rst,
    output      dqs_received_dly,
+//    output      dqs_di, // debugging:
+     //Input buffer ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_S (in ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i macro) has no loads. An input buffer must drive an internal load.
    input       dci_disable,  // disable DCI termination during writes and idle
    input [7:0] dly_data,
    input [3:0] din,
@@ -90,7 +92,6 @@ IOBUFDS_DCIEN #(
    .IBUFDISABLE(1'b0),
    .I(dqs_data_dly), //dqs_data),
    .T(dqs_tri));
 idelay_fine_pipe # (
    .IODELAY_GRP(IODELAY_GRP),
    .DELAY_VALUE(0),
@@ -105,6 +106,5 @@ idelay_fine_pipe # (
    .data_in(dqs_di),
    .data_out(dqs_received_dly)
 );
 endmodule
--- a/phy/phy_cmd.v
+++ b/phy/phy_cmd.v
@@ -76,7 +76,19 @@ module  phy_cmd#(
    input                  [6:0] dly_addr, // select which delay to program
    input                        ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
    input                        set,       // clk_div synchronous set all delays from previously loaded values
-    output                       locked,
+//    output                       locked,
+    output                       locked_mmcm,
+    output                       locked_pll,
+    output                       dly_ready,
+    output                       dci_ready,
+    output                       phy_locked_mmcm,
+    output                       phy_locked_pll,
+    output                       phy_dly_ready,
+    output                       phy_dci_ready,
+    output               [7:0]   tmp_debug,
    output                       ps_rdy,
    output     [PHASE_WIDTH-1:0] ps_out, 
 // command port
@@ -161,11 +173,17 @@ module  phy_cmd#(
    wire                         phy_dci_dis_dqs;
    reg                          dqs_tri_prev, dq_tri_prev;
-    wire                         phy_locked;
+//    wire                         phy_locked;
    wire                         phy_ps_rdy;
    wire       [PHASE_WIDTH-1:0] phy_ps_out; 
-    reg                          locked_r1,locked_r2;
+//    reg                          locked_r1,locked_r2;
    reg                          ps_rdy_r1,ps_rdy_r2;
+    reg                          locked_mmcm_r1,locked_mmcm_r2;
+    reg                          locked_pll_r1, locked_pll_r2;
+    reg                          dly_ready_r1, dly_ready_r2;
+    reg                          dci_ready_r1, dci_ready_r2;
    reg        [PHASE_WIDTH-1:0] ps_out_r1,ps_out_r2; 
    wire                  [63:0] phy_rdata; // data read from ddr3 iserdese2 at posedge clk_div
    reg                   [63:0] phy_rdata_r; // registered @ posedge mclk
@@ -175,6 +193,11 @@ module  phy_cmd#(
    wire   [ADDRESS_NUMBER-1:0] phy_addr_calm;
    wire                 [ 2:0] phy_bank_calm;
    reg                  [ 8:0] extra_prev;
+//    assign     phy_locked= phy_locked_mmcm && phy_locked_pll; // no dci and dly here
 //    output                [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
    // SuppressWarnings VEditor 
  (* keep = "true" *)  wire  phy_spare;
@@ -252,10 +275,15 @@ module  phy_cmd#(
    assign  phy_dci_dis_dq =   phy_dci_in;         // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
    assign  phy_dci_dis_dqs =  phy_dci_in || phy_odt_cur;  // In write leveling mode phy_dci_in = 0, phy_odt_cur=1 - use DCI on DQ only, no DQS
-    assign  locked = locked_r2;
+//    assign  locked = locked_r2;
    assign  ps_rdy = ps_rdy_r2;
    assign  ps_out = ps_out_r2;
+    assign  locked_mmcm = locked_mmcm_r2;
+    assign  locked_pll = locked_pll_r2;
+    assign  dly_ready = dly_ready_r2;
+    assign  dci_ready = dci_ready_r2;
    assign buf_wdata[63:0] = phy_rdata_r[63:0];
    assign cmda_tri=!cmda_en;
@@ -307,14 +335,25 @@ module  phy_cmd#(
 // cross clock boundary posedge posedge clk_div->negedge clk_div -> posedge mclk  (mclk is later than clk_div)    
    always @ (negedge clk_div) begin
-        locked_r1 <=   phy_locked;
+//        locked_r1 <=   phy_locked;
        ps_rdy_r1 <=   phy_ps_rdy;
        ps_out_r1 <=   phy_ps_out;
+        locked_mmcm_r1 <= phy_locked_mmcm;
+        locked_pll_r1  <= phy_locked_pll;
+        dly_ready_r1   <= phy_dly_ready;
+        dci_ready_r1   <= phy_dci_ready;
    end
    always @ (posedge mclk) begin
-        locked_r2 <=   locked_r1;
+//        locked_r2 <=   locked_r1;
        ps_rdy_r2 <=   ps_rdy_r1;
        ps_out_r2 <=   ps_out_r1; 
+        locked_mmcm_r2 <= locked_mmcm_r1;
+        locked_pll_r2  <= locked_pll_r1;
+        dly_ready_r2   <= dly_ready_r1;
+        dci_ready_r2   <= dci_ready_r1;
    end
@@ -405,7 +444,12 @@ module  phy_cmd#(
        .dly_addr        (dly_addr_r), // input[6:0] 
        .ld_delay        (ld_delay_r), // input
        .set             (set_r), // input
-        .locked          (phy_locked), // output
+//        .locked          (phy_locked), // output
+        .locked_mmcm     (phy_locked_mmcm), // output
+        .locked_pll      (phy_locked_pll), // output
+        .dly_ready       (phy_dly_ready), // output
+        .dci_ready       (phy_dci_ready), // output
+        .tmp_debug       (tmp_debug[7:0]),
        .ps_rdy          (phy_ps_rdy), // output
        .ps_out          (phy_ps_out) // output[7:0] 
    );

--- a/phy/phy_top.v
+++ b/phy/phy_top.v
@@ -106,25 +106,63 @@ module  phy_top #(
    input                  [6:0] dly_addr, // select which delay to program
    input                        ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
    input                        set,       // clk_div synchronous set all delays from previously loaded values
-    output                       locked,
+//    output                       locked,
+    output                       locked_mmcm,
+    output                       locked_pll,
+    output                       dly_ready,
+    output                       dci_ready,
+    output               [7:0]   tmp_debug,
    output                       ps_rdy,
    output     [PHASE_WIDTH-1:0] ps_out 
 );
-  reg rst=1'b0;
+  reg rst= 1'b1;
+//  reg rst_dbg=1'b1;
 //  always @(posedge clk_div or posedge rst_in) begin // got min hold violation
  always @(negedge clk_div or posedge rst_in) begin
    if (rst_in) rst <= 1'b1;
    else        rst <= 1'b0;
  end
+//  always @(posedge clk_div or posedge rst_in) begin
+//    if (rst_in) rst_dbg <= 1'b1;
+//    else        rst_dbg <= 1'b0;
+//  end
  wire  ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ;             
  wire  ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;             
  wire  ld_cmda =   (dly_addr[6:5] == 2'h2) && ld_delay ;             
  wire  ld_mmcm=    (dly_addr[6:0] == 7'h60) && ld_delay ;
  wire  clkfb_ref, clk_ref_pre; 
  wire  clk_ref; // 200MHz/300Mhz to calibrate I/O delays            
-  wire locked_mmcm,locked_pll, dly_ready, dci_ready;
+//  wire locked_mmcm,locked_pll, dly_ready, dci_ready;
-  assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
+//  assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
+  wire clkin_stopped_mmcm;
+  wire clkfb_stopped_mmcm;
+/*
+  reg dbg_reg1=1;
+  reg dbg_reg2=1;
+  reg dbg_reg3=1;
+*/  
+  assign tmp_debug ={
+    dly_addr[1],
+    dly_addr[0],
+    clkin_stopped_mmcm,
+    clkfb_stopped_mmcm,
+    ddr_rst,
+    rst_in,
+    dci_rst,
+    dly_rst
+  };
+  /*
+  always @ (posedge clk_in) begin
+    dbg_reg1 <= ~dbg_reg1;
+  end
+  always @ (posedge clk_ref) begin
+    dbg_reg2 <= ~dbg_reg2;
+  end
+  always @ (posedge clk_div) begin
+    dbg_reg3 <= ~dbg_reg3;
+  end
+  */
 /* memory reset */
    obuf #(
        .CAPACITANCE("DONT_CARE"),
@@ -241,9 +279,10 @@ wire sdclk; // BUFIO
    ) oddr_ds_i (
        .clk(sdclk), // input
        .ce(1'b1), // input
-        .rst(1'b0), // input
+        .rst(rst), // input
        .set(1'b0), // input
        .din(2'b01), // input[1:0] 
+        .tin(rst),   // tristate at reset
        .dq(ddr3_clk), // output
        .ndq(ddr3_nclk) // output
    );
@@ -321,9 +360,12 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
        .clkout1b(), // output
        .clkout2b(), // output
        .clkout3b(), // output
-        .clkfbout(clk_fb), // output
+        .clkfbout            (clk_fb), // output
        .clkfboutb(), // output
-        .locked(locked_mmcm) // output
+        .locked              (locked_mmcm),
+        .clkin_stopped       (clkin_stopped_mmcm), // output
+        .clkfb_stopped       (clkfb_stopped_mmcm) // output
+         // output
    );
 // Generate reference clock for the I/O delays
@@ -357,11 +399,10 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
        .rst(rst || dly_rst),
        .rdy(dly_ready)
    );
    dci_reset dci_reset_i (
        .reset(rst || dci_rst), // input
        .ready(dci_ready) // output
    );
+//assign dci_ready= !(rst || dci_rst); 
 endmodule
--- a/wrap/mmcm_phase_cntr.v
+++ b/wrap/mmcm_phase_cntr.v
@@ -95,7 +95,9 @@ module  mmcm_phase_cntr#(
    output clkout3b, // output 3, inverted
    output clkfbout, // dedicate feedback output    
    output clkfboutb,// inverted feedback output
-    output locked   // PLL locked output
+    output locked,   // PLL locked output
+    output clkin_stopped,
+    output clkfb_stopped
 );
    reg [PHASE_WIDTH-1:0] ps_dout_r;
    wire psen;       // phase shift enable input
@@ -185,8 +187,8 @@ module  mmcm_phase_cntr#(
    ) MMCME2_ADV_i (
        .CLKFBOUT       (clkfbout), // output
        .CLKFBOUTB      (clkfboutb), // output
-        .CLKFBSTOPPED      (), // output
+        .CLKFBSTOPPED   (clkfb_stopped), // output
-        .CLKINSTOPPED      (), // output
+        .CLKINSTOPPED   (clkin_stopped), // output
        .CLKOUT0        (clkout0), // output
        .CLKOUT0B       (clkout0b), // output
        .CLKOUT1        (clkout1), // output

--- a/wrap/oddr_ds.v
+++ b/wrap/oddr_ds.v
@@ -33,6 +33,7 @@ module  oddr_ds # (
    input  rst,
    input  set,
    input [1:0] din,
+    input  tin, // tristate control
    output dq,
    output ndq
 );
@@ -53,6 +54,7 @@ module  oddr_ds # (
    );
    /* Instance template for module OBUFDS */
+/*    
    OBUFDS #(
        .CAPACITANCE(CAPACITANCE),
        .IOSTANDARD(IOSTANDARD),
@@ -62,7 +64,19 @@ module  oddr_ds # (
        .OB(ndq), // output 
        .I(idq) // input 
    );
+*/
+    /* Instance template for module OBUFTDS */
+    OBUFTDS #(
+        .CAPACITANCE (CAPACITANCE),
+        .IOSTANDARD  (IOSTANDARD),
+        .SLEW        (SLEW)
+    ) OBUFDS_i (
+        .O  (dq), // output 
+        .OB (ndq), // output 
+        .I  (idq), // input 
+//        .T  (tin || rst) // input 
+        .T  (tin) // input 
+    );
 endmodule
--- a/wrap/oserdes_mem.v
+++ b/wrap/oserdes_mem.v
@@ -51,11 +51,11 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
               .DATA_RATE_OQ         (DATA_RATE),
               .DATA_RATE_TQ         (DATA_RATE),
               .DATA_WIDTH           (DATA_WIDTH),
-               .INIT_OQ              (1'b0),
+               .INIT_OQ              (1'b1),
-               .INIT_TQ              (1'b0),
+               .INIT_TQ              (1'b1),
               .SERDES_MODE          ("MASTER"),
-               .SRVAL_OQ             (1'b0),
+               .SRVAL_OQ             (1'b1),
-               .SRVAL_TQ             (1'b0),
+               .SRVAL_TQ             (1'b1),
               .TRISTATE_WIDTH       (DATA_WIDTH_TRI),
               .TBYTE_CTL            ("FALSE"), 
               .TBYTE_SRC            ("FALSE")
@@ -94,13 +94,13 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
               .DATA_RATE_TQ         (DATA_RATE),
               .DATA_WIDTH           (DATA_WIDTH),
 //               .DDR3_DATA            (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
-               .INIT_OQ              (1'b0),
+               .INIT_OQ              (1'b1),
-               .INIT_TQ              (1'b0),
+               .INIT_TQ              (1'b1),
               .INTERFACE_TYPE       ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3" 
               .ODELAY_USED          (0),         // 1 available only for MEMORY_DDR3
               .SERDES_MODE          ("MASTER"),
-               .SRVAL_OQ             (1'b0),
+               .SRVAL_OQ             (1'b1),
-               .SRVAL_TQ             (1'b0),
+               .SRVAL_TQ             (1'b1),
               .TRISTATE_WIDTH       (DATA_WIDTH_TRI)
            ) oserdes_i (
               .OFB                 (dout_dly),