merged with framepars

Makefile

+VERILOGDIR=   $(DESTDIR)/usr/local/verilog
+INSTALLDIR=   $(DESTDIR)/usr/local/bin
+DOCUMENTROOT= $(DESTDIR)/www/pages
+
+SCRIPTPATH=   py393
+COCOTB =      cocotb
+ 
+LINK = ln
+OWN = -o root -g root
+#INSTALL = $(INSTALL)
+INSTMODE   = 0755
+DOCMODE    = 0644
+PYTHON_EXE = $(SCRIPTPATH)/*.py \
+             cocotb/socket_command.py
+               
+FPGA_BITFILES =   *.bit
+VERILOG_HEADERS = system_defines.vh \
+                  includes/x393_parameters.vh \
+				  includes/x393_localparams.vh \
+				  includes/x393_cur_params_target.vh
+				  
+COMMAND_FILES =   py393/hargs \
+				  py393/hargs-auto \
+				  py393/includes \
+				  py393/startup5 \
+				  py393/startup14
+
+all:
+	@echo "make all in x393"
+install:
+	@echo "make install in x393"
+	$(INSTALL) $(OWN) -d $(VERILOGDIR)
+	$(INSTALL) $(OWN) -d $(DOCUMENTROOT)
+	$(INSTALL) $(OWN) -d $(INSTALLDIR)
+
+	$(INSTALL) $(OWN) -m $(INSTMODE) $(PYTHON_EXE)                          $(INSTALLDIR)
+    
+	$(INSTALL) $(OWN) -m $(DOCMODE) $(FPGA_BITFILES)                        $(VERILOGDIR)
+	$(INSTALL) $(OWN) -m $(DOCMODE) $(VERILOG_HEADERS)                      $(VERILOGDIR)
+	$(INSTALL) $(OWN) -m $(DOCMODE) $(COMMAND_FILES)                        $(VERILOGDIR)
+
+	$(LINK) -s -r        $(INSTALLDIR)/imgsrv.py                            $(DOCUMENTROOT)
+#	$(INSTALL) $(OWN) -m $(INSTMODE) $(SCRIPTPATH)/imgsrv.py                $(DOCUMENTROOT)
+#unistall
+#    rm $(SCRIPTPATH)/imgsrv.py
+
+clean:
+	@echo "make clean in x393"
+	
\ No newline at end of file

py393/hargs

@@ -4,7 +4,7 @@
 -l /usr/local/verilog/x393_cur_params_target.vh
 -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
 -c bitstream_set_path /usr/local/verilog/x393_parallel.bit
--c setupSensorsPower  "PAR12"  all  0  0.0
+-c setupSensorsPower  "PAR12"  all  0  0.1
 -c measure_all "*DI"
 -c setSensorClock 24.0 "2V5_LVDS"
 -c set_rtc

py393/hargs-eyesis

@@ -4,7 +4,9 @@
 -l /usr/local/verilog/x393_cur_params_target.vh
 -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
 -c bitstream_set_path /usr/local/verilog/x393_parallel.bit
--c setupEyesisPower 50 100
+-c setupSensorsPower  "PAR12"  all  0  0.2
+-c setEyesisPower 1
+-c sleep_ms 20
 -c measure_all "*DI"
 -c setSensorClock 24.0 "2V5_LVDS"
 -c set_rtc

py393/x393_jpeg.py

@@ -1065,6 +1065,16 @@ write_cmd_frame_sequencer  0  1  4  0x6c0  0x1c48 # reset  reset compressor memo
 write_cmd_frame_sequencer  0  1  8  0x6c0  0x3d4b # enable run compressor memory       (+2)
 write_cmd_frame_sequencer  0  1  8  0x600  0x7    # enable run compressor              (+0)
 
+write_cmd_frame_sequencer  1  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  1  1  4  0x600  0x4    #reset   reset compressor            (+2)
+write_cmd_frame_sequencer  1  1  4  0x6c0  0x1c48 # reset  reset compressor memory     (+0)
+write_cmd_frame_sequencer  1  1  8  0x6c0  0x3d4b # enable run compressor memory       (+2)
+write_cmd_frame_sequencer  1  1  8  0x600  0x7    # enable run compressor              (+0)
+
+
+
+
+
 set_qtables all 0 80
 
 set_rtc # maybe not needed as it can be set differently