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x393
Commit cba3cc1c authored by Andrey Filippov's avatar Andrey Filippov
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continue on initial x393 with a memory controller

parent f948ab8f
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address_map.txt
View file @ cba3cc1c
......@@ -2,18 +2,28 @@
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
0x1020 - DLY_SET // 0 bits -set pre-programmed delays
0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
0x1024..1025 - CMDA_EN // 0 bits - disable/enable command/address outputs
0x1026..1027 - SDRST_ACT // 0 bits - disable/enable active-low reset signal to DDR3 memory
0x1028..1029 - CKE_EN // 0 bits - disable/enable CKE signal to memory
0x102a..102b - DCI_RST // 0 bits - disable/enable CKE signal to memory
0x102c..102d - DLY_RST // 0 bits - disable/enable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // disable/enable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // disable/enable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // disable/enable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // disable/enable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // disable/enable CKE signal to memory
0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
0x1040..107f - 16-bit data
0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
......@@ -31,12 +41,25 @@
0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h3f0, // Address mask to set channel priorities
0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h3f8, // address mask to set mcontr top control registers
0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
0x1071 - REFRESH_PERIOD // 8-bit refresh period
0x1072 - REFRESH_ADDRESS // 10 bits
0x1073 - STATUS_CNTRL // 8 bits - write to status control (and debug?)
parameter MCONTR_TOP_16BIT_CHN_EN = 'h0, // 16 bits per-channel enable (want/need requests)
parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
// Status read address
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
parameter STATUS_ADDR_MASK = 'h1400, // AXI write address of status registers
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
================================ OLD =======================================================
Control addresses (in original ddrc_test01)
......
memctrl/ddr_refresh.v
View file @ cba3cc1c
......@@ -23,6 +23,7 @@
module ddr_refresh(
input rst,
input clk,
input en,
input [7:0] refresh_period, // in 16*clk, 0 - disable refresh, turn off requests
input set, // and reset counters
output reg want, // turns off next cycle after grant (or stays on if more are needed)
......@@ -36,8 +37,12 @@ module ddr_refresh(
wire over=(period_cntr == 0) && cry;
reg refresh_due;
reg en_refresh;
reg en_r;
always @ (posedge rst or posedge clk) begin
if (rst) en_r <= 0;
else en_r <= en;
if (rst) en_refresh <= 0;
else if (set) en_refresh <= (refresh_period != 0);
......@@ -63,10 +68,10 @@ module ddr_refresh(
else if (!refresh_due && grant) pending_rq <= pending_rq-1;
if (rst) want <= 0;
else want<= en_refresh && (pending_rq != 0);
else want<= en_refresh && en_r && (pending_rq != 0);
if (rst) need <= 0;
else need <= en_refresh && (pending_rq[4:3] != 0);
else need <= en_refresh && en_r && (pending_rq[4:3] != 0);
end
endmodule
memctrl/memctrl16.v
View file @ cba3cc1c
This diff is collapsed.
memctrl/scheduler16.v
View file @ cba3cc1c
......@@ -25,8 +25,9 @@ module scheduler16 #(
)(
input rst,
input clk,
input [15:0] want_rq, // both want_rq and need_rq should go inactive after being granted
input [15:0] need_rq,
input [width-1:0] chn_en, // channel enable mask
input [width-1:0] want_rq, // both want_rq and need_rq should go inactive after being granted
input [width-1:0] need_rq,
input en_schedul, // needs to be disabled before next access can be scheduled
output need, // granted access is "needed" one, not just "wanted"
output grant, // single-cycle granted channel access
......@@ -36,18 +37,13 @@ module scheduler16 #(
input [width-1:0] pgm_data, // priority data for the channel
input pgm_en // enable programming priority data (use different clock?)
);
// reg [width-1:0] pri00,pri01,pri02,pri03,pri04,pri05,pri06,pri07,pri08,pri09,pri10,pri11,pri12,pri13,pri14,pri15;
reg [width*16-1:0] pri_reg;
reg [15:0] want_conf, need_conf,need_want_conf;
// wire new_want,new_need;
// wire event_w;
wire [15:0] want_set,need_set;
reg [15:0] want_set_r,need_set_r;
// reg event_r, want_r;
reg need_r;
reg [width*16-1:0] sched_state;
wire need_some=| need_rq;
// wire want_some=| want_rq;
wire need_some=|(need_rq & & chn_en);
wire [15:0] next_want_conf,next_need_conf;
wire [3:0] index; // channel index to select
wire index_valid; // selected index valid ("needed" or "wanted")
......@@ -55,9 +51,8 @@ module scheduler16 #(
reg grant_sent; // turns on after grant, until en_schedul is de-asserted
reg [3:0] grant_chn_r;
wire grant_w;
// assign event_w=new_want | new_need;
assign next_want_conf=(want_conf & want_rq) | want_set;
assign next_need_conf=(need_conf & need_rq) | need_set;
assign next_want_conf=(want_conf & want_rq & chn_en) | want_set;
assign next_need_conf=(need_conf & need_rq & chn_en) | need_set;
assign grant=grant_r;
assign grant_chn=grant_chn_r;
assign grant_w=en_schedul && index_valid && !grant_sent;
......@@ -72,15 +67,13 @@ module scheduler16 #(
endgenerate
pri1hot16 i_pri1hot16_want(
.in(want_rq & ~want_conf ),
.in(want_rq & ~want_conf & chn_en),
.out(want_set),
.some());
// .some(new_want));
pri1hot16 i_pri1hot16_need(
.in(need_rq & ~need_conf ),
.in(need_rq & ~need_conf & chn_en),
.out(need_set),
.some());
// .some(new_need));
always @(posedge rst or posedge clk) begin
if (rst) begin
......@@ -95,12 +88,10 @@ module scheduler16 #(
always @ (posedge clk) begin
want_set_r<=want_set;
need_set_r<=need_set;
//event_r <= event_w;
//want_r<= want_some;
need_r<= need_some;
end
// TODO: want remains, need is removed (both need and want should be deactivated on grant!)
// Block that sets initila process state and increments it on every change of the requests
// Block that sets initial process state and increments it on every change of the requests
generate
genvar i1;
for (i1=0;i1<16;i1=i1+1) begin: sched_state_block
......
phy/mcontr_sequencer.v
View file @ cba3cc1c
......@@ -22,8 +22,13 @@
module mcontr_sequencer #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
//0x1080..10ff - 8- bit data - to set various delay values
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
// 0x1080..109f - set delay for SDD0-SDD7
// 0x10a0..10bf - set delay for SDD8-SDD15
// 0x10c0..10df - set delay for SD_CMDA
// 0x10e0 - set delay for MMCM
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
......@@ -126,7 +131,7 @@ module mcontr_sequencer #(
input run_seq, // start controller sequence (will and with !ddr_rst for stable mclk)
output run_done, // controller sequence finished
output run_busy, // controller sequence in progress
output mcontr_reset, // == ddr_reset that also resets sequencer
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -146,7 +151,7 @@ module mcontr_sequencer #(
// Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay?
output ext_buf_wr,
output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
output [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead of ext_buf_wr!, maybe not needed - will be generated externally
output [63:0] ext_buf_wdata, // valid with ext_buf_wr
// temporary debug data
output [11:0] tmp_debug
......@@ -244,6 +249,7 @@ module mcontr_sequencer #(
phy_dci_ready,
tmp_debug_a[7:0]};
assign mcontr_reset=ddr_rst; // to reset controller
assign run_done=sequence_done;
assign run_busy=cmd_busy[0]; //earliest
assign pause=cmd_fetch? (phy_cmd_add_pause || (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
......@@ -296,7 +302,7 @@ module mcontr_sequencer #(
.stb (cmd_stb), // input
.addr (phy_0bit_addr), // output[15:0]
.data (), // output[31:0]
.we( phy_0bit_we) // output
.we (phy_0bit_we) // output
);
assign set= phy_0bit_we && (phy_0bit_addr==MCONTR_PHY_0BIT_DLY_SET);
......@@ -331,7 +337,7 @@ module mcontr_sequencer #(
.stb (cmd_stb), // input
.addr (phy_16bit_addr), // output[15:0]
.data (phy_16bit_data), // output[31:0]
.we( phy_16bit_we) // output
.we (phy_16bit_we) // output
);
wire set_patterns;
wire set_patterns_tri;
......
x393.v
View file @ cba3cc1c
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