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Commit c9e297d5 authored by Andrey Filippov's avatar Andrey Filippov
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fixed cmdseqmux - reporting interrupt status and mask correctly

parent ebdb638e
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.project
View file @ c9e297d5
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160319192210839.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160327140517650.log</location>
</link> </link>
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<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160319192210839.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160327140517650.log</location>
</link> </link>
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<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160319192210839.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160327140517650.log</location>
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<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
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<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160319192210839.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160327140517650.log</location>
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<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
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<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
...@@ -127,7 +127,7 @@ ...@@ -127,7 +127,7 @@
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<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160319192210839.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160327135949141.dcp</location>
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</projectDescription> </projectDescription>
fpga_version.vh
View file @ c9e297d5
...@@ -31,7 +31,8 @@ ...@@ -31,7 +31,8 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly
// parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK // parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h03930079; // diff - failed // parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff // parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
......
util_modules/cmd_seq_mux.v
View file @ c9e297d5
...@@ -97,8 +97,8 @@ module cmd_seq_mux#( ...@@ -97,8 +97,8 @@ module cmd_seq_mux#(
wire ackn_w; //pre-acknowledge of one of the channels wire ackn_w; //pre-acknowledge of one of the channels
reg [3:0] ackn_r; reg [3:0] ackn_r;
wire [3:0] is = {is[3], is[2], is[1], is[0]}; wire [3:0] is = {is3, is2, is1, is0};
wire [3:0] im = {im[3], im[2], im[1], im[0]}; wire [3:0] im = {im3, im2, im1, im0};
assign pri_one_rr = {wr_en[3] & ~(|wr_en[2:0]), wr_en[2]&~(|wr_en[1:0]), wr_en[1] & wr_en[0], wr_en[0], assign pri_one_rr = {wr_en[3] & ~(|wr_en[2:0]), wr_en[2]&~(|wr_en[1:0]), wr_en[1] & wr_en[0], wr_en[0],
wr_en[3], wr_en[2]&~(|wr_en[1:0])&wr_en[3], wr_en[1] & ~ wr_en[3] & wr_en[0], wr_en[0] & ~ wr_en[3], wr_en[3], wr_en[2]&~(|wr_en[1:0])&wr_en[3], wr_en[1] & ~ wr_en[3] & wr_en[0], wr_en[0] & ~ wr_en[3],
......
x393.bit
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