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Elphel
x393
Commits
c9e297d5
Commit
c9e297d5
authored
Mar 27, 2016
by
Andrey Filippov
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fixed cmdseqmux - reporting interrupt status and mask correctly
parent
ebdb638e
Changes
4
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4 changed files
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15 additions
and
14 deletions
+15
-14
.project
.project
+11
-11
fpga_version.vh
fpga_version.vh
+2
-1
cmd_seq_mux.v
util_modules/cmd_seq_mux.v
+2
-2
x393.bit
x393.bit
+0
-0
No files found.
.project
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c9e297d5
...
@@ -62,52 +62,52 @@
...
@@ -62,52 +62,52 @@
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...
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...
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fpga_version.vh
View file @
c9e297d5
...
@@ -31,7 +31,8 @@
...
@@ -31,7 +31,8 @@
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*******************************************************************************/
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
parameter FPGA_VERSION = 32'h0393007c; // fixed cmdseqmux - reporting interrupt status and mask correctly
// parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
...
...
util_modules/cmd_seq_mux.v
View file @
c9e297d5
...
@@ -97,8 +97,8 @@ module cmd_seq_mux#(
...
@@ -97,8 +97,8 @@ module cmd_seq_mux#(
wire
ackn_w
;
//pre-acknowledge of one of the channels
wire
ackn_w
;
//pre-acknowledge of one of the channels
reg
[
3
:
0
]
ackn_r
;
reg
[
3
:
0
]
ackn_r
;
wire
[
3
:
0
]
is
=
{
is
[
3
]
,
is
[
2
]
,
is
[
1
]
,
is
[
0
]
};
wire
[
3
:
0
]
is
=
{
is
3
,
is2
,
is1
,
is0
};
wire
[
3
:
0
]
im
=
{
im
[
3
]
,
im
[
2
]
,
im
[
1
]
,
im
[
0
]
};
wire
[
3
:
0
]
im
=
{
im
3
,
im2
,
im1
,
im0
};
assign
pri_one_rr
=
{
wr_en
[
3
]
&
~
(
|
wr_en
[
2
:
0
])
,
wr_en
[
2
]
&~
(
|
wr_en
[
1
:
0
])
,
wr_en
[
1
]
&
wr_en
[
0
]
,
wr_en
[
0
]
,
assign
pri_one_rr
=
{
wr_en
[
3
]
&
~
(
|
wr_en
[
2
:
0
])
,
wr_en
[
2
]
&~
(
|
wr_en
[
1
:
0
])
,
wr_en
[
1
]
&
wr_en
[
0
]
,
wr_en
[
0
]
,
wr_en
[
3
]
,
wr_en
[
2
]
&~
(
|
wr_en
[
1
:
0
])
&
wr_en
[
3
]
,
wr_en
[
1
]
&
~
wr_en
[
3
]
&
wr_en
[
0
]
,
wr_en
[
0
]
&
~
wr_en
[
3
]
,
wr_en
[
3
]
,
wr_en
[
2
]
&~
(
|
wr_en
[
1
:
0
])
&
wr_en
[
3
]
,
wr_en
[
1
]
&
~
wr_en
[
3
]
&
wr_en
[
0
]
,
wr_en
[
0
]
&
~
wr_en
[
3
]
,
...
...
x393.bit
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c9e297d5
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