Skip to content

X
x393
Commit c8b52324 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing

parent 1d2f08b7
Show whitespace changes
Inline Side-by-side
Showing with 316 additions and 118 deletions
memctrl/cmd_encod_linear_wr.v
View file @ c8b52324
......@@ -26,7 +26,8 @@ module cmd_encod_linear_wr #(
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -185,13 +186,14 @@ module cmd_encod_linear_wr #(
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h2: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT); // single cycle
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // single cycle
// 4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_ODT); // single cycle
// next may loop
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (WSEL << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
......
memctrl/cmd_encod_tiled_32_wr.v
View file @ c8b52324
......@@ -47,8 +47,8 @@ module cmd_encod_tiled_32_wr #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -235,20 +235,21 @@ module cmd_encod_tiled_32_wr #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// loop
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hf: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/cmd_encod_tiled_wr.v
View file @ c8b52324
......@@ -49,8 +49,8 @@ module cmd_encod_tiled_wr #(
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input clk,
......@@ -235,17 +235,18 @@ module cmd_encod_tiled_wr #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
// 4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN);
4'h4: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// start loop
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......
memctrl/phy/phy_cmd.v
View file @ c8b52324
......@@ -371,8 +371,8 @@ module phy_cmd#(
wire [7:0] dqs_data;
// assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'h0;
assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'hff;
assign dqs_data=phy_dqs_toggle_cur?dqs_pattern[7:0]:8'h0; // Has to be low to satisfy write levelling preamble
phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
......
wrap/ddr3_wrap.v
View file @ c8b52324
......@@ -23,14 +23,14 @@
module ddr3_wrap#(
parameter ADDRESS_NUMBER = 15,
parameter TRISTATE_DELAY_CLK = 2,
parameter TRISTATE_DELAY_CLK = 4'h2,
parameter TRISTATE_DELAY = 0,
parameter CLK_DELAY = 0,
parameter CMDA_DELAY = 0,
parameter DQS_IN_DELAY = 0,
parameter DQ_IN_DELAY = 0,
parameter DQS_OUT_DELAY = 0,
parameter DQ_OUT_DELAY = 0
parameter CLK_DELAY = 1500,
parameter CMDA_DELAY = 1500,
parameter DQS_IN_DELAY = 1500,
parameter DQ_IN_DELAY = 1500,
parameter DQS_OUT_DELAY = 1500,
parameter DQ_OUT_DELAY = 1500
)(
input mclk,
input [1:0] dq_tri,
......@@ -56,27 +56,88 @@ module ddr3_wrap#(
inout NDQSU //,
);
wire #(CLK_DELAY) SDCLK_D = SDCLK;
wire #(CLK_DELAY) SDNCLK_D = SDNCLK;
wire #(CMDA_DELAY) SDRST_D = SDRST;
wire [ADDRESS_NUMBER-1:0] #(CMDA_DELAY) SDA_D = SDA;
wire [2:0] #(CMDA_DELAY) SDBA_D = SDBA;
wire #(CMDA_DELAY) SDWE_D = SDWE;
wire #(CMDA_DELAY) SDRAS_D = SDRAS;
wire #(CMDA_DELAY) SDCAS_D = SDCAS;
wire #(CMDA_DELAY) SDCKE_D = SDCKE;
wire #(CMDA_DELAY) SDODT_D = SDODT;
// generate
/*
input mclk,
input [1:0] dq_tri,
input [1:0] dqs_tri,
*/
wire [1:0] en_dq_d;
wire [1:0] en_dqs_d;
wire [1:0] #(TRISTATE_DELAY) en_dq = en_dq_d;
wire [1:0] #(TRISTATE_DELAY) en_dqs = en_dqs_d;
localparam CLK_DELAY_H = CLK_DELAY/4;
localparam CMDA_DELAY_H = CMDA_DELAY/4;
localparam DQS_IN_DELAY_H = DQS_IN_DELAY/4;
localparam DQ_IN_DELAY_H = DQ_IN_DELAY/4;
localparam DQS_OUT_DELAY_H = DQS_OUT_DELAY/4;
localparam DQ_OUT_DELAY_H = DQ_OUT_DELAY/4;
wire #(CLK_DELAY_H) SDCLK_H1 = SDCLK;
wire #(CLK_DELAY_H) SDNCLK_H1 = SDNCLK;
wire #(CMDA_DELAY_H) SDRST_H1 = SDRST;
wire [ADDRESS_NUMBER-1:0] #(CMDA_DELAY_H) SDA_H1 = SDA;
wire [2:0] #(CMDA_DELAY_H) SDBA_H1 = SDBA;
wire #(CMDA_DELAY_H) SDWE_H1 = SDWE;
wire #(CMDA_DELAY_H) SDRAS_H1 = SDRAS;
wire #(CMDA_DELAY_H) SDCAS_H1 = SDCAS;
wire #(CMDA_DELAY_H) SDCKE_H1 = SDCKE;
wire #(CMDA_DELAY_H) SDODT_H1 = SDODT;
wire #(CLK_DELAY_H) SDCLK_H2 = SDCLK_H1;
wire #(CLK_DELAY_H) SDNCLK_H2 = SDNCLK_H1;
wire #(CMDA_DELAY_H) SDRST_H2 = SDRST_H1;
wire [ADDRESS_NUMBER-1:0] #(CMDA_DELAY_H) SDA_H2 = SDA_H1;
wire [2:0] #(CMDA_DELAY_H) SDBA_H2 = SDBA_H1;
wire #(CMDA_DELAY_H) SDWE_H2 = SDWE_H1;
wire #(CMDA_DELAY_H) SDRAS_H2 = SDRAS_H1;
wire #(CMDA_DELAY_H) SDCAS_H2 = SDCAS_H1;
wire #(CMDA_DELAY_H) SDCKE_H2 = SDCKE_H1;
wire #(CMDA_DELAY_H) SDODT_H2 = SDODT_H1;
wire #(CLK_DELAY_H) SDCLK_H3 = SDCLK_H2;
wire #(CLK_DELAY_H) SDNCLK_H3 = SDNCLK_H2;
wire #(CMDA_DELAY_H) SDRST_H3 = SDRST_H2;
wire [ADDRESS_NUMBER-1:0] #(CMDA_DELAY_H) SDA_H3 = SDA_H2;
wire [2:0] #(CMDA_DELAY_H) SDBA_H3 = SDBA_H2;
wire #(CMDA_DELAY_H) SDWE_H3 = SDWE_H2;
wire #(CMDA_DELAY_H) SDRAS_H3 = SDRAS_H2;
wire #(CMDA_DELAY_H) SDCAS_H3 = SDCAS_H2;
wire #(CMDA_DELAY_H) SDCKE_H3 = SDCKE_H2;
wire #(CMDA_DELAY_H) SDODT_H3= SDODT_H2;
wire #(CLK_DELAY_H) SDCLK_D = SDCLK_H3;
wire #(CLK_DELAY_H) SDNCLK_D = SDNCLK_H3;
wire #(CMDA_DELAY_H) SDRST_D = SDRST_H3;
wire [ADDRESS_NUMBER-1:0] #(CMDA_DELAY_H) SDA_D = SDA_H3;
wire [2:0] #(CMDA_DELAY_H) SDBA_D = SDBA_H3;
wire #(CMDA_DELAY_H) SDWE_D = SDWE_H3;
wire #(CMDA_DELAY_H) SDRAS_D = SDRAS_H3;
wire #(CMDA_DELAY_H) SDCAS_D = SDCAS_H3;
wire #(CMDA_DELAY_H) SDCKE_D = SDCKE_H3;
wire #(CMDA_DELAY_H) SDODT_D = SDODT_H3;
wire [1:0] en_dq_dl;
wire [1:0] en_dqs_dl;
wire [1:0] #(TRISTATE_DELAY) en_dq_d0 = en_dq_dl;
wire [1:0] #(TRISTATE_DELAY) en_dqs_d0 = en_dqs_dl;
wire [1:0] #(DQ_OUT_DELAY_H) en_dq_d1=en_dq_d0;
wire [1:0] #(DQ_OUT_DELAY_H) en_dqs_d1=en_dqs_d0;
wire [1:0] #(DQ_OUT_DELAY_H) en_dq_d2=en_dq_d1;
wire [1:0] #(DQ_OUT_DELAY_H) en_dqs_d2=en_dqs_d1;
wire [1:0] #(DQ_IN_DELAY_H) en_dq_d3=en_dq_d2;
wire [1:0] #(DQ_IN_DELAY_H) en_dqs_d3=en_dqs_d2;
wire [1:0] #(DQ_OUT_DELAY_H) en_dq_d4=en_dq_d3;
wire [1:0] #(DQ_OUT_DELAY_H) en_dqs_d4=en_dqs_d3;
wire [1:0] #(DQ_OUT_DELAY_H) en_dq_d5=en_dq_d4;
wire [1:0] #(DQ_OUT_DELAY_H) en_dqs_d5=en_dqs_d4;
wire [1:0] #(DQ_IN_DELAY_H) en_dq_d6=en_dq_d5;
wire [1:0] #(DQ_IN_DELAY_H) en_dqs_d6=en_dqs_d5;
wire [1:0] #(DQ_IN_DELAY_H) en_dq_d7=en_dq_d6;
wire [1:0] #(DQ_IN_DELAY_H) en_dqs_d7=en_dqs_d6;
// wire [1:0] en_dq_out=en_dq_d2;
// wire [1:0] en_dqs_out=en_dqs_d2;
wire [1:0] en_dq_out=en_dq_d3;
wire [1:0] en_dqs_out=en_dqs_d3;
// wire [1:0] en_dq_in= ~en_dq_d0 & ~en_dq_d1 & ~en_dq_d2 & ~en_dq_d3 & ~en_dq_d4;
// wire [1:0] en_dqs_in=~en_dqs_d0 & ~en_dqs_d1 & ~en_dqs_d2 & ~en_dqs_d3 & ~en_dqs_d4;
wire [1:0] en_dq_in= ~en_dq_d0 & ~en_dq_d1 & ~en_dq_d2 & ~en_dq_d3 & ~en_dq_d4 & ~en_dq_d5 & ~en_dq_d6 & ~en_dq_d7;
wire [1:0] en_dqs_in=~en_dqs_d0 & ~en_dqs_d1 & ~en_dqs_d2 & ~en_dqs_d3 & ~en_dqs_d4 & ~en_dqs_d5 & ~en_dqs_d6 & ~en_dqs_d7;
/* Instance template for module dly_16 */
dly_16 #(
......@@ -86,37 +147,134 @@ module ddr3_wrap#(
.rst (~SDRST),
.dly (TRISTATE_DELAY_CLK),
.din ({~dqs_tri,~dq_tri}),
.dout ({en_dqs_d,en_dq_d})
.dout ({en_dqs_dl,en_dq_dl})
);
wire [15:0] SDD_H1;
wire SDDML_H1;
wire SDDMU_H1;
wire DQSL_H1;
wire NDQSL_H1;
wire DQSU_H1;
wire NDQSU_H1;
wire [15:0] SDD_H2;
wire SDDML_H2;
wire SDDMU_H2;
wire DQSL_H2;
wire NDQSL_H2;
wire DQSU_H2;
wire NDQSU_H2;
wire [15:0] SDD_H3;
wire SDDML_H3;
wire SDDMU_H3;
wire DQSL_H3;
wire NDQSL_H3;
wire DQSU_H3;
wire NDQSU_H3;
wire [15:0] SDD_D;
wire SDDML_D;
wire SDDMU_D;
wire DQSL_D; // LDQS I/O pad
wire NDQSL_D; // ~LDQS I/O pad
wire DQSU_D; // UDQS I/O pad
wire NDQSU_D; //,
wire DQSL_D;
wire NDQSL_D;
wire DQSU_D;
wire NDQSU_D;
wire [15:0] SDD_DH1;
wire DQSL_DH1;
wire NDQSL_DH1;
wire DQSU_DH1;
wire NDQSU_DH1;
wire [15:0] SDD_DH2;
wire DQSL_DH2;
wire NDQSL_DH2;
wire DQSU_DH2;
wire NDQSU_DH2;
wire [15:0] SDD_DH3;
wire DQSL_DH3;
wire NDQSL_DH3;
wire DQSU_DH3;
wire NDQSU_DH3;
assign #(DQ_OUT_DELAY_H) SDD_H1[ 7:0] = SDD[7:0];
assign #(DQ_OUT_DELAY_H) SDD_H1[15:8] = SDD[15:8];
assign #(DQ_OUT_DELAY_H) SDD_H2[ 7:0] = SDD_H1[7:0];
assign #(DQ_OUT_DELAY_H) SDD_H2[15:8] = SDD_H1[15:8];
assign #(DQ_OUT_DELAY_H) SDD_H3[ 7:0] = SDD_H2[7:0];
assign #(DQ_OUT_DELAY_H) SDD_H3[15:8] = SDD_H2[15:8];
assign #(DQ_OUT_DELAY_H) SDD_D[ 7:0] = en_dq_out[0]? SDD_H3[7:0]: 8'bz;
assign #(DQ_OUT_DELAY_H) SDD_D[15:8] = en_dq_out[1]? SDD_H3[15:8]:8'bz;
assign #(DQ_OUT_DELAY_H) SDDML_H1 = SDDML;
assign #(DQ_OUT_DELAY_H) SDDMU_H1 = SDDMU;
assign #(DQ_OUT_DELAY_H) SDDML_H2 = SDDML_H1;
assign #(DQ_OUT_DELAY_H) SDDMU_H2 = SDDMU_H1;
assign #(DQ_OUT_DELAY_H) SDDML_H3 = SDDML_H2;
assign #(DQ_OUT_DELAY_H) SDDMU_H3 = SDDMU_H2;
assign #(DQ_OUT_DELAY_H) SDDML_D = en_dq_out[0]? SDDML_H3: 1'bz;
assign #(DQ_OUT_DELAY_H) SDDMU_D = en_dq_out[1]? SDDMU_H3: 1'bz;
assign #(DQ_IN_DELAY_H) SDD_DH1 [ 7:0] = SDD_D[7:0];
assign #(DQ_IN_DELAY_H) SDD_DH1 [15:8] = SDD_D[15:8];
assign #(DQ_IN_DELAY_H) SDD_DH2 [ 7:0] = SDD_DH1[7:0];
assign #(DQ_IN_DELAY_H) SDD_DH2 [15:8] = SDD_DH1[15:8];
assign #(DQ_IN_DELAY_H) SDD_DH3 [ 7:0] = SDD_DH2[7:0];
assign #(DQ_IN_DELAY_H) SDD_DH3 [15:8] = SDD_DH2[15:8];
assign #(DQ_IN_DELAY_H) SDD [ 7:0] = en_dq_in[0]? SDD_DH3[7:0]:8'bz;
assign #(DQ_IN_DELAY_H) SDD [15:8] = en_dq_in[1]? SDD_DH3[15:8]:8'bz;
assign #(DQS_OUT_DELAY_H) DQSL_H1 = DQSL;
assign #(DQS_OUT_DELAY_H) NDQSL_H1 = NDQSL;
assign #(DQS_OUT_DELAY_H) DQSU_H1 = DQSU;
assign #(DQS_OUT_DELAY_H) NDQSU_H1 = NDQSU;
assign #(DQ_OUT_DELAY) SDD_D[ 7:0] = en_dq[0]? SDD[7:0]: 8'bz;
assign #(DQ_OUT_DELAY) SDD_D[15:8] = en_dq[1]? SDD[15:8]:8'bz;
assign #(DQS_OUT_DELAY_H) DQSL_H2 = DQSL_H1;
assign #(DQS_OUT_DELAY_H) NDQSL_H2 = NDQSL_H1;
assign #(DQS_OUT_DELAY_H) DQSU_H2 = DQSU_H1;
assign #(DQS_OUT_DELAY_H) NDQSU_H2 = NDQSU_H1;
assign #(DQ_OUT_DELAY) SDDML_D = en_dq[0]? SDDML: 1'bz;
assign #(DQ_OUT_DELAY) SDDMU_D = en_dq[1]? SDDMU: 1'bz;
assign #(DQS_OUT_DELAY_H) DQSL_H3 = DQSL_H2;
assign #(DQS_OUT_DELAY_H) NDQSL_H3 = NDQSL_H2;
assign #(DQS_OUT_DELAY_H) DQSU_H3 = DQSU_H2;
assign #(DQS_OUT_DELAY_H) NDQSU_H3 = NDQSU_H2;
assign #(DQS_OUT_DELAY_H) DQSL_D = en_dqs_out[0]? DQSL_H3: 1'bz;
assign #(DQS_OUT_DELAY_H) NDQSL_D = en_dqs_out[0]? NDQSL_H3: 1'bz;
assign #(DQS_OUT_DELAY_H) DQSU_D = en_dqs_out[1]? DQSU_H3: 1'bz;
assign #(DQS_OUT_DELAY_H) NDQSU_D = en_dqs_out[1]? NDQSU_H3: 1'bz;
assign #(DQ_IN_DELAY) SDD [ 7:0] = en_dq[0]? 8'bz : SDD_D[7:0];
assign #(DQ_IN_DELAY) SDD [15:8] = en_dq[1]? 8'bz : SDD_D[15:8];
assign #(DQS_IN_DELAY_H) DQSL_DH1 = DQSL_D;
assign #(DQS_IN_DELAY_H) NDQSL_DH1 = NDQSL_D;
assign #(DQS_IN_DELAY_H) DQSU_DH1 = DQSU_D;
assign #(DQS_IN_DELAY_H) NDQSU_DH1 = NDQSU_D;
assign #(DQS_OUT_DELAY) DQSL_D = en_dqs[0]? DQSL: 1'bz;
assign #(DQS_OUT_DELAY) NDQSL_D = en_dqs[0]? NDQSL: 1'bz;
assign #(DQS_OUT_DELAY) DQSU_D = en_dqs[1]? DQSU: 1'bz;
assign #(DQS_OUT_DELAY) NDQSU_D = en_dqs[1]? NDQSU: 1'bz;
assign #(DQS_IN_DELAY_H) DQSL_DH2 = DQSL_DH1;
assign #(DQS_IN_DELAY_H) NDQSL_DH2 = NDQSL_DH1;
assign #(DQS_IN_DELAY_H) DQSU_DH2 = DQSU_DH1;
assign #(DQS_IN_DELAY_H) NDQSU_DH2 = NDQSU_DH1;
assign #(DQS_IN_DELAY) DQSL = en_dqs[0]? 1'bz : DQSL_D;
assign #(DQS_IN_DELAY) NDQSL = en_dqs[0]? 1'bz : NDQSL_D;
assign #(DQS_IN_DELAY) DQSU = en_dqs[1]? 1'bz : DQSU_D;
assign #(DQS_IN_DELAY) NDQSU = en_dqs[1]? 1'bz : NDQSU_D;
assign #(DQS_IN_DELAY_H) DQSL_DH3 = DQSL_DH2;
assign #(DQS_IN_DELAY_H) NDQSL_DH3 = NDQSL_DH2;
assign #(DQS_IN_DELAY_H) DQSU_DH3 = DQSU_DH2;
assign #(DQS_IN_DELAY_H) NDQSU_DH3 = NDQSU_DH2;
assign #(DQS_IN_DELAY_H) DQSL = en_dqs_in[0]? DQSL_DH3: 1'bz;
assign #(DQS_IN_DELAY_H) NDQSL = en_dqs_in[0]? NDQSL_DH3: 1'bz;
assign #(DQS_IN_DELAY_H) DQSU = en_dqs_in[1]? DQSU_DH3: 1'bz;
assign #(DQS_IN_DELAY_H) NDQSU = en_dqs_in[1]? NDQSU_DH3: 1'bz;
ddr3 #(
.TCK_MIN (2500),
......
x393_testbench01.sav
View file @ c8b52324
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Tue Apr 21 03:43:52 2015
[*] Wed Apr 22 06:13:24 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150420194727213.lxt"
[dumpfile_mtime] "Tue Apr 21 01:52:16 2015"
[dumpfile_size] 252456387
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150422000228091.lxt"
[dumpfile_mtime] "Wed Apr 22 06:07:54 2015"
[dumpfile_size] 272771001
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 41533420
[size] 1823 1173
[pos] 2065 0
*-13.595797 41566328 157271875 157546875 43667500 43655000 44285000 44297500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 42303990
[size] 1823 1180
[pos] 2071 0
*-12.659416 42321294 42321138 42326138 42321258 42321294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.x393_i.
......@@ -40,17 +40,22 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_in_dly_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iserdes_mem_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iserdes_mem_i.iserdes_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 347
[signals_width] 369
[sst_width] 373
[signals_width] 336
[sst_expanded] 1
[sst_vpaned_height] 635
[sst_vpaned_height] 636
@c00200
-top_simulation
@28
......@@ -1011,8 +1016,6 @@ x393_testbench01.x393_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
@28
x393_testbench01.ddr3_i.en_dq[1:0]
x393_testbench01.ddr3_i.en_dqs[1:0]
x393_testbench01.ddr3_i.SDCLK_D[0]
@22
x393_testbench01.ddr3_i.SDA_D[14:0]
......@@ -1021,23 +1024,56 @@ x393_testbench01.ddr3_i.SDBA_D[2:0]
x393_testbench01.ddr3_i.SDRAS_D[0]
x393_testbench01.ddr3_i.SDCAS_D[0]
x393_testbench01.ddr3_i.SDWE_D[0]
x393_testbench01.ddr3_i.DQSL[0]
x393_testbench01.ddr3_i.DQSL_H3[0]
x393_testbench01.ddr3_i.DQSL_D[0]
x393_testbench01.ddr3_i.DQSL_DH1[0]
x393_testbench01.ddr3_i.DQSL_DH2[0]
x393_testbench01.ddr3_i.DQSL_DH3[0]
x393_testbench01.ddr3_i.DQSU_D[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.ddr3_i.SDD_H3[15:0]
x393_testbench01.ddr3_i.SDD_D[15:0]
@29
@28
x393_testbench01.ddr3_i.SDODT_D[0]
@1000200
-DDR3_wrap
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
@22
x393_testbench01.ddr3_i.SDD[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dout[63:0]
@28
x393_testbench01.ddr3_i.en_dq_dl[1:0]
x393_testbench01.ddr3_i.en_dq_d0[1:0]
x393_testbench01.ddr3_i.en_dq_d1[1:0]
x393_testbench01.ddr3_i.en_dq_out[1:0]
x393_testbench01.ddr3_i.en_dq_d3[1:0]
x393_testbench01.ddr3_i.en_dq_in[1:0]
x393_testbench01.ddr3_i.en_dqs_dl[1:0]
x393_testbench01.ddr3_i.en_dqs_out[1:0]
x393_testbench01.ddr3_i.en_dqs_in[1:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsl[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dqsu[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dout[31:0]
@200
-
-
@1000200
-DDR3_wrap
@800200
-dqs0_dq0_out
@28
......@@ -1074,7 +1110,7 @@ x393_testbench01.x393_i.SDD[15:0]
x393_testbench01.x393_i.SDODT[0]
@1000200
-DDR3
@800200
@c00200
-phy_cmd_
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.mclk[0]
......@@ -1153,11 +1189,11 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
-group_end
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@1000200
@1401200
-phy_cmd_
@200
-
@800200
@c00200
-ch0_buf
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0]
......@@ -1189,7 +1225,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.ram_512x64w_1kx32r_i.RAMB36E1_i.ADDRBWRADDR[15:0]
@200
-
@1000200
@1401200
-ch0_buf
@200
-
......@@ -1792,7 +1828,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
-PS_PIO
@c00200
@800200
-LINEAR_CH1
@200
-
......@@ -2248,7 +2284,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
@1401200
@1000200
-LINEAR_CH1
@c00200
-TILED_CH2
......
x393_testbench01.tf
View file @ c8b52324
......@@ -33,14 +33,14 @@
`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
//`define TEST_TILED_WRITE 0
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_TILED_READ 1
//`define TEST_TILED_READ 0
//`define TEST_TILED_WRITE32 0
//`define TEST_TILED_READ32 0
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -721,14 +721,14 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
`ifdef USE_DDR3_WRAP
ddr3_wrap #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.TRISTATE_DELAY_CLK (1), // total 2
.TRISTATE_DELAY_CLK (4'h1), // total 2
.TRISTATE_DELAY (0),
.CLK_DELAY (0),
.CMDA_DELAY (0),
.DQS_IN_DELAY (0),
.DQ_IN_DELAY (0),
.DQS_OUT_DELAY (0),
.DQ_OUT_DELAY (0)
.CLK_DELAY (1550),
.CMDA_DELAY (1550),
.DQS_IN_DELAY (3150),
.DQ_IN_DELAY (1550),
.DQS_OUT_DELAY (1550),
.DQ_OUT_DELAY (1550)
) ddr3_i (
.mclk (WRAP_MCLK), // input
.dq_tri ({WRAP_PHY_DQ_TRI[4],WRAP_PHY_DQ_TRI[0]}), // input[1:0]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment