Commit c8b01721 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

working on infrequent errors when cirbuf rolls over

parent 64e5e516

.project

+11 −11
Original line number Diff line number Diff line
@@ -62,52 +62,52 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160512172954764.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160512120153045.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160513114712446.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160512122847249.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160513115248831.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160512120153045.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160513114712446.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160512120153045.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160513114712446.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -127,7 +127,7 @@ 
		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160512120153045.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160513114712446.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

.settings/com.elphel.vdt.VivadoBitstream.prefs

+1 −1
Original line number Diff line number Diff line
@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true 
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_124_force=true

VivadoBitstream_124_rawfile=x393_hispi

VivadoBitstream_124_rawfile=x393_parallel

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->

eclipse.preferences.version=1

axi/cmprs_afi_mux.v

+13 −3
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), 
    

    reg   [1:0] winner1;           // 2 first level arbitration winners

    reg   [1:0] winner2;           // 2-bit second level arbitration winner

    wire  [1:0] pre_winner2_w;     // 1 cycle ahead of winner2

    

//    reg   [1:0] cur_chn;          // Can it be the same as cur_chn?

    wire  [7:0] fifo_count0_m1 = fifo_count0 - 1;
@@ -290,6 +291,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), 
    assign {fifo_rst3, fifo_rst2, fifo_rst1, fifo_rst0} = reset_pointers;

    assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;

    

    assign pre_winner2_w = (counts_corr1[1 * 9 +: 9] > counts_corr1[0 * 9 +: 9]) ? {1'b1,winner1[1]} : {1'b0,winner1[0]};

    

    assign afi_awaddr =  {chunk_addr,5'b0};

    assign afi_awid =    afi_awid_r; //  {1'b0,wleft[3:2],last_burst_in_frame,cur_chn}; 

    assign afi_awvalid = awvalid[1];
@@ -306,6 +309,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), 
    assign afi_awqos =         4'h0;

    assign afi_wstrb =         8'hff;

    assign afi_wrissuecap1en = 1'b0;

    

    

    

`ifdef DEBUG_RING

    debug_slave #(

        .SHIFT_WIDTH       (64),
@@ -433,11 +439,14 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), 
        // second arbitration level (latency 3 clk)

        if (counts_corr1[1 * 9 +: 9] > counts_corr1[0 * 9 +: 9]) begin

            counts_corr2 <= counts_corr1[1 * 9 +: 9];

            winner2 <=      {1'b1,winner1[1]};

//            winner2 <=      {1'b1,winner1[1]};

        end else begin

            counts_corr2 <= counts_corr1[0 * 9 +: 9];

            winner2 <=      {1'b0,winner1[0]};

//            winner2 <=      {1'b0,winner1[0]};

        end

        

        winner2 <=  pre_winner2_w;

        

        //ready_to_start need_to_bother

        //done_burst

        if      (!en)          busy <= 0;
@@ -549,7 +558,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop), 
        .en                  (en),                  // input

        .reset_pointers      (reset_pointers),      // input[3:0] 

        .pre_busy_w          (pre_busy_w),          // input

        .winner_channel      (winner2),             // input[1:0] 

        .pre_winner_channel  (pre_winner2_w),       // input[1:0] 

//        .winner_channel      (winner2),             // input[1:0] 

        .need_to_bother      (need_to_bother),      // input

//        .chunk_inc           (chunk_inc),           // input[2:0]

        .chunk_inc_want_m1   (pre_chunk_inc_m1),    // input[1:0] Want to increment by this (0..3) + 1, if not roll over

axi/cmprs_afi_mux_ptr.v

+31 −7
Original line number Diff line number Diff line
@@ -44,7 +44,8 @@ module cmprs_afi_mux_ptr( 
    input                         en,                 // 0 - resets, 0->1 resets all pointers. While reset allows write response

    input                  [ 3:0] reset_pointers,     // per-channel - reset pointers

    input                         pre_busy_w,         // combinatorial signal - one before busy[0] (depends on ptr_resetting)

    input                  [ 1:0] winner_channel,     // channel that won arbitration for AXI access, valid @ pre_busy_w

    input                  [ 1:0] pre_winner_channel, // channel that won arbitration for AXI access, valid 1 cycle ahead of @ pre_busy_w

//    input                  [ 1:0] winner_channel,     // channel that won arbitration for AXI access, valid @ pre_busy_w

    input                         need_to_bother,     // wants to start access if address and data FIFO permit

    input                   [1:0] chunk_inc_want_m1,  // how much to increment chunk pointer (0..3) +1 - valid with busy[0] (w/o rollover)
@@ -81,26 +82,34 @@ module cmprs_afi_mux_ptr( 
    

    reg   [3:0] chunks_to_rollover_r;   // [3] >=8 

    wire  [3:0] chunks_to_rollover_m1;

    wire  [3:0] pre_chunks_to_rollover_m1;

    reg         max_inc_ram_we;

    reg   [1:0] max_inc_ram_wa;

    wire        rollover_w; // this cycle causes rollover - valid at pre_busy_w

    reg         rollover_r; // this cycle causes rollover - valid at busy[0] and late

    reg  [ 1:0] winner_channel;     // channel that won arbitration for AXI access, valid @ pre_busy_w

    

    

    wire        ptr_ram_wa = ptr_ram[ptr_wa]; // SuppressThisWarning VEditor debug - just to view 

//    wire  [2:0] max_wlen_di;   // data to write to max_inc_ram and bypass register

    reg   [2:0] max_wlen_r;    // memory registered output

    reg   [2:0] max_wlen_same; // used to bypass max_inc_ram for the same channel

//    reg         use_same_max_wlen; // valid @ pre_busy_w

    reg   [1:0] last_max_written; // channel for which max_wlen was written to RAM

    

    assign ptr_resetting = resetting[0];

    assign sa_len_ra= {busy[1],ptr_wa[1:0]};

    

    assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],

                           reset_rq_pri[3] | reset_rq_pri[1]};

//    assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);

    assign ptr_ram_di= (resetting[1] ||rollover_r)  ? 27'b0 : chunk_ptr_inc ;



    assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];

    assign start_resetting_w = en && !busy[0] && !resetting[0] && (|reset_rq) && !need_to_bother;

    

//    assign max_inc = max_inc_ram[winner_channel];

    assign max_wlen = max_inc_ram[winner_channel]; // valid @pre_busy_w

///    assign max_wlen = max_inc_ram[winner_channel]; // valid @pre_busy_w

//    assign max_wlen = (last_max_written == winner_channel) ? (max_inc_ram_we? max_wlen_di: max_wlen_same) :max_wlen_r ; // valid @pre_busy_w

    assign max_wlen = (last_max_written == winner_channel) ? max_wlen_same :max_wlen_r ; // valid @pre_busy_w

    

//chunk_inc_want_m1

    assign pre_chunk_inc_m1 = (max_wlen[1:0] >= chunk_inc_want_m1)? chunk_inc_want_m1 : max_wlen[1:0];
@@ -108,8 +117,15 @@ module cmprs_afi_mux_ptr( 
    

    assign chunks_to_rollover = sa_len_ram[sa_len_ra] -  ptr_ram_di;

    assign chunks_to_rollover_m1 = chunks_to_rollover_r -1;

       

//    assign max_wlen_di = (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};    

    // 1 cycle ahead of chunks_to_rollover_m1

    assign pre_chunks_to_rollover_m1 =  {|chunks_to_rollover[26:3],chunks_to_rollover[2:0]} - 1;  

    always @ (posedge hclk) begin

        winner_channel <= pre_winner_channel;

        max_wlen_r <= max_inc_ram[pre_winner_channel]; // valid @pre_busy_w

        if       (!en)                 last_max_written <= 0;

        else if  (ptr_we & ~ptr_wa[2]) last_max_written <= ptr_wa[1:0];

        

        en_d <= en;

        // ===== calculate and rollover channel addresses ====

        // clear (during "resetting" or update 8x27 RAM that holds chunk pointers for the current burst and currenty frame
@@ -162,7 +178,15 @@ module cmprs_afi_mux_ptr( 
        max_inc_ram_we <= ptr_we & ~ptr_wa[2];

        max_inc_ram_wa <= ptr_wa[1:0];

        

        if (max_inc_ram_we) max_inc_ram[max_inc_ram_wa] <= (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};

        // set 1 cycle earlier 

        if (ptr_we & ~ptr_wa[2]) max_wlen_same <= (|pre_chunks_to_rollover_m1[3:2])?3'h7:{1'b0,pre_chunks_to_rollover_m1[1:0]};

        

        if (max_inc_ram_we) begin

            max_inc_ram[max_inc_ram_wa] <= max_wlen_same; // max_wlen_di; //  (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};

//            max_wlen_same <=               max_wlen_di;

        end

        

        

    end

endmodule

fpga_version.vh

+3 −1
Original line number Diff line number Diff line
@@ -32,7 +32,9 @@ 
 * with at least one of the Free Software programs.

 *******************************************************************************/

 

        parameter FPGA_VERSION =          32'h0393008a;    // HiSPI sensor (14 MPix)

//        parameter FPGA_VERSION =          32'h0393008c;      // hispi, all met, 83.55%

        parameter FPGA_VERSION =          32'h0393008b;    // parallel, all met, 82.06%

//        parameter FPGA_VERSION =          32'h0393008a;    // HiSPI sensor (14 MPix) no timing errors

//        parameter FPGA_VERSION =          32'h03930089;    // Auto-synchronizing i2c sequencers with the command ones

//        parameter FPGA_VERSION =          32'h03930088;    // Fixing circbuf rollover pointers bug (only one path violated)

//      parameter FPGA_VERSION =          32'h03930087;    // Fixed default 90% quantization table