created test fixture with macro define switch between parallel and HiSPi sensors

fpga_version.vh

-    parameter FPGA_VERSION =          32'h03930042;
+    parameter FPGA_VERSION =          32'h03930050;
\ No newline at end of file

simulation_modules/par12_hispi_psp4l.v

@@ -107,11 +107,21 @@ module  par12_hispi_psp4l#(
 
     // generate output clock (normally multiplier first, but in simulation there will be less calculations if division is first)
     wire         oclk;
-    wire         int_clk;
+//    wire         int_clk;
     wire         next_line_oclk; 
     wire         next_frame_oclk ;
     reg          orst_r = 1;
     wire         orst = rst || orst_r;
+    simul_clk_mult_div #(
+        .MULTIPLIER(CLOCK_MPY),
+        .DIVISOR(CLOCK_DIV),
+        .SKIP_FIRST(5)
+    ) simul_clk_div_mult_i (
+        .clk_in(pclk), // input
+        .en(1'b1), // input
+        .clk_out(oclk) // output
+    );
+/*   
     simul_clk_mult #(
         .MULTIPLIER(CLOCK_MPY)
     ) simul_clk_mult_i (
@@ -127,7 +137,7 @@ module  par12_hispi_psp4l#(
         .en      (1'b1), // input
         .clk_out (oclk) // output
     );
-    
+*/    
     pulse_cross_clock #(
         .EXTRA_DLY(0)
     ) pulse_cross_clock_sof_sol_i (

simulation_modules/sim_clk_div.v

@@ -29,7 +29,7 @@ module  sim_clk_div#(
     );
     integer cntr = 0;
     reg clk_out_r = 0;
-    assign clk_out = clk_out_r;
+    assign clk_out = (DIVISOR == 1) ? clk_in: clk_out_r;
     always @(clk_in) if (en) begin
         if (cntr == 0) begin
             cntr = DIVISOR - 1;

simulation_modules/simul_clk_div_mult.v

+/*******************************************************************************
+ * Module: simul_clk_div_mult
+ * Date:2015-10-12  
+ * Author: andrey     
+ * Description: Simulation clock rational multiplier
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * simul_clk_div_mult.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_clk_div_mult.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_clk_div_mult#(
+        parameter MULTIPLIER = 3,
+        parameter DIVISOR =    5,
+        parameter SKIP_FIRST = 5
+    ) (
+        input      clk_in,
+        input      en,
+        output     clk_out
+);
+    wire clk_int;
+    generate
+        if (DIVISOR > 1) 
+            sim_clk_div #(
+                .DIVISOR   (DIVISOR)
+            ) sim_clk_div_i (
+                .clk_in   (clk_in), // input
+                .en       (en), // input
+                .clk_out  (clk_int) // output
+            );
+        else
+            assign clk_int = clk_in;
+    endgenerate
+    generate
+        if (MULTIPLIER > 1) 
+            simul_clk_mult #(
+                .MULTIPLIER (MULTIPLIER),
+                .SKIP_FIRST (SKIP_FIRST)
+            ) simul_clk_mult_i (
+                .clk_in  (clk_int), // input
+                .en      (en), // input
+                .clk_out (clk_out) // output
+            );
+        else
+            assign clk_out = clk_int;
+    endgenerate
+endmodule
+

simulation_modules/simul_clk_mult.v

@@ -34,7 +34,7 @@ module  simul_clk_mult#(
     integer num_period = 0;
     reg en1 = 0;
     reg clk_out_r = 0;
-    assign clk_out = clk_out_r;
+    assign clk_out = (MULTIPLIER == 1)? clk_in: clk_out_r;
     always @ (posedge clk_in) begin
         phase = $realtime;
         if (num_period >= SKIP_FIRST) begin

simulation_modules/simul_clk_mult_div.v

+/*******************************************************************************
+ * Module: simul_clk_mult_div
+ * Date:2015-10-12  
+ * Author: andrey     
+ * Description: Simulation clock rational multiplier
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * simul_clk_mult_div.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_clk_mult_div.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_clk_mult_div#(
+        parameter MULTIPLIER = 3,
+        parameter DIVISOR =    5,
+        parameter SKIP_FIRST = 5
+    ) (
+        input      clk_in,
+        input      en,
+        output     clk_out
+);
+    wire clk_int;
+    generate
+        if (MULTIPLIER > 1) 
+            simul_clk_mult #(
+                .MULTIPLIER (MULTIPLIER),
+                .SKIP_FIRST (SKIP_FIRST)
+            ) simul_clk_mult_i (
+                .clk_in  (clk_in), // input
+                .en      (en), // input
+                .clk_out (clk_int) // output
+            );
+        else
+            assign clk_int = clk_in;
+    endgenerate
+    generate
+        if (DIVISOR > 1) 
+            sim_clk_div #(
+                .DIVISOR   (DIVISOR)
+            ) sim_clk_div_i (
+                .clk_in   (clk_in), // input
+                .en       (en), // input
+                .clk_out  (clk_out) // output
+            );
+        else
+            assign clk_out = clk_int;
+    endgenerate
+endmodule
+

system_defines.vh

@@ -2,6 +2,8 @@
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES
   `define PRELOAD_BRAMS
+  // if HISPI is not defined, parallel sensor interface is used for all channels
+//  `define HISPI
 //  `define DEBUG_RING 1
   `define MEMBRIDGE_DEBUG_WRITE 1
 // Enviroment-dependent options