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MCLT window generators - with(128:1)/without(4:1) multiplier, ROM data 

and Python ROM data generators
parent 04653ceb
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dsp/create_wnd_mul_rom.py 0 → 100755
View file @ c78b5a40
#!/usr/bin/env python
# -*- coding: utf-8 -*-
from __future__ import print_function
from __future__ import division
# Copyright (C) 2017, Elphel.inc.
# Helper module create AHCI registers type/default data
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
'''
Calculate ROM for half-sine 1d window for lapped transform.
Created for 8x8 (16x16 overlapped) with 128:1 super resolution, so instead of :
sin(1*pi/32), sin(3*pi/32),..., sin(15*pi/32) for each of the rows and columns
there are:
sin(1*pi/2048), sin(2*pi/2048),..., sin(32*pi/2048) for each of the rows and columns
that requires 1024x18bits ROM. no need to have sin(0*pi/2048) as it is 0
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2017, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import sys
import math
import os
import datetime
mclt_wnd_rom_path= '../includes/mclt_wnd_mul.vh'
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
return {'data':data,'data_p':data_p}
def print_params(data,
out_file_name,
comment=""): # text to add to the file header
with open(out_file_name,"w") as out_file:
print ("// Created with "+sys.argv[0], file=out_file)
if comment:
print (comment, file=out_file)
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
# if (include_parity):
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def create_wnd_1d (N=1024, bits=18): # N=32, bits=18, all data is positive
rom = []
sin = []
for i in range(N):
rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count
return rom
print_params(
create_with_parity(create_wnd_1d (N=1024, bits=18), 18, False),
os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),
"// MCLT 1d 16 count window with 128:1 super resolution data")
print ("MCLT 1d 16 count window with 128:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))
dsp/create_wnd_sres4_rom.py 0 → 100755
View file @ c78b5a40
#!/usr/bin/env python
# -*- coding: utf-8 -*-
from __future__ import print_function
from __future__ import division
# Copyright (C) 2017, Elphel.inc.
# Helper module create AHCI registers type/default data
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
'''
Calculate ROM for half-sine 2d window for lapped transform.
Only one quadrant is stored.
created for 8x8 (16x16 overlapped) with 4:1 super resolution, so instead of :
sin(1*pi/32), sin(3*pi/32),..., sin(15*pi/32) for each of the rows and columns
there are:
sin(1*pi/64), sin(2*pi/64),..., sin(32*pi/64) for each of the rows and columns
that requires 32x32x18bits ROM. no need to have sin(0*pi/64) as it is 0
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2017, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import sys
import math
import os
import datetime
mclt_wnd_rom_path= '../includes/mclt_wnd_sres4.vh'
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
return {'data':data,'data_p':data_p}
def print_params(data,
out_file_name,
comment=""): # text to add to the file header
with open(out_file_name,"w") as out_file:
print ("// Created with "+sys.argv[0], file=out_file)
if comment:
print (comment, file=out_file)
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
# if (include_parity):
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def create_wnd_2d (N=32, bits=18): # N=32, bits=18, all data is positive
rom = []
sin = []
for i in range(N):
sin.append(math.sin(math.pi*(i+1)/(2*N)))
for i in range(N):
for j in range(N):
rom.append(int(round(sin[i] * sin[j] * ((1 << bits) - 1)))) # loosing 1 count
return rom
print_params(
create_with_parity(create_wnd_2d (N=32, bits=18), 18, False),
os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),
"// MCLT 16x16 window with 4:1 super resolution data")
print ("MCLT 16x16 window with 4:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))
dsp/mclt_wnd_mul.v 0 → 100644
View file @ c78b5a40
/*!
* <b>Module:</b> mclt_wnd_mul
* @file mclt_wnd_mul.v
* @date 2017-12-06
* @author eyesis
*
* @brief MCLT window with MPY (128:1 superresolution)
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* mclt_wnd_mul.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt_wnd_mul.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// Latency = 5
module mclt_wnd_mul#(
parameter SHIFT_WIDTH = 8, // bits in shift (1 bit - integer, 7 bits - fractional
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter OUT_WIDTH = 18 // bits in window value (positive)
)(
input clk, //!< system clock, posedge
input en, //!< re (both re and ren - just for power)
input [3:0] x_in, //!< tile pixel X
input [3:0] y_in, //!< tile pixel Y
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y
output [OUT_WIDTH - 1 : 0] wnd_out
);
wire [COORD_WIDTH - 1 : 0] x_full;
wire [COORD_WIDTH - 1 : 0] y_full;
wire x_zero;
wire y_zero;
reg [1:0] zero; // x_zero | y_zero;
reg [2:0] regen; //
wire [OUT_WIDTH - 1 : 0] wnd_out_x;
wire [OUT_WIDTH - 1 : 0] wnd_out_y;
reg [2*OUT_WIDTH - 1 : 0] wnd_out_r;
assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 1: OUT_WIDTH];
always @ (posedge clk) begin
regen <= {regen[1:0],en};
zero <= {1'b0, x_zero | y_zero};
wnd_out_r <= wnd_out_x * wnd_out_y;
end
mclt_full_shift #(
.COORD_WIDTH(COORD_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH)
) mclt_full_shift_x_i (
.clk (clk), // input
.coord (x_in), // input[3:0]
.shift (x_shft), // input[2:0] signed
.coord_out (x_full), // output[4:0] reg
.zero (x_zero) // output reg
);
mclt_full_shift #(
.COORD_WIDTH(COORD_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH)
) mclt_full_shift_y_i (
.clk (clk), // input
.coord (y_in), // input[3:0]
.shift (y_shft), // input[2:0] signed
.coord_out (y_full), // output[4:0] reg
.zero (y_zero) // output reg
);
ram18tpr_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4)
`ifdef PRELOAD_BRAMS
`include "mclt_wnd_mul.vh"
`endif
) i_wnd_rom (
.clk_a (clk), // input
.addr_a (x_full), // input[9:0]
.en_a (regen[1]), // input
.regen_a (regen[2]), // input
.we_a (1'b0), // input
.rrst_a (1'b0), // input
.regrst_a (zero[1]), // input
.data_out_a(wnd_out_x), // output[17:0]
.data_in_a (18'b0), // input[17:0]
.clk_b (clk), // input
.addr_b (y_full), // input[9:0]
.en_b (regen[1]), // input
.regen_b (regen[2]), // input
.we_b (1'b0), // input
.rrst_b (1'b0), // input
.regrst_b (zero[1]), // input
.data_out_b(wnd_out_y), // output[17:0]
.data_in_b (18'b0) // input[17:0]
);
endmodule
dsp/mclt_wnd_sres4.v 0 → 100644
View file @ c78b5a40
/*!
* <b>Module:</b> mclt_wnd_sres4
* @file mclt_wnd_sres4.v
* @date 2017-12-06
* @author eyesis
*
* @brief MCLT window w/o MPY (4:1 superresolution)
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* mclt_wnd_sres4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt_wnd_sres4.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// Latency = 4
module mclt_wnd_sres4#(
parameter SHIFT_WIDTH = 3, // bits in shift (1 bit - integer, 2 bits - fractional
parameter COORD_WIDTH = 5, // bits in full coordinate 10/2 for 18K RAM
parameter OUT_WIDTH = 18 // bits in window value (positive)
)(
input clk, //!< system clock, posedge
input en, //!< re (both re and ren - just for power)
input [3:0] x_in, //!< tile pixel X
input [3:0] y_in, //!< tile pixel Y
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y
output [OUT_WIDTH - 1 : 0] wnd_out
);
wire [COORD_WIDTH - 1 : 0] x_full;
wire [COORD_WIDTH - 1 : 0] y_full;
wire x_zero;
wire y_zero;
reg [1:0] zero; // x_zero | y_zero;
reg [2:0] regen; //
always @ (posedge clk) begin
regen <= {regen[1:0],en};
zero <= {1'b0, x_zero | y_zero};
end
mclt_full_shift #(
.COORD_WIDTH(COORD_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH)
) mclt_full_shift_x_i (
.clk (clk), // input
.coord (x_in), // input[3:0]
.shift (x_shft), // input[2:0] signed
.coord_out (x_full), // output[4:0] reg
.zero (x_zero) // output reg
);
mclt_full_shift #(
.COORD_WIDTH(COORD_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH)
) mclt_full_shift_y_i (
.clk (clk), // input
.coord (y_in), // input[3:0]
.shift (y_shft), // input[2:0] signed
.coord_out (y_full), // output[4:0] reg
.zero (y_zero) // output reg
);
ram18pr_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(4),
.LOG2WIDTH_RD(4),
.DUMMY(0)
`ifdef PRELOAD_BRAMS
`include "mclt_wnd_sres4.vh"
`endif
) i_wnd_rom (
.rclk (clk), // input
.raddr ({y_full,x_full}), // input[9:0]
.ren (regen[1]), // input
.regen (regen[2]), // input
.rrst (1'b0), // input
.regrst (zero[1]), // input
.data_out (wnd_out), // output[17:0]
.wclk (1'b0), // input
.waddr (10'b0), // input[9:0]
.we (1'b0), // input
.web (4'hf), // input[3:0]
.data_in (18'b0) // input[17:0]
);
endmodule
includes/mclt_wnd_mul.vh 0 → 100644
View file @ c78b5a40
// Created with ./create_wnd_mul_rom.py
// MCLT 1d 16 count window with 128:1 super resolution data
, .INIT_00 (256'h1921178F15FD146B12D911470FB50E230C910AFF096D07DB064804B603240192)
, .INIT_01 (256'h323F30AD2F1B2D8A2BF82A6628D4274325B1241F228D20FB1F691DD71C451AB3)
, .INIT_02 (256'h4B5449C3483246A14510437F41ED405C3ECB3D393BA83A17388536F4356233D0)
, .INIT_03 (256'h645F62CE613E5FAE5E1D5C8D5AFC596C57DB564A54BA5329519850074E764CE5)
, .INIT_04 (256'h7D597BCA7A3B78AB771C758D73FD726E70DE6F4E6DBF6C2F6A9F690F677F65EF)
, .INIT_05 (256'h964094B39325919790098E7A8CEC8B5E89CF884186B285248395820680777EE8)
, .INIT_06 (256'hAF10AD84ABF8AA6BA8DFA752A5C5A439A2ACA11E9F919E049C779AE9995C97CE)
, .INIT_07 (256'hC7C6C63BC4B1C326C19BC010BE85BCFABB6FB9E3B858B6CCB540B3B5B229B09D)
, .INIT_08 (256'hE05CDED3DD4BDBC2DA39D8B0D727D59ED415D28BD102CF78CDEECC64CADAC950)
, .INIT_09 (256'hF8D0F749F5C3F43DF2B6F12FEFA8EE21EC9AEB13E98CE804E67CE4F4E36CE1E4)
, .INIT_0A (256'h111D0F990E150C910B0D09890805068004FB037601F1006CFEE7FD61FBDBFA56)
, .INIT_0B (256'h294027BF263E24BD233B21BA20381EB61D341BB21A2F18AD172A15A7142412A0)
, .INIT_0C (256'h41353FB83E393CBB3B3D39BE383F36C0354133C1324230C22F422DC22C412AC1)
, .INIT_0D (256'h58F9577F56045489530D519250164E9A4D1E4BA14A2548A8472B45AE443142B3)
, .INIT_0E (256'h70886F116D996C216AA9693167B9664064C8634E61D5605C5EE25D685BEE5A74)
, .INIT_0F (256'h87DE866A84F68382820E80997F247DAF7C3A7AC5794F77D9766374EC737671FF)
, .INIT_10 (256'h9EF79D879C179AA7993797C6965594E493729201908F8F1C8DAA8C378AC48951)
, .INIT_11 (256'hB5D1B465B2F9B18DB020AEB4AD47ABDAAA6CA8FEA790A622A4B4A345A1D6A067)
, .INIT_12 (256'hCC66CAFFC998C830C6C8C55FC3F6C28DC124BFBBBE51BCE7BB7DBA12B8A7B73C)
, .INIT_13 (256'hE2B5E153DFEFDE8CDD28DBC5DA60D8FCD797D632D4CDD367D201D09BCF34CDCE)
, .INIT_14 (256'hF8BAF75CF5FDF49FF340F1E1F081EF21EDC1EC61EB00E99FE83EE6DCE57AE418)
, .INIT_15 (256'h0E700D170BBE0A64090A07B0065504FA039F024300E8FF8BFE2FFCD2FB75FA18)
, .INIT_16 (256'h23D62282212E1FD91E841D2F1BDA1A84192E17D71680152913D2127A11220FC9)
, .INIT_17 (256'h38E73798364934FA33AB325B310B2FBA2E692D182BC62A74292227D0267D2529)
, .INIT_18 (256'h4DA04C574B0E49C4487A473045E5449A434F420340B73F6A3E1E3CD03B833A35)
, .INIT_19 (256'h61FE60BB5F785E345CF05BAB5A66592157DB5695554E540752C0517950314EE9)
, .INIT_1A (256'h75FF74C17384724671086FC96E8A6D4A6C0A6ACA698A6849670765C664846341)
, .INIT_1B (256'h899E8867872F85F784BF8387824E81147FDB7EA07D667C2B7AF079B47878773B)
, .INIT_1C (256'h9CD99BA89A779945981496E195AF947B9348921490E08FAB8E768D418C0B8AD4)
, .INIT_1D (256'hAFACAE82AD58AC2DAB01A9D6A8A9A77DA650A522A3F4A2C6A197A0689F399E09)
, .INIT_1E (256'hC216C0F3BFCFBEABBD86BC61BB3BBA15B8EFB7C8B6A1B579B451B328B200B0D6)
, .INIT_1F (256'hD413D2F7D1DAD0BCCF9ECE80CD61CC42CB22CA02C8E2C7C1C6A0C57EC45CC339)
, .INIT_20 (256'hE5A0E48BE375E25EE148E030DF19DE00DCE8DBCFDAB5D99BD881D766D64BD52F)
, .INIT_21 (256'hF6BBF5ADF49EF38FF27FF16FF05FEF4EEE3CED2AEC18EB05E9F2E8DEE7CAE6B5)
, .INIT_22 (256'h0761065A0553044B0343023A01310027FF1DFE12FD07FBFCFAF0F9E3F8D6F7C9)
, .INIT_23 (256'h178F169015901490138F128E118C108A0F870E840D810C7C0B780A73096D0867)
, .INIT_24 (256'h2743264C2554245B23622268216E20741F791E7D1D811C851B881A8A198D188E)
, .INIT_25 (256'h367B358B349B33AA32B931C730D52FE22EEF2DFB2D072C122B1D2A282931283B)
, .INIT_26 (256'h4534444C4364427B419240A83FBE3ED33DE83CFC3C103B233A3539483859376B)
, .INIT_27 (256'h536C528C51AC50CB4FEA4F094E264D444C604B7D4A9849B448CE47E84702461B)
, .INIT_28 (256'h612060495F715E995DC05CE65C0C5B325A57597B589F57C356E55608552A544B)
, .INIT_29 (256'h6E506D816CB16BE16B106A3F696E689B67C966F66622654E647963A462CE61F7)
, .INIT_2A (256'h7AF77A31796A78A277DA77117648757F74B473EA731E7253718670B96FEC6F1E)
, .INIT_2B (256'h87158658859984DA841B835B829A81D9811880557F937ED07E0C7D477C837BBD)
, .INIT_2C (256'h92A891F3913E90888FD18F1A8E628DA98CF18C378B7D8AC28A07894C889087D3)
, .INIT_2D (256'h9DAE9D029C559BA89AFA9A4C999D98ED983D978D96DB962A957794C49411935D)
, .INIT_2E (256'hA826A782A6DFA63AA595A4F0A44AA3A3A2FCA254A1ACA103A05A9FB09F059E5A)
, .INIT_2F (256'hB20DB172B0D8B03CAFA0AF04AE67ADC9AD2BAC8DABEDAB4DAAADAA0CA96AA8C8)
, .INIT_30 (256'hBB62BAD1BA3FB9ADB91AB887B7F3B75EB6C9B634B59EB507B470B3D8B33FB2A6)
, .INIT_31 (256'hC423C39BC313C28AC201C177C0ECC061BFD5BF48BEBBBE2EBDA0BD11BC82BBF2)
, .INIT_32 (256'hCC50CBD2CB53CAD3CA53C9D2C951C8CFC84CC7C9C746C6C1C63CC5B7C531C4AA)
, .INIT_33 (256'hD3E7D372D2FDD286D210D198D120D0A8D02FCFB5CF3ACEC0CE44CDC8CD4BCCCE)
, .INIT_34 (256'hDAE7DA7CDA0FD9A3D935D8C7D859D7EAD77AD70AD699D627D5B5D543D4CFD45C)
, .INIT_35 (256'hE14FE0EDE08AE027DFC3DF5FDEFADE94DE2EDDC7DD60DCF8DC8FDC26DBBCDB52)
, .INIT_36 (256'hE71DE6C5E66CE612E5B8E55DE502E4A6E449E3ECE38EE330E2D1E271E211E1B0)
, .INIT_37 (256'hEC52EC03EBB4EB64EB13EAC2EA70EA1EE9CBE977E923E8CEE879E823E7CCE775)
, .INIT_38 (256'hF0ECF0A7F061F01BEFD4EF8CEF44EEFCEEB2EE68EE1EEDD3ED87ED3BECEEECA0)
, .INIT_39 (256'hF4EAF4AEF472F436F3F9F3BBF37DF33EF2FEF2BEF27DF23CF1FAF1B7F174F130)
, .INIT_3A (256'hF84CF81AF7E8F7B5F782F74EF719F6E4F6AEF678F641F609F5D1F598F55EF524)
, .INIT_3B (256'hFB11FAE9FAC1FA98FA6EFA44FA19F9EEF9C2F995F968F93AF90CF8DCF8ADF87C)
, .INIT_3C (256'hFD39FD1BFCFCFCDDFCBDFC9DFC7CFC5BFC38FC16FBF2FBCEFBA9FB84FB5EFB38)
, .INIT_3D (256'hFEC3FEAFFE9BFE85FE6FFE59FE42FE2AFE12FDF9FDDFFDC5FDAAFD8FFD73FD56)
, .INIT_3E (256'hFFB0FFA6FF9BFF90FF84FF77FF6AFF5CFF4DFF3EFF2FFF1EFF0DFEFCFEE9FED7)
, .INIT_3F (256'hFFFFFFFFFFFEFFFCFFFAFFF7FFF4FFF0FFEBFFE6FFE0FFDAFFD3FFCBFFC3FFBA)
, .INITP_01 (256'h5555555555555555555555555555555555555555555555000000000000000000)
, .INITP_02 (256'hAAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555)
, .INITP_03 (256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA)
, .INITP_04 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAA)
, .INITP_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INITP_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INITP_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
includes/mclt_wnd_sres4.vh 0 → 100644
View file @ c78b5a40
// Created with ./create_wnd_sres4_rom.py
// MCLT 16x16 window with 4:1 super resolution data
, .INIT_00 (256'h238721BE1FE01DEE1BEA19D517AF157C133A10ED0E960C3509CD075F04ED0277)
, .INIT_01 (256'h323F322F320131B4314830BD30152F4F2E6C2D6C2C502B1929C7285B26D7253B)
, .INIT_02 (256'h46F943673FAC3BCA37C3339A2F502AEA266921D01D23186313950EBA09D704ED)
, .INIT_03 (256'h645F644063E363486271615C600C5E815CBB5ABC588556175374509E4D964A5E)
, .INIT_04 (256'h6A3E64E75F525981537A4D3F46D4403E3980329E2B9E24821D50160C0EBA075F)
, .INIT_05 (256'h96409612958794A0935D91C08FC88D788AD087D3848380E07CEE78AF74256F54)
, .INIT_06 (256'h8D4386297EBC77016EFD66B45E2C556A4C73434D39FE308A26F91D50139509CD)
, .INIT_07 (256'hC7C6C788C6CFC59CC3EFC1C9BF2BBC18B891B497B02FAB5AA61BA0759A6D9405)
, .INIT_08 (256'hAFF0A7179DD894378A3B7FEA754A6A615F3753D2483A3C75308A248218630C35)
, .INIT_09 (256'hF8D0F883F79DF61EF408F15BEE19EA44E5DFE0ECDB6ED569CEE1C7D9C055B85B)
, .INIT_0A (256'hD230C79FBC93B112A52598D18C1F7F1771C16424564A483A39FE2B9E1D230E96)
, .INIT_0B (256'h294028E427D22608238A20581C7317E012A00CB60627FEF6F728EEC1E5C7DC3F)
, .INIT_0C (256'hF3EFE7ACDAD9CD80BFA8B15AA29F937F84047438642453D2434D329E21D010ED)
, .INIT_0D (256'h58F9588F5750553D52584EA34A1F44CF3EB737DA303D27E51ED615160AABFF9C)
, .INIT_0E (256'h15170729F899E96FD9B6C976B8B9A78B95F6840471C15F374C7339802669133A)
, .INIT_0F (256'h87DE876585FB83A080567C1F76FE70F66A0A623E5998501D45D33AC02EEB225B)
, .INIT_10 (256'h3595260515BF04CEF33DE115CE62BB31A78B937F7F176A61556A403E2AEA157C)
, .INIT_11 (256'hB5D1B54AB3B5B113AD67A8B2A2F69C39947D8BC8821E77876C085FA8526F4466)
, .INIT_12 (256'h5554442B323A1F8D0C2EF829E38CCE62B8B9A29F8C1F754A5E2C46D42F5017AF)
, .INIT_13 (256'hE2B5E221E062DD7CD96FD43ECDECC67EBDF7B45DA9B69E08915B83B7752365AA)
, .INIT_14 (256'h744061894DF8399924790EA5F829E115C976B15A98D17FEA66B44D3F339A19D5)
, .INIT_15 (256'h0E700DCE0BE708BE0453FEAAF7C5EFAAE65EDBE5D047C38BB5B8A6D796F18611)
, .INIT_16 (256'h92467E0D68E852E53C1124790C2EF33DD9B6BFA8A5258A3B6EFD537A37C31BEA)
, .INIT_17 (256'h38E73837362A32BF2DF827DA206817A50D990248F5BAE7F7D906C8F2B7C4A587)
, .INIT_18 (256'hAF5599A682FA6B5F52E539991F8D04CEE96FCD80B1129437770159813BCA1DEE)
, .INIT_19 (256'h61FE61425F0E5B6456464FB747BA3E563390276E19F70B36FB31E9F4D788C3FA)
, .INIT_1A (256'hCB59B4419C1D82FA68E84DF8323A15BFF899DAD9BC939DD87EBC5F523FAC1FE0)
, .INIT_1B (256'h899E88D5867D82967D2276266DA563A4582B4B3F3CE92D321C2309C7F629E155)
, .INIT_1C (256'hE642CDD0B44199A67E0D6189442B26050729E7ACC79FA717862964E7436721BE)
, .INIT_1D (256'hAFACAED8AC5DA83BA2769B119210877A7B546DA65E794DD63BC828581394FD88)
, .INIT_1E (256'hFFFFE642CB59AF5592467440555435951517F3EFD230AFF08D436A3E46F92387)
, .INIT_1F (256'hD413D334D097CC3DC629BE60B4E5A9C09CF58E8E7E946D0F5A0C45952FB81881)
, .INIT_20 (256'h1881FD88E155C3FAA587861165AA4466225BFF9CDC3FB85B94056F544A5E253B)
, .INIT_21 (256'hF6BBF5D1F314EE85E827DFFED60FCA61BCFAADE29D248AC976DD616B4A82322F)
, .INIT_22 (256'h2FB81394F629D788B7C496F17523526F2EEB0AABE5C7C0559A6D74254D9626D7)
, .INIT_23 (256'h178F169B13C00EFE085AFFD6F57AE94ADB4ECB90BA18A6F292287BC963E24A82)
, .INIT_24 (256'h4595285809C7E9F4C8F2A6D783B75FA83AC01516EEC1C7D9A07578AF509E285B)
, .INIT_25 (256'h367B357E32852D9426AD1DD513110667F7E0E784D55DC177ABDE94A07BC9616B)
, .INIT_26 (256'h5A0C3BC81C23FB31D906B5B8915B6C0845D31ED6F728CEE1A61B7CEE537429C7)
, .INIT_27 (256'h536C52654F524A35431039E82EC221A7129C01ADEEE3DA4AC3EEABDE922876DD)
, .INIT_28 (256'h6D0F4DD62D320B36E7F7C38B9E087787501D27E5FEF6D569AB5A80E056172B19)
, .INIT_29 (256'h6E506D416A1564CE5D6F53FD487E3AF82B7419FC069AF15ADA4AC177A6F28AC9)
, .INIT_2A (256'h7E945E793CE919F7F5BAD047A9B6821E5998303D0627DB6EB02F848358852C50)
, .INIT_2B (256'h871585FF82BC7D4F75BB6C056033524B425730611C73069AEEE3D55DBA189D24)
, .INIT_2C (256'h8E8E6DA64B3F276E0248DBE5B45D8BC8623E37DA0CB6E0ECB49787D35ABC2D6C)
, .INIT_2D (256'h9DAE9C91993993AA8BE581F175D26792573844CE306119FC01ADE784CB90ADE2)
, .INIT_2E (256'h9CF57B54582B33900D99E65EBDF7947D6A0A3EB712A0E5DFB8918AD05CBB2E6C)
, .INIT_2F (256'hB20DB0E9AD7EA7CF9FDF95B289507ABF6A09573842572B74129CF7E0DB4EBCFA)
, .INIT_30 (256'hA9C0877A63A43E5617A5EFAAC67E9C3970F644CF17E0EA44BC188D785E812F4F)
, .INIT_31 (256'hC423C2FABF7FB9B4B19DA73E9A9F8BC77ABF6792524B3AF821A70667E94ACA61)
, .INIT_32 (256'hB4E592106DA547BA2068F7C5CDECA2F676FE4A1F1C73EE19BF2B8FC8600C3015)
, .INIT_33 (256'hD3E7D2B9CF2FC94CC113B689A9B59A9F895075D26033487E2EC21311F57AD60F)
, .INIT_34 (256'hBE609B1176264FB727DAFEAAD43EA8B27C1F4EA32058F15BC1C991C0615C30BD)
, .INIT_35 (256'hE14FE01DDC86D68FCE39C38AB689A73E95B281F16C0553FD39E81DD5FFD6DFFE)
, .INIT_36 (256'hC629A2767D2256462DF80453D96FAD6780565258238AF408C3EF935D62713148)
, .INIT_37 (256'hEC52EB1CE77CE173D906CE39C113B19D9FDF8BE575BB5D6F431026AD085AE827)
, .INIT_38 (256'hCC3DA83B82965B6432BF08BEDD7CB11383A0553D2608F61EC59C94A0634831B4)
, .INIT_39 (256'hF4EAF3B1F009E9F3E173D68FC94CB9B4A7CF93AA7D4F64CE4A352D940EFEEE85)
, .INIT_3A (256'hD097AC5D867D5F0E362A0BE7E062B3B585FB575027D2F79DC6CF958763E33201)
, .INIT_3B (256'hFB11F9D6F628F009E77CDC86CF2FBF7FAD7E993982BC6A154F52328513C0F314)
, .INIT_3C (256'hD334AED888D5614238370DCEE221B54A8765588F28E4F883C78896126440322F)
, .INIT_3D (256'hFEC3FD88F9D6F3B1EB1CE01DD2B9C2FAB0E99C9185FF6D415265357E169BF5D1)
, .INIT_3E (256'hD413AFAC899E61FE38E70E70E2B5B5D187DE58F92940F8D0C7C69640645F323F)
, .INIT_3F (256'hFFFFFEC3FB11F4EAEC52E14FD3E7C423B20D9DAE87156E50536C367B178FF6BB)
, .INITP_01 (256'h5555555550000000555555540000000055555400000000000000000000000000)
, .INITP_02 (256'hAAAAA55555540000AA9555555550000055555555554000005555555555000000)
, .INITP_03 (256'hAAAAAAAA55554000AAAAAAA955554000AAAAAAA555550000AAAAAA5555550000)
, .INITP_04 (256'hFFFFFAAAA9555000FFFFAAAAA9555000FFEAAAAAA5555000AAAAAAAA95554000)
, .INITP_05 (256'hFFFFFFEAAA955400FFFFFFEAAA955400FFFFFFAAAA555400FFFFFEAAAA555000)
, .INITP_06 (256'hFFFFFFFEAAA55400FFFFFFFAAA955400FFFFFFFAAA955400FFFFFFFAAA955400)
, .INITP_07 (256'hFFFFFFFEAAA55400FFFFFFFEAAA55400FFFFFFFEAAA55400FFFFFFFEAAA55400)
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