Matched simulation (agianst 353) through all the compression modules (c71eec74) · Commits · Elphel / x393

compressor_jp/cmprs_buf_average.v

+6 −3

Original line number	Diff line number	Diff line
		@@ -221,10 +221,13 @@ module cmprs_buf_average#(
		if (!frame_en) wpage <= 0;
		else if (yc_pre_first_out) wpage <= wpage + 1; // will start from 1, not 0. Maybe changed to there strobe - end of writing

		if (!frame_en \|\| pre_first_in) first <= 0;
		else if (ccv_out_start) first <= pre_first_mb;

		if (ccv_out_start) begin
		rpage[1:0] <= wpage[1:0];
		four_blocks_rd <= four_blocks;
		first <= pre_first_mb;
		// first <= pre_first_mb;
		last <= pre_last_mb;
		color_enable <= pre_color_enable; // valid with address
		end

compressor_jp/jp_channel.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -772,7 +772,7 @@ module jp_channel#(
		// focus sharp module calculates amount of high-frequency components and optioanlly overlays/replaces actual image
		wire [12:0] focus_do; // output[12:0] reg pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
		wire focus_ds; // output reg data out strobe (one ahead of the start of dv)

		// TODO: Verify focus_sharp393: quantizer output (with strobes) is now 2 cycles later than in 353 (relative to xdct out). Seems to be OK.
		focus_sharp393 focus_sharp393_i (
		.clk (xclk), // input - pixel clock
		.clk2x (xclk2x), // input 2x pixel clock

compressor_jp/quantizer393.v

+32 −16

Original line number	Diff line number	Diff line
		@@ -46,9 +46,9 @@ module quantizer393(
		input first_in, // first block in (valid @ start)
		output reg first_out, // valid @ ds
		input [12:0] di, // [11:0] pixel data in (signed)
		output [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
		output reg dv, // data out valid
		output reg ds, // data out strobe (one ahead of the start of dv)
		output reg [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
		output dv, // data out valid
		output ds, // data out strobe (one ahead of the start of dv)
		output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
		input dcc_en, // enable dcc (sync to beginning of a new frame)
		input [ 2:0] hfc_sel, // hight frequency components select [2:0] (includes components with both numbers >=hfc_sel
		@@ -87,7 +87,10 @@ module quantizer393(
		// for fifo for ctype, dc
		wire ctype;
		wire [ 8:0] dc;
		wire next_dv;
		// wire next_dv;
		// reg [ 2:0] last_dv; // last dv cycle (will turn of unless new ds)
		reg [ 2:0] ds_r;
		reg [ 3:0] ren;

		reg [ 5:0] start;
		wire dcc_stb;
		@@ -123,7 +126,8 @@ module quantizer393(
		assign start_a = start[5];
		assign start_z = start[4];
		assign dcc_stb = start[2];

		assign ds = ds_r[2];
		assign dv = ren[3];
		always @ (posedge clk) begin
		if (stb) block_mem_ram[block_mem_wa[2:0]] <= {coring_num[2:0],tsi[2:0], ctypei, dci[8:0]};

		@@ -141,13 +145,13 @@ module quantizer393(
		assign dcc_data[15:0]=sel_satnum?
		{n255[7:0],n000[7:0]}:
		{dcc_first \|\| (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
		assign do[12:0]=zigzag_q[12:0];
		// assign do[12:0]=zigzag_q[12:0];
		assign qmul[27:0]=tdor[15:0]*d3[11:0];

		assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
		assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical

		assign next_dv=en && (ds \|\| (dv && (zra[5:0]!=6'h00)));
		// assign next_dv=en && (ds \|\| (dv && (zra[5:0]!=6'h00)));
		always @ (posedge clk) begin
		d1[12:0] <= di[12:0];
		//inv_sign
		@@ -187,10 +191,22 @@ module quantizer393(

		if (start_out) rpage <= wpage;

		// last_dv <= {last_dv[1:0], en && (zra[5:0] == 6'h3f)};

		if (start_out) zra[5:0] <= 6'b0;
		else if (zra[5:0]!=6'h3f) zra[5:0] <= zra[5:0]+1; // conserving energy
		ds <= start_out;
		dv <= next_dv;
		// else if (zra[5:0]!=6'h3f) zra[5:0] <= zra[5:0]+1; // conserving energy
		else if (ren[0]) zra[5:0] <= zra[5:0]+1; // conserving energy

		ds_r <= {ds_r[1:0], en && start_out};

		if (!en) ren[0] <= 0;
		else if (start_out) ren[0] <= 1;
		else if ((zra[5:0] == 6'h3f)) ren[0] <= 0;

		if (!en) ren[3:1] <= 0;
		else ren[3:1] <= ren [2:0];

		if (ren[2]) do[12:0] <= zigzag_q[12:0];

		if (start_a) first_interm <= first_in;
		if (start_out) first_out <=first_interm;
		@@ -305,15 +321,15 @@ module quantizer393(
		);

		ram18_var_w_var_r #(
		.REGISTERS (0),
		.REGISTERS (1),
		.LOG2WIDTH_WR (4),
		.LOG2WIDTH_RD (4),
		.DUMMY (0)
		) i_zigzagbuf (
		.rclk (clk), // input
		.raddr ({3'b0,rpage,zra[5:0]}), // input[9:0]
		.ren (next_dv), // input
		.regen (1'b1), // input
		.ren (ren[0]), // input
		.regen (ren[1]), // input
		.data_out (zigzag_q[15:0]), // output[15:0]
		.wclk (clk), // input
		.waddr ({3'b0,wpage,zwa[5:0]}), // input[9:0]

compressor_jp/stuffer393.v

+4 −4

Original line number	Diff line number	Diff line
		@@ -158,20 +158,20 @@ module stuffer393 (
		// ts_cycles <= {ts_cycles[6:0],ts_rstb};
		ts_cycles <= {ts_cycles[5:0],ts_rstb};
		if (ts_cycles[0]) sec_r[ 7: 0] <= ts_dout;
		else if (time_size_out) sec_r[ 7: 0] <= sec_r[23:16];
		else if (start_sizeout) sec_r[ 7: 0] <= size_count[ 7:0];
		else if (time_size_out) sec_r[ 7: 0] <= sec_r[23:16];

		if (ts_cycles[1]) sec_r[15: 8] <= ts_dout;
		else if (time_size_out) sec_r[15: 8] <= sec_r[31:24];
		else if (start_sizeout) sec_r[15: 8] <= size_count[15:8];
		else if (time_size_out) sec_r[15: 8] <= sec_r[31:24];

		if (ts_cycles[2]) sec_r[23:16] <= ts_dout;
		else if (time_size_out) sec_r[23:16] <= usec_r[ 7: 0];
		else if (start_sizeout) sec_r[23:16] <= size_count[23:16];
		else if (time_size_out) sec_r[23:16] <= usec_r[ 7: 0];

		if (ts_cycles[3]) sec_r[31:24] <= ts_dout;
		else if (time_size_out) sec_r[31:24] <= usec_r[15: 8];
		else if (start_sizeout) sec_r[31:24] <= 8'hff;
		else if (time_size_out) sec_r[31:24] <= usec_r[15: 8];

		if (ts_cycles[4]) usec_r[ 7: 0] <= ts_dout;
		else if (time_out) usec_r[ 7: 0] <= {4'h0, usec_r[19:16]};

timing/camsync393.v

+5 −2

Original line number	Diff line number	Diff line
		@@ -568,8 +568,11 @@ module camsync393 #(
		sr_rcv_first[31:0] <={sr_rcv_first[30:0],sr_rcv_second[31]};
		sr_rcv_second[31:0] <={sr_rcv_second[30:0],trigger_condition_filtered};
		end

		rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) \|\| (rcv_done_rq && rcv_run));
		// Why was it local_got_pclk? Also, it is a multi-bit vector
		// rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) \|\| (rcv_done_rq && rcv_run));
		// TODO: think of disabling receiving sync if sesnor is not ready yet (not done with a previous frame)
		rcv_done_rq <= start_en && ((ts_external_pclk && (rcv_run && !rcv_run_d)) \|\| (rcv_done_rq && rcv_run));
		//
		rcv_done_rq_d <= rcv_done_rq;
		rcv_done <= rcv_done_rq_d && !rcv_done_rq;

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