Commit a5d68f54 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

continue debugging

parent 22f7ceaa

compressor_jp/focus_sharp393.v

+3 −0
Original line number Diff line number Diff line
@@ -325,6 +325,9 @@ module focus_sharp393( 
        .LOG2WIDTH_WR (4),

        .LOG2WIDTH_RD (4),

        .DUMMY        (0)

`ifdef PRELOAD_BRAMS

    `include "includes/focus_filt.dat.vh"

`endif

    ) i_focus_dct_tab (

        .rclk         (clk), // input

        .raddr        ({filt_sel[3:0],tba[2:0],tba[5:3]}), // input[9:0]

compressor_jp/huffman393.v

+3 −0
Original line number Diff line number Diff line
@@ -389,6 +389,9 @@ module huffman393 ( 
        .LOG2WIDTH_WR(4),

        .LOG2WIDTH_RD(5),

        .DUMMY(0)

`ifdef PRELOAD_BRAMS

    `include "includes/huffman.dat.vh"

`endif

    ) i_htab (

        .rclk(xclk2x), // input

        .raddr(haddr[8:0]), // input[8:0]

compressor_jp/jp_channel.v

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ module jp_channel#( 
        parameter CMPRS_FORMAT=               2,

        parameter CMPRS_COLOR_SATURATION=     3,

        parameter CMPRS_CORING_MODE=          4,

        parameter CMPRS_TABLES=               6, // 6..7

        parameter CMPRS_TABLES=               6, // 6(data)..7(address)



        parameter FRAME_HEIGHT_BITS=          16, // Maximal frame height 

        parameter LAST_FRAME_BITS=            16, // number of bits in frame counter (before rolls over)

compressor_jp/quantizer393.v

+6 −0
Original line number Diff line number Diff line
@@ -267,6 +267,9 @@ module quantizer393( 
        .LOG2WIDTH_WR (4),

        .LOG2WIDTH_RD (4),

        .DUMMY        (0)

`ifdef PRELOAD_BRAMS

    `include "includes/quantization_100.dat.vh"

`endif

    ) i_quant_table (

        .rclk         (clk),                          // input

        .raddr        ({tba[9:6],tba[2:0],tba[5:3]}), // input[8:0]
@@ -285,6 +288,9 @@ module quantizer393( 
        .LOG2WIDTH_WR (4),

        .LOG2WIDTH_RD (2),

        .DUMMY        (0)

`ifdef PRELOAD_BRAMS

    `include "includes/coring.dat.vh"

`endif

    ) i_coring_table (

        .rclk         (clk), // input

        .raddr        ({tbac[3:0],qmulr[11:4]}), // input[10:0]

compressor_jp/xdct393.v

+8 −8
Original line number Diff line number Diff line
@@ -379,10 +379,10 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t 
         addsub4a_comp	<= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;

    end



    assign p1a_all = addsub1a_comp * memory1a; //[15:0]; // TODO: Check - memory is [16:0] !

    assign p2a_all = addsub2a_comp * memory2a; //[15:0];

    assign p3a_all = addsub3a_comp * memory3a; //[15:0];

    assign p4a_all = addsub4a_comp * memory4a; //[15:0];

    assign p1a_all = addsub1a_comp * memory1a[15:0]; // [16] is sign!

    assign p2a_all = addsub2a_comp * memory2a[15:0];

    assign p3a_all = addsub3a_comp * memory3a[15:0];

    assign p4a_all = addsub4a_comp * memory4a[15:0];





    always @ (posedge nclk)
@@ -612,10 +612,10 @@ module dct393_stage2 ( 
//    assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];

//   assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];



    assign p1b_all = addsub1b_comp * memory1a; // AF2015: TODO: Check - memory is 16:0

    assign p2b_all = addsub2b_comp * memory2a;

    assign p3b_all = addsub3b_comp * memory3a;

    assign p4b_all = addsub4b_comp * memory4a;

    assign p1b_all = addsub1b_comp * memory1a[15:0]; // MSB [16] is sign!

    assign p2b_all = addsub2b_comp * memory2a[15:0];

    assign p3b_all = addsub3b_comp * memory3a[15:0];

    assign p4b_all = addsub4b_comp * memory4a[15:0];





    always @ (posedge clk) begin