Working on MCLT version for Bayer data, exploiting symmetry of DTT of

checker board data (half zeros)

dsp/create_bayer_fold_rom.py

+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+from __future__ import print_function
+from __future__ import division
+# Copyright (C) 2017, Elphel.inc.
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+'''
+Calculate ROM for MCLT fold indices with Bahyer pattern on the input
+Source tile is expanded to accommodate small lateral chromatic aberrations (up to +/- 3 pixels for 22x22 pixel tiles):
+A0..A2 - sample column in folded 8x8 tile
+A3..A5 - sample row in folded 8x8 tile
+A6 -     variant, folding to the same 8x8 sample (with checker board there are only 2 of 4)
+A7 -     invert checker: 0 - pixels on main diagonal, 1 - zeros on main diagonal
+A8..A9 - source tile size: 0 - 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (all < 512)
+D0..D4 - pixel column in 16x16 tile (for window)
+D5..D7 - pixel row in 16x16 tile (for window)
+D8..D15 - pixel offset in full tile, MSB omitted - it will be restored from bits 7 and 15
+D16 - negate for mode 0 (CC)
+D17 - negate for mode 1 (SC) other modes (CS and SS are reversed SC and CC, negated for inverted checker
+'''
+  
+__author__ = "Andrey Filippov"
+__copyright__ = "Copyright 2017, Elphel, Inc."
+__license__ = "GPL"
+__version__ = "3.0+"
+__maintainer__ = "Andrey Filippov"
+__email__ = "andrey@elphel.com"
+__status__ = "Development"
+import sys
+import math
+import os
+import datetime
+mclt_wnd_rom_path=  '../includes/mclt_bayer_fold_rom.vh'
+
+def create_with_parity (init_data,   # numeric data (may be less than full array
+                        num_bits,    # number of bits in item, valid:  1,2,4,8,9,16,18,32,36,64,72
+                        full_bram):  # true if ramb36, false - ramb18
+    d = num_bits
+    num_bits8 = 1;
+    while d > 1:
+        d >>= 1
+        num_bits8 <<= 1
+    bsize = (0x4000,0x8000)[full_bram]
+    bdata = [0  for i in range(bsize)]
+    sb = 0
+    for item in init_data:
+        for bt in range (num_bits8):
+            bdata[sb+bt] = (item >> bt) & 1;
+        sb += num_bits8
+    data = []
+    for i in range (len(bdata)//256):
+        d = 0;
+        for b in range(255, -1,-1):
+            d = (d<<1) +  bdata[256*i+b]
+        data.append(d)
+    data_p = []
+    num_bits_p = num_bits8 >> 3
+    sb = 0
+    print ("num_bits=",num_bits)
+    print ("num_bits8=",num_bits8)
+    print ("num_bits_p=",num_bits_p)
+    if num_bits_p:    
+        pbsize = bsize >> 3    
+        pbdata = [0  for i in range(pbsize)]
+        for item in init_data:
+            for bt in range (num_bits_p):
+                pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
+            sb += num_bits_p
+        for i in range (len(pbdata)//256):
+            d = 0;
+            for b in range(255, -1,-1):
+                d = (d<<1) +  pbdata[256*i+b]
+            data_p.append(d)
+    return {'data':data,'data_p':data_p}
+
+
+def print_params(data,
+                 out_file_name,
+                 comment=""): # text to add to the file header
+    with open(out_file_name,"w") as out_file:
+        print ("// Created with "+sys.argv[0], file=out_file)
+        if comment:
+            print (comment, file=out_file)
+        for i, v in enumerate(data['data']):
+            if v:
+                print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
+    #    if (include_parity):
+        for i, v in enumerate(data['data_p']):
+            if v:
+                print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
+
+def  get_fold_indices(x, n = 8):
+    n1 = n >> 1
+#    ind = [[0,0,0,0,0,0],[0,0,0,0,0,0]]# new int[2][6];
+    ind = [[0,0,0,0],[0,0,0,0]]# new int[2][6];
+    if x < n1:
+        ind[0][0] = n + n1 - x - 1 #// C: -cR, S: +cR
+        ind[0][1] = n1     + x
+        ind[0][2] = -1
+        ind[0][3] =  1
+#        ind[0][4] = n1     - x -1
+#        ind[0][5] =  -1 #// c - window derivative over shift is negative
+        
+        ind[1][0] = n + n1 + x#;     // C: -d,  S: -d
+        ind[1][1] = n1     - x - 1
+        ind[1][2] = -1
+        ind[1][3] = -1
+
+#        ind[1][4] = n1     + x;
+#        ind[1][5] =  -1# // d - window derivative over shift is negative
+    else:
+        x-=n1;
+        ind[0][0] =          x#     // C: +a, S: +a
+        ind[0][1] =          x
+        ind[0][2] =  1
+        ind[0][3] =  1
+#        ind[0][4] =  n     - x - 1
+#        ind[0][5] =  1#   // a - window derivative over shift is positive
+        
+        ind[1][0] = n      - x - 1# // C: -bR, S: +bR
+        ind[1][1] = n      - x - 1
+        ind[1][2] = -1
+        ind[1][3] =  1
+#        ind[1][4] =          x
+#        ind[1][5] =  1#   // b - window derivative over shift is positive
+    return ind
+
+def create_fold(n = 8): # n - DCT and window size
+#    fold_index = (n*n) * [4*[0]] # new int[n*n][4];
+    fold_index = []
+    for _ in range(n*n):
+        fold_index.append([0,0,0,0])
+#    fold_k =     new double[4][n*n][4];
+#    fold_signs = 4 * [(n*n) * [4*[0]]] 
+#    fold_signs = 4 * [(n*n) * [4*[0]]]
+    fold_signs = []
+    for _ in range(4):
+        a = []
+        for _a in range(n*n):
+            a.append([0,0,0,0])
+        fold_signs.append(a)            
+    print("fold_signs=",fold_signs) 
+    
+    vert_ind = [0,0]        # new int[2];
+    vert_k =   [[0,0],[0,0]] #new double[2][2];
+    hor_ind =  [0,0]        # new int[2];
+    hor_k =    [[0,0],[0,0]] #new double[2][2];
+    #int [][] fi;
+    n2 = 2 * n;
+    for i in range(n): # (int i = 0; i < n; i++ ){
+        fi = get_fold_indices(i,n)
+        vert_ind[0] = fi[0][0];
+        vert_ind[1] = fi[1][0];
+        vert_k[0][0] =   fi[0][2]# * hwindow[fi[0][1]]; // use cosine sign
+        vert_k[0][1] =   fi[1][2]# * hwindow[fi[1][1]]; // use cosine sign
+        vert_k[1][0] =   fi[0][3]# * hwindow[fi[0][1]]; // use sine sign
+        vert_k[1][1] =   fi[1][3]# * hwindow[fi[1][1]]; // use sine sign
+        for j in range(n): # (int j = 0; j < n; j++ ){
+            fi = get_fold_indices(j,n)
+            hor_ind[0] = fi[0][0];
+            hor_ind[1] = fi[1][0];
+            hor_k[0][0] =   fi[0][2]# * hwindow[fi[0][1]]; // use cosine sign
+            hor_k[0][1] =   fi[1][2]# * hwindow[fi[1][1]]; // use cosine sign
+            hor_k[1][0] =   fi[0][3]# * hwindow[fi[0][1]]; // use sine sign
+            hor_k[1][1] =   fi[1][3]# * hwindow[fi[1][1]]; // use sine sign
+            indx = n * i + j
+            for k in range(4): #(int k = 0; k<4;k++) {
+                fold_index[indx][k] = n2 * vert_ind[(k>>1) & 1] + hor_ind[k & 1]
+            for mode in range(4): # (int mode = 0; mode<4; mode++){
+                for k in range(4): #(int k = 0; k<4;k++) {
+                    fold_signs[mode][indx][k]=     vert_k[(mode>>1) &1][(k>>1) & 1] * hor_k[mode &1][k & 1]
+                    #fold_k[mode][indx][k] =     vert_k[(mode>>1) &1][(k>>1) & 1] * hor_k[mode &1][k & 1]; 
+#        for (int i = 0; i < n; i++ ){
+#            fi = get_fold_indices(i,n);
+#            System.out.println(i+"->"+String.format("?[%2d %2d %2d %2d] [%2d %2d %2d %2d] %f %f",
+#                    fi[0][0],fi[0][1],fi[0][2],fi[0][3],
+#                    fi[1][0],fi[1][1],fi[1][2],fi[1][3], hwindow[fi[0][1]], hwindow[fi[1][1]]));
+#        }
+    print("fold_index=",fold_index)
+    print("fold_signs=",fold_signs)
+    for  i in range(n * n): #(int i = 0; i < n*n; i++){
+        print("%3x:   %6x   %6x   %6x   %6x"%(i,fold_index[i][0],fold_index[i][1],fold_index[i][2],fold_index[i][3]))
+        print("   :   %2d   %2d   %2d   %2d"%(fold_signs[0][i][0],  fold_signs[0][i][1], fold_signs[0][i][2], fold_signs[0][i][3]))
+        print("   :   %2d   %2d   %2d   %2d"%(fold_signs[1][i][0],  fold_signs[1][i][1], fold_signs[1][i][2], fold_signs[1][i][3]))
+        print("   :   %2d   %2d   %2d   %2d"%(fold_signs[2][i][0],  fold_signs[2][i][1], fold_signs[2][i][2], fold_signs[2][i][3]))
+        print("   :   %2d   %2d   %2d   %2d"%(fold_signs[3][i][0],  fold_signs[3][i][1], fold_signs[3][i][2], fold_signs[3][i][3]))
+    """
+    fold = (4*n*n)*[0]    
+    for var in range(4):
+        for i in range(n * n):
+            fold[var * 64 + i] = (fold_index[i][var]
+                                  + (((0,1)[fold_signs[0][i][var] < 0]) <<  8) +
+                                  + (((0,1)[fold_signs[1][i][var] < 0]) <<  9) +
+                                  + (((0,1)[fold_signs[2][i][var] < 0]) << 10) +
+                                  + (((0,1)[fold_signs[3][i][var] < 0]) << 11))
+    """
+    fold = (4*2*2*n*n)*[0] # sizes (16-18-20-22) * invert_checker (0,1) * variant(0,1) * index (0..63)
+    for inv_checker in range(2):    
+        for i in range(n * n):
+            addresses=[]
+            signs = []
+            for var4 in range(4):
+                row = (fold_index[i][var4] >> 4) & 0xf
+                col = (fold_index[i][var4] >> 0) & 0xf
+                blank = (row ^ col ^ inv_checker) & 1
+                if not blank:
+                    addresses.append (fold_index[i][var4])
+                    signs.append ([((0,1)[fold_signs[0][i][var4] < 0]),((0,1)[fold_signs[1][i][var4] < 0])])
+            for size_bits, size_val in enumerate ([16,18,20,22]):
+                for var2 in range(2):
+                    row = (addresses[var2] >> 4) & 0xf
+                    col = (addresses[var2] >> 0) & 0xf
+                    full_addr = (row * size_val + col) & 0xff # saving one address bit
+                    fold[(size_bits << 8) + (inv_checker << 7) + (var2 << 6) + i] = (
+                        (addresses[var2]  & 0xff) +
+                        ((full_addr & 0xff) << 8) +
+                        (signs[var2][0] << 16) +
+                        (signs[var2][1] << 17))         
+            
+#      wire                        [7:0] wnd_a_w =   fold_rom_out[7:0];
+#    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
+#    reg          [PIX_ADDR_WIDTH-1:0] pix_a_r;
+#    wire                       [ 1:0] sgn_w =     fold_rom_out[16 +: 2];
+            
+    return fold
+
+'''
+Calculate ROM for MCLT fold indices with Bahyer pattern on the input
+Source tile is expanded to accommodate small lateral chromatic aberrations (up to +/- 3 pixels for 22x22 pixel tiles):
+A0..A2 - sample column in folded 8x8 tile
+A3..A5 - sample row in folded 8x8 tile
+A6 -     variant, folding to the same 8x8 sample (with checker board there are only 2 of 4)
+A7 -     invert checker: 0 - pixels on main diagonal, 1 - zeros on main diagonal
+A8..A9 - source tile size: 0 - 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (all < 512)
+D0..D4 - pixel column in 16x16 tile (for window)
+D5..D7 - pixel row in 16x16 tile (for window)
+D8..D15 - pixel offset in full tile, MSB omitted - it will be restored from bits 7 and 15
+D16 - negate for mode 0 (CC)
+D17 - negate for mode 1 (SC) other modes (CS and SS are reversed SC and CC, negated for inverted checker
+'''
+                        
+print_params(
+    create_with_parity(create_fold (), 18, False),
+    os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),
+    "// MCLT 16x16...22x22 Bayer -> 8x8 fold indices")
+print ("MCLT 16x16...22x22 Bayer -> 8x8 fold indices data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))
+                 

dsp/create_fold_rom.py

@@ -18,9 +18,10 @@ from __future__ import division
 #
 '''
 Calculate ROM for MCLT fold indices:
-A0..A1 - variant, folding to the same 8x8 sample
-A2..A4 - sample column in folded 8x8 tile
-A5..A7 - sample row in folded 8x8 tile
+A0..A2 - sample column in folded 8x8 tile
+A3..A5 - sample row in folded 8x8 tile
+A6..A7 - variant, folding to the same 8x8 sample
+
 D0..D4 - pixel column in 16x16 tile
 D5..D7 - pixel row in 16x16 tile
 D8 -  negate for mode 0 (CC)
@@ -207,9 +208,9 @@ def create_fold(n = 8): # n - DCT and window size
 
 '''
 Calculate ROM for MCLT fold indices:
-A0..A1 - variant, folding to the same 8x8 sample
-A2..A4 - sample column in folded 8x8 tile
-A5..A7 - sample row in folded 8x8 tile
+A0..A2 - sample column in folded 8x8 tile
+A3..A5 - sample row in folded 8x8 tile
+A6..A7 - variant, folding to the same 8x8 sample
 D0..D4 - pixel column in 16x16 tile
 D5..D7 - pixel row in 16x16 tile
 D8 -  negate for mode 0 (CC)

dsp/dsp_ma_preadd.v

@@ -79,7 +79,7 @@ module  dsp_ma_preadd #(
                           2'b01,
                           2'b01};
    initial begin
-      $display("dsp_ma_preadd, using DSP48E1");
+      $display("dsp_ma_preadd, using DSP48E1. FIXME: implement BREG=2 for undef INSTANTIATE_DSP48E1");
    end
                          
     DSP48E1 #(

dsp/mclt16x16.v

@@ -286,8 +286,6 @@ D11 - negate for mode 3 (SS)
     
         .clk_a     (clk),       // input
         .addr_a    ({2'b0,in_cntr[1:0],in_cntr[7:2]}),    // input[9:0] 
-///        .en_a      (in_busy[1]),   // input
-///        .regen_a   (in_busy[2]),   // input
         .en_a      (in_busy[0]),   // input
         .regen_a   (in_busy[1]),   // input
         .we_a      (1'b0),         // input
@@ -303,7 +301,7 @@ D11 - negate for mode 3 (SS)
         .data_in_b (18'b0)         // input[17:0] 
     );
 
-// Latency = 5
+// Latency = 6
     mclt_wnd_mul #(
         .SHIFT_WIDTH (SHIFT_WIDTH),
         .COORD_WIDTH (COORD_WIDTH),
@@ -315,7 +313,8 @@ D11 - negate for mode 3 (SS)
         .x_in      (mpix_a_w[3:0]), // input[3:0] 
         .y_in      (mpix_a_w[7:4]), // input[3:0] 
         .x_shft    (x_shft_r2),     // input[7:0] 
-        .y_shft    (y_shft_r2),     // input[7:0] 
+        .y_shft    (y_shft_r2),     // input[7:0]
+        .zero_in   (1'b0),          // input TODO: covert from mpix_use_r?  
         .wnd_out   (window_w) // output[17:0] valid with in_busy[8]
     );
 
@@ -349,7 +348,6 @@ D11 - negate for mode 3 (SS)
     ) dly_var_first_i (
         .clk  (clk),           // input
         .rst  (rst),           // input
-///        .dly  (4'h8),          // input[3:0] 
         .dly  (4'h9),          // input[3:0] 
         .din  (in_busy[0] && (in_cntr[1:0] == 0)),  // input[0:0] 
         .dout (var_first_d)    // output[0:0] 

dsp/mclt16x16_bayer.v

+/*!
+ * <b>Module:</b> mclt16x16_bayer
+ * @file mclt16x16_bayer.v
+ * @date 2017-12-21  
+ * @author eyesis
+ *     
+ * @brief Generate addresses and windows to fold MCLT Bayer data
+ *
+ * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ *
+ * <b>License </b>
+ *
+ * mclt16x16_bayer.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * mclt16x16_bayer.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+
+module  mclt16x16_bayer#(
+    parameter SHIFT_WIDTH =      7, // bits in shift (7 bits - fractional)
+    parameter PIX_ADDR_WIDTH =   9, // number of pixel address width
+//    parameter EXT_PIX_LATENCY =  2, // external pixel buffer a->d latency
+    parameter COORD_WIDTH =     10, // bits in full coordinate 10 for 18K RAM
+    parameter PIXEL_WIDTH =     16, // input pixel width (unsigned) 
+    parameter WND_WIDTH =       18, // input pixel width (unsigned) 
+    parameter OUT_WIDTH =       25, // bits in dtt output
+    parameter DTT_IN_WIDTH =    25, // bits in DTT input
+    parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)    
+    parameter OUT_RSHIFT =       2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
+    parameter OUT_RSHIFT2 =      0, // overall right shift for the second (vertical) pass
+    parameter DSP_B_WIDTH =     18, // signed, output from sin/cos ROM
+    parameter DSP_A_WIDTH =     25,
+    parameter DSP_P_WIDTH =     48,
+    parameter DEAD_CYCLES =     14  // start next block immedaitely, or with longer pause
+)(
+    input                             clk,          //!< system clock, posedge
+    input                             rst,          //!< sync reset
+    input                             start,        //!< start convertion of the next 256 samples
+    input                       [1:0] tile_size,    //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
+    input                             inv_checker,  //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
+    input                       [7:0] top_left,     //!< index of the 16x16 top left corner
+    input                       [1:0] valid_rows,   //!< 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
+    input           [SHIFT_WIDTH-1:0] x_shft,       //!< tile pixel X fractional shift (valid @ start) 
+    input           [SHIFT_WIDTH-1:0] y_shft,       //!< tile pixel Y fractional shift (valid @ start)
+    
+    output       [PIX_ADDR_WIDTH-1:0] pix_addr,     //!< external pixel buffer address
+    output                            pix_re,       //!< pixel read enable (sync with  mpixel_a)
+    output                            pix_page,     //!< copy pixel page (should be externally combined with first color)
+    input           [PIXEL_WIDTH-1:0] pix_d         //!< pixel data, latency = 2 from pixel address
+);
+    localparam  DTT_OUT_DELAY = 99; // 191; // start output to sin/cos rotator, ~=3/4 of 256
+    localparam  DTT_IN_DELAY =  62; // 69; // wa -ra min = 1
+    reg            [ 1:0] start_r;
+
+    // maybe use small FIFO memory?
+    reg [SHIFT_WIDTH-1:0] x_shft_r;  // registered at start
+    reg [SHIFT_WIDTH-1:0] y_shft_r;  // registered at start
+    reg [SHIFT_WIDTH-1:0] x_shft_r2; // use for the window calculation
+    reg [SHIFT_WIDTH-1:0] y_shft_r2; // use for the window calculation
+    reg [SHIFT_WIDTH-1:0] x_shft_r3; // registered @ start_dtt
+    reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt
+    reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill
+    reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill
+
+//    wire signed       [WND_WIDTH-1:0] window;       //!< msb==0, always positive
+    wire                         [1:0] signs;        //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
+    wire                        [14:0] phases;        //!< other signals
+    
+    wire signed   [WND_WIDTH-1:0] window_w;
+    reg  signed   [WND_WIDTH-1:0] window_r;
+    reg  signed [PIXEL_WIDTH-1:0] pix_d_r;         // registered pixel data (to be absorbed by MPY)
+    
+    reg  signed [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
+    reg  signed              [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
+    // rounding
+    wire signed              [DTT_IN_WIDTH-3:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]
+    `ifdef ROUND
+                 + pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH]
+    `endif
+    ;
+
+    reg  signed [DTT_IN_WIDTH-1:0] data_cc_r;   
+    reg  signed [DTT_IN_WIDTH-1:0] data_sc_r;
+    reg  signed [DTT_IN_WIDTH-1:0] data_sc_r2; // data_sc_r delayed by 1 cycle 
+    reg  signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
+    
+    reg                            mode_mux;   
+    reg                      [6:0] dtt_in_cntr; //
+    reg                            dtt_in_page;
+    wire                     [8:0] dtt_in_wa = {1'b0,dtt_in_page, dtt_in_cntr[0], dtt_in_cntr[6:1]};  
+    wire                           dtt_we = phases[14];
+    
+       
+    wire                    [ 1:0] pix_sgn_d;
+    reg                     [ 1:0] pix_sgn_r;
+    
+    wire                           var_first; // adding subtracting first variant of 4 folds    
+    reg                            var_last;    // next cycle the   data_xx_r will have data  (in_busy[14], ...)
+
+// reading/converting DTT
+    reg                            start_dtt; //  = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256 
+    reg                      [6:0] dtt_r_cntr; //
+    reg                            dtt_r_page;
+    reg                            dtt_r_re;
+    reg                            dtt_r_regen;
+    reg                            dtt_start;
+    
+//    wire                     [1:0] dtt_mode = {dtt_r_cntr[7], dtt_r_cntr[6]}; // TODO: or reverse? 
+    wire                           dtt_mode = dtt_r_cntr[6]; // TODO: or reverse? 
+    wire                     [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};
+    wire signed             [35:0] dtt_r_data_w; // high bits are not used 
+    wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0]; 
+   
+   
+   
+    
+    always @ (posedge clk) begin
+    
+        if (start) begin
+            x_shft_r <= x_shft;
+            y_shft_r <= y_shft;
+        end
+        start_r <= {start_r[0], start};
+        if (start_r[1]) begin      // same latency as mpix_a_w
+            x_shft_r2 <= x_shft_r; // use for the window 
+            y_shft_r2 <= y_shft_r;
+        end
+
+        if (start_dtt) begin 
+            x_shft_r3 <= x_shft_r2; 
+            y_shft_r3 <= y_shft_r2;
+        end
+/*
+        if (dtt_start_first_fill) begin 
+            x_shft_r4 <= x_shft_r3; 
+            y_shft_r4 <= y_shft_r3;
+        end
+*/
+        if (phases[8]) begin
+            pix_d_r <= pix_d;
+            window_r <=   window_w;
+        end
+        if (phases[9])  pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra
+    
+        // pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60
+        if (phases[10]) begin
+            pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};
+//            mpix_use_r  <= mpix_use_d;
+//            var_first_r <= var_first_d;
+            pix_sgn_r <=  pix_sgn_d; 
+        end
+        
+        var_last <= var_first & phases[11];
+       
+        if (phases[11]) begin
+//            data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (mpix_use_r ? (mpix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
+//            data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (mpix_use_r ? (mpix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
+             data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;
+             data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;
+             data_sc_r2 <= data_sc_r;
+         end
+         
+         if (phases[12]) data_sc_r2 <= data_sc_r;
+        
+         if      (var_last)    mode_mux <= 0;
+         else if (phases[13])  mode_mux <= mode_mux + 1;
+    
+         if (phases[13]) case (mode_mux)
+             1'b0: data_dtt_in <= data_cc_r;
+             1'b1: data_dtt_in <= data_sc_r2;
+         endcase
+    
+         if (!phases[14]) dtt_in_cntr <= 0; 
+         else             dtt_in_cntr <= dtt_in_cntr + 1;
+   
+         start_dtt <= dtt_in_cntr == DTT_IN_DELAY;
+
+         if (rst)               dtt_in_page <= 0;
+         else if (&dtt_in_cntr) dtt_in_page <= dtt_in_page + 1;
+        
+        // reading memory and running DTT
+        
+        if (start_dtt)        dtt_r_page <=dtt_in_page;
+        
+        if (rst)              dtt_r_re <= 1'b0;
+        else if (start_dtt)   dtt_r_re <= 1'b1;
+        else if (&dtt_r_cntr) dtt_r_re <= 1'b0;
+        dtt_r_regen <= dtt_r_re;
+        
+        if (!dtt_r_re) dtt_r_cntr <= 0;
+        else           dtt_r_cntr <= dtt_r_cntr + 1;
+        
+///        dtt_start <= dtt_r_cntr[5:0] == 0;
+        dtt_start <= (dtt_r_cntr[5:0] == 0) && dtt_r_re;
+    
+    end
+    
+      
+    mclt_bayer_fold #(
+        .SHIFT_WIDTH     (SHIFT_WIDTH),
+        .PIX_ADDR_WIDTH  (PIX_ADDR_WIDTH),
+        .COORD_WIDTH     (COORD_WIDTH),
+        .PIXEL_WIDTH     (PIXEL_WIDTH),
+        .WND_WIDTH       (WND_WIDTH),
+        .OUT_WIDTH       (OUT_WIDTH),
+        .DTT_IN_WIDTH    (DTT_IN_WIDTH),
+        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
+        .OUT_RSHIFT      (OUT_RSHIFT),
+        .OUT_RSHIFT2     (OUT_RSHIFT2),
+        .DSP_B_WIDTH     (DSP_B_WIDTH),
+        .DSP_A_WIDTH     (DSP_A_WIDTH),
+        .DSP_P_WIDTH     (DSP_P_WIDTH),
+        .DEAD_CYCLES     (DEAD_CYCLES)
+    ) mclt_bayer_fold_i (
+        .clk         (clk),         // input
+        .rst         (rst),         // input
+        .start       (start),       // input
+        .tile_size   (tile_size),   // input[1:0] 
+        .inv_checker (inv_checker), // input
+        .top_left    (top_left),    // input[7:0] 
+        .valid_rows  (valid_rows),  // input[1:0] 
+        .x_shft      (x_shft),      // input[6:0] 
+        .y_shft      (y_shft),      // input[6:0] 
+        .pix_addr    (pix_addr),    // output[8:0] 
+        .pix_re      (pix_re),      // output
+        .pix_page    (pix_page),    // output
+        .window      (window_w),     // output[17:0] signed 
+        .signs       (signs),       // output[1:0] 
+        .phases      (phases),      // output[7:0]
+        .var_first   (var_first)    // output reg 
+    );
+
+    dly_var #(
+        .WIDTH(2),
+        .DLY_WIDTH(4)
+    ) dly_pix_sgn_i (
+        .clk  (clk),           // input
+        .rst  (rst),           // input
+        .dly  (4'h1),          // input[3:0] 
+        .din  (signs),    // input[0:0] 
+        .dout (pix_sgn_d)     // output[0:0] 
+    );
+
+
+    ram18p_var_w_var_r #(
+        .REGISTERS(1),
+        .LOG2WIDTH_WR(5),
+        .LOG2WIDTH_RD(5)
+    ) ram18p_var_w_var_r_dtt_in_i (
+        .rclk     (clk),          // input
+        .raddr    (dtt_r_ra),     // input[8:0] 
+        .ren      (dtt_r_re),     // input
+        .regen    (dtt_r_regen),  // input
+        .data_out (dtt_r_data_w), // output[35:0] 
+        .wclk     (clk),          // input
+        .waddr    (dtt_in_wa),    // input[8:0] 
+        .we       (dtt_we),       // input
+        .web      (4'hf),         // input[3:0] 
+        .data_in  ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] 
+    );
+    wire [8:0] dbgt_diff_wara = dtt_in_wa-dtt_r_ra;
+    
+    
+/*
+    wire signed [OUT_WIDTH-1:0] dtt_out_wd;
+    wire                  [3:0] dtt_out_wa16;
+    wire                        dtt_out_we;
+    wire                        dtt_sub16;
+    wire                        dtt_inc16;
+    reg                   [4:0] dtt_out_ram_cntr;
+    reg                   [4:0] dtt_out_ram_wah;
+    wire                        dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
+    reg                         dtt_start_first_fill;
+    reg                         dtt_start_out;  // start read out to sin/cos rotator
+*/
+
+endmodule
+

dsp/mclt_bayer_fold.v

+/*!
+ * <b>Module:</b> mclt_bayer_fold
+ * @file mclt_bayer_fold.v
+ * @date 2017-12-21  
+ * @author eyesis
+ *     
+ * @brief Generate addresses and windows to fold MCLT Bayer data
+ *
+ * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ *
+ * <b>License </b>
+ *
+ * mclt_bayer_fold.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * mclt_bayer_fold.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+
+module  mclt_bayer_fold#(
+    parameter SHIFT_WIDTH =      7, // bits in shift (7 bits - fractional)
+    parameter PIX_ADDR_WIDTH =   9, // number of pixel address width
+//    parameter EXT_PIX_LATENCY =  2, // external pixel buffer a->d latency
+    parameter ADDR_DLY =        4'h2, // extra delay of pixel address to match window delay
+    parameter COORD_WIDTH =     10, // bits in full coordinate 10 for 18K RAM
+    parameter PIXEL_WIDTH =     16, // input pixel width (unsigned) 
+    parameter WND_WIDTH =       18, // input pixel width (unsigned) 
+    parameter OUT_WIDTH =       25, // bits in dtt output
+    parameter DTT_IN_WIDTH =    25, // bits in DTT input
+    parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)    
+    parameter OUT_RSHIFT =       2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
+    parameter OUT_RSHIFT2 =      0, // overall right shift for the second (vertical) pass
+    parameter DSP_B_WIDTH =     18, // signed, output from sin/cos ROM
+    parameter DSP_A_WIDTH =     25,
+    parameter DSP_P_WIDTH =     48,
+    parameter DEAD_CYCLES =     14  // start next block immedaitely, or with longer pause
+)(
+    input                             clk,          //!< system clock, posedge
+    input                             rst,          //!< sync reset
+    input                             start,        //!< start convertion of the next 256 samples
+    input                       [1:0] tile_size,    //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
+    input                             inv_checker,  //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
+    input                       [7:0] top_left,     //!< index of the 16x16 top left corner
+    input                       [1:0] valid_rows,   //!< 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
+    input           [SHIFT_WIDTH-1:0] x_shft,       //!< tile pixel X fractional shift (valid @ start) 
+    input           [SHIFT_WIDTH-1:0] y_shft,       //!< tile pixel Y fractional shift (valid @ start)
+    
+    output       [PIX_ADDR_WIDTH-1:0] pix_addr,     //!< external pixel buffer address
+    output                            pix_re,       //!< pixel read enable (sync with  mpixel_a)
+    output                            pix_page,     //!< copy pixel page (should be externally combined with first color)
+    output signed     [WND_WIDTH-1:0] window,       //!< msb==0, always positive
+    output                      [1:0] signs,        //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
+    output                     [14:0] phases,        //!< other signals
+    output reg                        var_first  
+);
+    reg                         [6:0] in_cntr;      // input phase counter
+    reg                        [14:0] run_r;        // run phase
+    reg                         [1:0] tile_size_r;  // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
+    reg                               inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
+    reg                         [7:0] top_left_r0;  // index of the 16x16 top left corner
+    reg                         [7:0] top_left_r;   // index of the 16x16 top left corner
+    reg                         [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
+    reg                         [1:0] valid_rows_r ;// correct latency for window rom
+    reg             [SHIFT_WIDTH-1:0] x_shft_r0;    // tile pixel X fractional shift (valid @ start) 
+    reg             [SHIFT_WIDTH-1:0] y_shft_r0;    // tile pixel Y fractional shift (valid @ start)
+    reg             [SHIFT_WIDTH-1:0] x_shft_r;     // matching delay 
+    reg             [SHIFT_WIDTH-1:0] y_shft_r;     // matching delay
+    wire                       [17:0] fold_rom_out;
+
+    // does not have enough bits for pixel address (9) and window address(8), restoring MSB of pixel address from both MSBc
+    wire                        [7:0] wnd_a_w =   fold_rom_out[7:0];
+    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
+    reg          [PIX_ADDR_WIDTH-1:0] pix_a_r;
+    wire                       [ 1:0] sgn_w =     fold_rom_out[16 +: 2];
+    reg                               blank_r;    // blank window (latency 1 from fold_rom_out)
+//    wire                              blank_d;    //  delayed to matchwindow rom regrst
+    wire                              pre_page =  in_cntr == 2; // valid 1 cycle before fold_rom_out
+    
+    wire                              var_first_d; // adding subtracting first variant of 2 folds    
+    
+    assign phases = run_r;
+    
+//    wire           [ 3:0] bayer_1hot = { mpix_a_w[4] &  mpix_a_w[0],  
+//                                        mpix_a_w[4] & ~mpix_a_w[0],
+//                                        ~mpix_a_w[4] &  mpix_a_w[0],
+//                                        ~mpix_a_w[4] & ~mpix_a_w[0]};
+                                        
+//    wire                          mpix_use = |(bayer_d & bayer_1hot); //not disabled by bayer, valid with mpix_a_w
+//    wire                          mpix_use_d; // delayed
+//    reg                           mpix_use_r; // delayed
+
+   
+    always @ (posedge clk) begin
+        if (rst) run_r <= 0;
+        else     run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
+        
+        if (!run_r[0]) in_cntr <= 0;
+        else           in_cntr <= in_cntr + 1;
+        
+        if (start) begin
+            tile_size_r <=   tile_size;
+            inv_checker_r<=  inv_checker;
+            top_left_r0 <=   top_left;
+            valid_rows_r0 <= valid_rows;
+            x_shft_r0 <=     x_shft;
+            y_shft_r0 <=     y_shft;
+        end
+        
+        if (in_cntr == 1) top_left_r <=top_left_r0;
+        
+        if (in_cntr == 1) begin
+            x_shft_r <= x_shft_r0;
+            y_shft_r <= y_shft_r0;
+        end
+            
+
+        if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};
+        
+
+        if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
+        
+        blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);  
+        
+        if (run_r[10]) begin
+            var_first <= var_first_d;
+        end
+         
+    end
+
+     ram18tp_var_w_var_r #(
+        .REGISTERS_A(1),
+        .REGISTERS_B(1),
+        .LOG2WIDTH_A(4),
+        .LOG2WIDTH_B(4)
+`ifdef PRELOAD_BRAMS
+    `include "mclt_bayer_fold_rom.vh"
+`endif
+    ) i_mclt_fold_rom (
+    
+        .clk_a     (clk),          // input
+        .addr_a    ({tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]}),    // input[9:0] 
+        .en_a      (run_r[0]),     // input
+        .regen_a   (run_r[1]),     // input
+        .we_a      (1'b0),         // input
+        .data_out_a(fold_rom_out), // output[17:0] 
+        .data_in_a (18'b0),        // input[17:0]
+        // port B may be used for other mclt16x16 
+        .clk_b     (1'b0),         // input
+        .addr_b    (10'b0),        // input[9:0] 
+        .en_b      (1'b0),         // input
+        .regen_b   (1'b0),         // input
+        .we_b      (1'b0),         // input
+        .data_out_b(),             // output[17:0] 
+        .data_in_b (18'b0)         // input[17:0] 
+    );
+
+// Matching window latency with pixel data latency
+    dly_var #(
+        .WIDTH(11),
+        .DLY_WIDTH(4)
+    ) dly_pixel_addr_i (
+        .clk  (clk),      // input
+        .rst  (rst),      // input
+        .dly  (4'h2),     // input[3:0] Delay for external memory latency = 2, reduce for higher 
+        .din  ({pre_page, run_r[3], pix_a_r}), // input[0:0] 
+        .dout ({pix_page,   pix_re, pix_addr}) // output[0:0] 
+    );
+
+/*
+    dly_var #(
+        .WIDTH(1),
+        .DLY_WIDTH(4)
+    ) dly_blank_i (
+        .clk  (clk),           // input
+        .rst  (rst),           // input
+        .dly  (4'h0),          // TODO: put correct value! 
+        
+        
+         
+        .din  (blank_r),  // input[0:0] 
+        .dout (blank_d)   // output[0:0] 
+    );
+*/
+// Latency = 6
+    mclt_wnd_mul #(
+        .SHIFT_WIDTH (SHIFT_WIDTH),
+        .COORD_WIDTH (COORD_WIDTH),
+        .OUT_WIDTH   (WND_WIDTH)
+    ) mclt_wnd_i (
+        .clk       (clk), // input
+        .en        (run_r[2]), // input
+        .x_in      (wnd_a_w[3:0]), // input[3:0] 
+        .y_in      (wnd_a_w[7:4]), // input[3:0] 
+        .x_shft    (x_shft_r),     // input[7:0] 
+        .y_shft    (y_shft_r),     // input[7:0]
+        .zero_in   (blank_r),      // input 2 cycles after inputs! 
+        .wnd_out   (window)        // output[17:0] valid with in_busy[8]
+    );
+
+    dly_var #(
+        .WIDTH(2),
+        .DLY_WIDTH(4)
+    ) dly_signs_i (
+        .clk  (clk),           // input
+        .rst  (rst),           // input
+        .dly  (4'h5),        // TODO: put correct value! 
+        .din  (sgn_w),  // input[0:0] 
+        .dout (signs)   // output[0:0] 
+    );
+
+    dly_var #(
+        .WIDTH(1),
+        .DLY_WIDTH(4)
+    ) dly_var_first_i (
+        .clk  (clk),           // input
+        .rst  (rst),           // input
+        .dly  (4'h9),          // input[3:0] 
+        .din  (run_r[0] && (in_cntr[0] == 0)),  // input[0:0] 
+        .dout (var_first_d)    // output[0:0] 
+    );
+
+    
+//
+endmodule
+

dsp/mclt_test_02.tf

+/*!
+ * <b>Module:</b>mclt_test_01
+ * @file mclt_test_01.tf
+ * @date 2016-12-02  
+ * @author  Andrey Filippov
+ *     
+ * @brief testing MCLT 16x16 -> 4*8*8 transform
+ * Uses 2 DSP blocks 
+ *
+ * @copyright Copyright (c) 2016 Elphel, Inc.
+ *
+ * <b>License:</b>
+ *
+ *mclt_test_01.tf is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mclt_test_01.tf is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+  `define INSTANTIATE_DSP48E1
+  `define PRELOAD_BRAMS
+//  `define ROUND 
+module  mclt_test_02 ();
+`ifdef IVERILOG              
+    `ifdef NON_VDT_ENVIROMENT
+        parameter fstname="mclt_test_02.fst";
+    `else
+        `include "IVERILOG_INCLUDE.v"
+    `endif // NON_VDT_ENVIROMENT
+`else // IVERILOG
+    `ifdef CVC
+        `ifdef NON_VDT_ENVIROMENT
+            parameter fstname = "x393.fst";
+        `else // NON_VDT_ENVIROMENT
+            `include "IVERILOG_INCLUDE.v"
+        `endif // NON_VDT_ENVIROMENT
+    `else
+        parameter fstname = "mclt_test_02.fst";
+    `endif // CVC
+`endif // IVERILOG
+    
+    parameter CLK_PERIOD =      10; // ns
+//    parameter WIDTH =           25; //4; // input data width
+    parameter SHIFT_WIDTH =      7; // bits in shift (7 bits - fractional)
+    parameter COORD_WIDTH =     10; // bits in full coordinate 10 for 18K RAM
+    parameter PIXEL_WIDTH =     16; // input pixel width (unsigned) 
+    parameter WND_WIDTH =       18; // input pixel width (unsigned) 
+    parameter OUT_WIDTH =       25; // bits in dtt output
+    parameter DTT_IN_WIDTH =    25; // bits in DTT input
+    parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results)    
+    parameter OUT_RSHIFT =       2; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
+    parameter OUT_RSHIFT2 =      0; // overall right shift for the second (vertical) pass
+    parameter DSP_B_WIDTH =     18; // signed, output from sin/cos ROM
+    parameter DSP_A_WIDTH =     25;
+    parameter DSP_P_WIDTH =     48;
+    parameter DEAD_CYCLES =     14;  // start next block immedaitely, or with longer pause
+    
+    //parameter DCT_GAP = 16; // between runs            
+    
+    //parameter SAME_BITS=4; // (3) to match 24-bit widths
+    
+    reg              RST = 1'b1;
+    reg              CLK = 1'b0;
+    
+    reg   [PIXEL_WIDTH-1 : 0]   tile_shift[0:258];  // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg   [PIXEL_WIDTH-1 : 0]   tiles[0:1023];
+    reg   [SHIFT_WIDTH-1 : 0]   shifts_x[0:3]; 
+    reg   [SHIFT_WIDTH-1 : 0]   shifts_y[0:3]; 
+    reg               [3 : 0]   bayer[0:3]; 
+    
+    reg                 [3:0]   java_wnd_signs[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg                 [7:0]   java_fold_index[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg     [WND_WIDTH - 1:0]   java_tiles_wnd[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+
+    reg     [WND_WIDTH - 1:0]   tiles_wnd[0:1023];    // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_in[0:1023];  // SuppressThisWarning VEditor : assigned in $readmem() system task
+
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_out[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_rot0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg  [DTT_IN_WIDTH - 1:0]   java_dtt_rot[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    integer   i, n, n_out;
+    initial begin
+        $readmemh("input_data/clt_wnd_signs.dat",  java_wnd_signs);
+        $readmemh("input_data/clt_fold_index.dat", java_fold_index);
+    
+//        $readmemh("input_data/tile_01.dat",tile_shift);
+        //============ tile 0
+        $readmemh("input_data/clt_tile_00_2_x1489_y951.dat",tile_shift);
+        shifts_x[0] = tile_shift[0][SHIFT_WIDTH-1:0];
+        shifts_y[0] = tile_shift[1][SHIFT_WIDTH-1:0];
+        bayer[0] =    tile_shift[2][3:0];
+        for (i=0; i<256; i=i+1) begin
+            tiles['h000 + i] = tile_shift[i+3]; 
+        end
+        $readmemh("input_data/clt_wnd_00_2_x1489_y951.dat",java_tiles_wnd);
+        for (i=0; i<256; i=i+1) begin
+            tiles_wnd['h000 + i] = java_tiles_wnd[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_in_00_2_x1489_y951.dat",java_dtt_in0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_in['h000 + i] = java_dtt_in0[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_out_00_2_x1489_y951.dat",java_dtt_out0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_out['h000 + i] = java_dtt_out0[i]; 
+        end
+        
+        $readmemh("input_data/clt_dtt_rot_00_2_x1489_y951.dat",java_dtt_rot0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_rot['h000 + i] = java_dtt_rot0[i]; 
+        end
+        
+        //============ tile 1
+        
+        $readmemh("input_data/clt_tile_01_2_x1489_y951.dat",tile_shift);
+        shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
+        shifts_y[1] = tile_shift[1][SHIFT_WIDTH-1:0];
+        bayer[1] =    tile_shift[2][3:0];
+        for (i=0; i<256; i=i+1) begin
+            tiles['h100 + i] = tile_shift[i+3]; 
+        end
+        
+        $readmemh("input_data/clt_wnd_01_2_x1489_y951.dat",java_tiles_wnd);
+        for (i=0; i<256; i=i+1) begin
+            tiles_wnd['h100 + i] = java_tiles_wnd[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_in_01_2_x1489_y951.dat",java_dtt_in0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_in['h100 + i] = java_dtt_in0[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_out_01_2_x1489_y951.dat",java_dtt_out0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_out['h100 + i] = java_dtt_out0[i]; 
+        end
+        
+        $readmemh("input_data/clt_dtt_rot_01_2_x1489_y951.dat",java_dtt_rot0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_rot['h100 + i] = java_dtt_rot0[i]; 
+        end
+        
+        //============ tile 2
+        
+        $readmemh("input_data/clt_tile_02_2_x1489_y951.dat",tile_shift);
+        shifts_x[2] = tile_shift[0][SHIFT_WIDTH-1:0];
+        shifts_y[2] = tile_shift[1][SHIFT_WIDTH-1:0];
+        bayer[2] =    tile_shift[2][3:0];
+        for (i=0; i<256; i=i+1) begin
+            tiles['h200 + i] = tile_shift[i+3]; 
+        end
+        
+        $readmemh("input_data/clt_wnd_02_2_x1489_y951.dat",java_tiles_wnd);
+        for (i=0; i<256; i=i+1) begin
+            tiles_wnd['h200 + i] = java_tiles_wnd[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_in_02_2_x1489_y951.dat",java_dtt_in0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_in['h200 + i] = java_dtt_in0[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_out_02_2_x1489_y951.dat",java_dtt_out0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_out['h200 + i] = java_dtt_out0[i]; 
+        end
+        
+        $readmemh("input_data/clt_dtt_rot_02_2_x1489_y951.dat",java_dtt_rot0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_rot['h200 + i] = java_dtt_rot0[i]; 
+        end
+        
+        //============ tile 3
+        
+        $readmemh("input_data/clt_tile_00_2_x1489_y951.dat",tile_shift);
+        shifts_x[3] = tile_shift[0][SHIFT_WIDTH-1:0];
+        shifts_y[3] = tile_shift[1][SHIFT_WIDTH-1:0];
+        bayer[3] =    tile_shift[2][3:0];
+        for (i=0; i<256; i=i+1) begin
+            tiles['h300 + i] = tile_shift[i+3]; 
+        end
+        $readmemh("input_data/clt_wnd_00_2_x1489_y951.dat",java_tiles_wnd);
+        for (i=0; i<256; i=i+1) begin
+            tiles_wnd['h300 + i] = java_tiles_wnd[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_in_00_2_x1489_y951.dat",java_dtt_in0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_in['h300 + i] = java_dtt_in0[i]; 
+        end
+
+        $readmemh("input_data/clt_dtt_out_00_2_x1489_y951.dat",java_dtt_out0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_out['h300 + i] = java_dtt_out0[i]; 
+        end
+        
+        $readmemh("input_data/clt_dtt_rot_00_2_x1489_y951.dat",java_dtt_rot0);
+        for (i=0; i<256; i=i+1) begin
+            java_dtt_rot['h300 + i] = java_dtt_rot0[i]; 
+        end
+        
+        for (n=0;n<4;n=n+1) begin
+            $display("Tile %d: shift x = %h, shift_y = %h, bayer = %h", 0, shifts_x[n], shifts_y[n], bayer[n]);
+            for (i = 256 * n; i < 256 * (n + 1); i = i + 16) begin
+                $display ("%h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
+                    tiles[i+ 0],tiles[i+ 1],tiles[i+ 2],tiles[i+ 3],
+                    tiles[i+ 4],tiles[i+ 5],tiles[i+ 6],tiles[i+ 7],
+                    tiles[i+ 8],tiles[i+ 9],tiles[i+10],tiles[i+11],
+                    tiles[i+12],tiles[i+13],tiles[i+14],tiles[i+15]);
+            end
+            $display("");
+        end
+        
+    end
+
+    reg                         start;
+    reg       [SHIFT_WIDTH-1:0] x_shft; 
+    reg       [SHIFT_WIDTH-1:0] y_shft;
+    reg                   [3:0] bayer_r;
+    reg                   [1:0] page_in; 
+    wire                        pre_busy_w;
+    wire                        pre_busy;
+    reg                         LATE = 0;
+    wire                        mpixel_re;
+    wire                        mpixel_page;    
+    reg                         mpixel_reg;
+    reg                         mpixel_valid;
+    wire                  [7:0] mpixel_a;
+    reg     [PIXEL_WIDTH-1 : 0] pixel_r;
+    reg     [PIXEL_WIDTH-1 : 0] pixel_r2;
+    wire    [PIXEL_WIDTH-1 : 0] mpixel_d = mpixel_valid ? pixel_r2 : {PIXEL_WIDTH{1'bz}};  
+    
+    wire                        pre_last_in;   // SuppressThisWarning VEditor - output only
+    wire                        pre_first_out; // SuppressThisWarning VEditor - output only
+    wire                        pre_last_out;  // SuppressThisWarning VEditor - output only
+    wire                  [7:0] out_addr;      // SuppressThisWarning VEditor - output only
+    wire                        dv;            // SuppressThisWarning VEditor - output only
+    wire        [OUT_WIDTH-1:0] dout;          // SuppressThisWarning VEditor - output only
+    
+    assign  #(1)  pre_busy = pre_busy_w;
+    
+    
+    always #(CLK_PERIOD/2) CLK = ~CLK;    
+    initial begin
+        $dumpfile(fstname);
+        $dumpvars(0,mclt_test_02); // SuppressThisWarning VEditor
+        #100;
+        start =  0;
+        page_in = 0;
+        LATE = 0;
+        RST = 0;
+        #100;
+        repeat (10) @(posedge CLK);
+//        #1;
+        for (n = 0; n < 4; n = n+1) begin
+            if (n>2) LATE = 1;
+            while (pre_busy || LATE) begin
+                if (!pre_busy) LATE = 0;
+                @(posedge CLK);
+                #1;
+            end
+            start = 1;
+            x_shft = shifts_x[n];
+            y_shft = shifts_y[n];
+            bayer_r = bayer[n];
+            @(posedge CLK);
+            #1;
+            start = 0; 
+            x_shft = 'bz;
+            y_shft = 'bz;
+            bayer_r = 'bz;                    
+            @(posedge CLK);
+//            #1;
+        end 
+        // emergency finish
+        repeat (1024) @(posedge CLK);
+        $finish; 
+        //pre_last_out
+    end
+    
+    always @ (posedge CLK) if (!RST) begin
+        mpixel_reg <=     mpixel_re;
+        mpixel_valid <=   mpixel_reg; 
+        if (mpixel_re)    pixel_r <= tiles[{page_in,mpixel_a}];
+        if (mpixel_reg)   pixel_r2 <= pixel_r; 
+        if (mpixel_page)  page_in <= page_in + 1;
+        if (pre_last_out) n_out <= n_out + 1;
+
+    end
+
+    initial begin
+        n_out = 0;
+        while (n_out < 4)  @(posedge CLK);
+        repeat (32)        @(posedge CLK);
+        $finish;
+    
+    end
+
+    integer n1, cntr1, diff1;// SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire           [7:0] mpix_a_w = mclt16x16_i.mpix_a_w;
+    wire           [7:0] java_fi_w = java_fold_index[cntr1];  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n1 = 0; n1 < 4; n1 = n1+1) begin
+            while (mclt16x16_i.in_cntr != 2) begin
+                @(negedge CLK);
+            end
+            for (cntr1 = 0; cntr1 < 256; cntr1 = cntr1 + 1) begin
+                diff1 = mpix_a_w - java_fi_w; // java_fold_index[cntr1];
+                @(negedge CLK);
+            end
+        end
+    end
+
+    integer n2, cntr2, diff2, diff2a; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r;
+//    reg            [7:0] java_fi_r;  
+    wire [WND_WIDTH-1:0] java_window_w = tiles_wnd[n2 * 256 + cntr2]; //  java_tiles_wnd[cntr2];  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n2 = 0; n2 < 4; n2 = n2+1) begin
+            while (mclt16x16_i.in_cntr != 9) begin
+                @(negedge CLK);
+            end
+            for (cntr2 = 0; cntr2 < 256; cntr2 = cntr2 + 1) begin
+                diff2 = window_r - java_window_w;
+                if (n2 < 1) diff2a = window_r - java_window_w; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+
+//Compare window signs
+    integer n3, cntr3, diff3; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire           [3:0] mpix_sgn_w =  mclt16x16_i.mpix_sgn_w; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire           [3:0] java_sgn_w =  { //java_wnd_signs[java_fold_index[cntr3]];  // SuppressThisWarning VEditor : assigned in $readmem() system task
+    java_wnd_signs[{2'b11,cntr3[7:2]}][cntr3[1:0]],
+    java_wnd_signs[{2'b10,cntr3[7:2]}][cntr3[1:0]],
+    java_wnd_signs[{2'b01,cntr3[7:2]}][cntr3[1:0]],
+    java_wnd_signs[{2'b00,cntr3[7:2]}][cntr3[1:0]] 
+    };
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n3 = 0; n3 < 4; n3 = n3+1) begin
+            while (mclt16x16_i.in_cntr != 2) begin
+                @(negedge CLK);
+            end
+            for (cntr3 = 0; cntr3 < 256; cntr3 = cntr3 + 1) begin
+                #1;
+                diff3 = mpix_sgn_w - java_sgn_w; // java_fold_index[cntr1];
+                @(negedge CLK);
+            end
+        end
+    end
+
+//Compare DTT inputs
+
+    integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_i.data_dtt_in;
+    wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = java_dtt_in[{n4[1:0], cntr4[1:0],cntr4[7:2]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n4 = 0; n4 < 4; n4 = n4+1) begin
+            while (mclt16x16_i.in_cntr != 16) begin
+                @(negedge CLK);
+            end
+            for (cntr4 = 0; cntr4 < 256; cntr4 = cntr4 + 1) begin
+                #1;
+                diff4 = data_dtt_in - java_data_dtt_in;
+                if (n4 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+
+    integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_i.dtt_r_data;
+    wire [DTT_IN_WIDTH-1:0] java_dtt_r_data =  java_dtt_in[{n5[1:0], cntr5[7:0]}]; // java_dtt_in0[cntr5[7:0]];
+    
+    wire                           dtt_r_regen = mclt16x16_i.dtt_r_regen;
+    reg                            dtt_r_dv; // SuppressThisWarning VEditor just for simulation
+    always @ (posedge CLK) begin
+        if (RST) dtt_r_dv <= 0;
+        else     dtt_r_dv <= dtt_r_regen;
+    end
+    
+      
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n5 = 0; n5 < 4; n5 = n5+1) begin
+            while ((!dtt_r_dv) || (mclt16x16_i.dtt_r_cntr[7:0] != 2)) begin
+                @(negedge CLK);
+            end
+            for (cntr5 = 0; cntr5 < 256; cntr5 = cntr5 + 1) begin
+                #1;
+                diff5 = dtt_r_data - java_dtt_r_data;
+                if (n5 < 1) diff5a = dtt_r_data - java_dtt_r_data; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+
+
+
+
+    integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;
+//    wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];  
+    wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out[{n6[1:0], cntr6[0],cntr6[1], cntr6[7:2]}]; //java_dtt_out0[{cntr6[0],cntr6[1],cntr6[7:2]}];  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n6 = 0; n6 < 4; n6 = n6+1) begin
+            while ((!mclt16x16_i.dtt_rd_regen_dv[2]) || (mclt16x16_i.dtt_rd_cntr[7:0] != 2)) begin
+                @(negedge CLK);
+            end
+            for (cntr6 = 0; cntr6 < 256; cntr6 = cntr6 + 1) begin
+                #1;
+                diff6 = data_dtt_out - java_data_dtt_out;
+                if (n6 < 1) diff6a = data_dtt_out - java_data_dtt_out; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+
+    reg FIRST_OUT;
+    always @(posedge CLK) FIRST_OUT <= mclt16x16_i.pre_first_out;
+    
+    integer n7, cntr7, diff7, diff7a; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    wire [OUT_WIDTH-1:0] java_data_dtt_rot = java_dtt_rot[{n7[1:0], cntr7[1],cntr7[0],cntr7[7:2]}];  //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n7 = 0; n7 < 4; n7 = n7+1) begin
+            while (!FIRST_OUT) begin
+                @(negedge CLK);
+            end
+            for (cntr7 = 0; cntr7 < 256; cntr7 = cntr7 + 1) begin
+                #1;
+                diff7 = dout - java_data_dtt_rot;
+                if (n7 < 1) diff7a = dout - java_data_dtt_rot; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+    
+    
+    
+    mclt16x16 #(
+        .SHIFT_WIDTH     (SHIFT_WIDTH),
+        .COORD_WIDTH     (COORD_WIDTH),
+        .PIXEL_WIDTH     (PIXEL_WIDTH),
+        .WND_WIDTH       (WND_WIDTH),
+        .OUT_WIDTH       (OUT_WIDTH),
+        .DTT_IN_WIDTH    (DTT_IN_WIDTH),
+        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
+        .OUT_RSHIFT      (OUT_RSHIFT),
+        .OUT_RSHIFT2     (OUT_RSHIFT2),
+        .DSP_B_WIDTH     (DSP_B_WIDTH),
+        .DSP_A_WIDTH     (DSP_A_WIDTH),
+        .DSP_P_WIDTH     (DSP_P_WIDTH),
+        .DEAD_CYCLES     (DEAD_CYCLES)
+    ) mclt16x16_i (
+        .clk             (CLK),         // input
+        .rst             (RST),         // input
+        .start           (start),       // input
+        .x_shft          (x_shft),      // input[6:0] 
+        .y_shft          (y_shft),      // input[6:0] 
+        .bayer           (bayer_r),     // input[3:0] 
+        .mpixel_re       (mpixel_re),   // output
+        .mpixel_page     (mpixel_page), // output  //!< increment pixel page after this
+        
+        .mpixel_a        (mpixel_a),    // output[7:0] 
+        .mpixel_d        (mpixel_d),    // input[15:0] 
+        .pre_busy        (pre_busy_w),    // output
+        .pre_last_in     (pre_last_in), // output reg 
+        .pre_first_out   (pre_first_out), // output
+        .pre_last_out    (pre_last_out), // output
+        .out_addr        (out_addr), // output[7:0] 
+        .dv              (dv), // output
+        .dout            (dout) // output[24:0] signed 
+    );
+
+    localparam PIX_ADDR_WIDTH = 9;
+    localparam ADDR_DLY = 2;
+    reg                   [1:0] TILE_SIZE =   3; // 22;
+    reg                         INV_CHECKER = 0;
+    reg                   [7:0] TOP_LEFT =    69; // center
+    reg                   [1:0] VALID_ROWS =  3;  // for green component
+    reg                   [6:0] CLT_SHIFT_X = 'h62; // shift_x, 7 bits
+    reg                   [6:0] CLT_SHIFT_Y = 'h0a;  // shift_y, 7 bits
+    wire                  [8:0] PIX_ADDR9;
+    wire                        PIX_RE;
+    wire                        PIX_PAGE; // copy page address // SuppressThisWarning VEditor - not yet used
+    wire    [PIXEL_WIDTH-1 : 0] PIX_D = PIX_VALID ? PIX_R2 : {PIXEL_WIDTH{1'bz}};  
+    reg     [PIXEL_WIDTH-1 : 0] PIX_R;
+    reg     [PIXEL_WIDTH-1 : 0] PIX_R2;
+    reg                         PIX_REG;
+    reg                         PIX_VALID;
+    reg   [PIXEL_WIDTH-1 : 0]   bayer_tiles[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    
+
+    always @ (posedge CLK) if (!RST) begin
+        PIX_REG <=        PIX_RE;
+        PIX_VALID <=      PIX_REG; 
+        if (PIX_RE)    PIX_R <= bayer_tiles[{1'b0, PIX_ADDR9}];
+        if (PIX_REG)   PIX_R2 <= PIX_R; 
+    end
+
+    initial begin
+        $readmemh("input_data/clt_tile22_x1489_y951.dat",bayer_tiles);
+    end
+    
+    mclt16x16_bayer #(
+        .SHIFT_WIDTH     (SHIFT_WIDTH),
+        .PIX_ADDR_WIDTH  (PIX_ADDR_WIDTH),
+        .COORD_WIDTH     (COORD_WIDTH),
+        .PIXEL_WIDTH     (PIXEL_WIDTH),
+        .WND_WIDTH       (WND_WIDTH),
+        .OUT_WIDTH       (OUT_WIDTH),
+        .DTT_IN_WIDTH    (DTT_IN_WIDTH),
+        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
+        .OUT_RSHIFT      (OUT_RSHIFT),
+        .OUT_RSHIFT2     (OUT_RSHIFT2),
+        .DSP_B_WIDTH     (DSP_B_WIDTH),
+        .DSP_A_WIDTH     (DSP_A_WIDTH),
+        .DSP_P_WIDTH     (DSP_P_WIDTH),
+        .DEAD_CYCLES     (DEAD_CYCLES)
+    ) mclt_bayer_fold_i (
+        .clk         (CLK),         // input
+        .rst         (RST),         // input
+        .start       (start),       // input
+        .tile_size   (TILE_SIZE),   // input[1:0] 
+        .inv_checker (INV_CHECKER), // input
+        .top_left    (TOP_LEFT),    // input[7:0] 
+        .valid_rows  (VALID_ROWS),  // input[1:0] 
+        .x_shft      (CLT_SHIFT_X), // input[6:0] 
+        .y_shft      (CLT_SHIFT_Y), // input[6:0] 
+        .pix_addr    (PIX_ADDR9),   // output[8:0] 
+        .pix_re      (PIX_RE),      // output
+        .pix_page    (PIX_PAGE),    // output
+        .pix_d       (PIX_D)        // input[15:0] 
+    );
+
+
+
+endmodule

dsp/mclt_wnd_mul.v

@@ -43,12 +43,13 @@ module  mclt_wnd_mul#(
     parameter COORD_WIDTH = 10,  // bits in full coordinate 10 for 18K RAM 
     parameter OUT_WIDTH =   18   // bits in window value (positive) 
 )(
-    input                           clk,   //!< system clock, posedge
-    input                           en,    //!< re (both re and ren - just for power)
-    input                     [3:0] x_in,  //!< tile pixel X
-    input                     [3:0] y_in,  //!< tile pixel Y
+    input                           clk,     //!< system clock, posedge
+    input                           en,      //!< re (both re and ren - just for power)
+    input                     [3:0] x_in,    //!< tile pixel X
+    input                     [3:0] y_in,    //!< tile pixel Y
     input         [SHIFT_WIDTH-1:0] x_shft,  //!< tile pixel X
     input         [SHIFT_WIDTH-1:0] y_shft,  //!< tile pixel Y
+    input                           zero_in, // set window to zero (2 cycles after other inputs) 
     output signed [OUT_WIDTH - 1 : 0] wnd_out            
 );
     wire         [COORD_WIDTH - 1 : 0] x_full;
@@ -77,7 +78,7 @@ module  mclt_wnd_mul#(
         wnd_out_x_r <= wnd_out_x;
         wnd_out_y_r <= wnd_out_y;
 //        zero <= {zero[0],  x_zero | y_zero};
-        zero <= x_zero | y_zero;
+        zero <= x_zero | y_zero | zero_in;
         wnd_out_r <= wnd_out_w; // wnd_out_x_r * wnd_out_y_r;
     end
 

includes/mclt_bayer_fold_rom.vh

+// Created with ./create_bayer_fold_rom.py
+// MCLT 16x16...22x22 Bayer -> 8x8 fold indices
+, .INIT_00 (256'hA4A4A2A2A6A6A0A0A8A8AEAEAAAAACACB3B3B5B5B1B1B7B7BFBFB9B9BDBDBBBB)
+, .INIT_01 (256'h848482828686808088888E8E8A8A8C8C93939595919197979F9F99999D9D9B9B)
+, .INIT_02 (256'h13131515111117171F1F19191D1D1B1B040402020606000008080E0E0A0A0C0C)
+, .INIT_03 (256'h33333535313137373F3F39393D3D3B3B242422222626202028282E2E2A2A2C2C)
+, .INIT_04 (256'hD3D3D5D5D1D1D7D7DFDFD9D9DDDDDBDBC4C4C2C2C6C6C0C0C8C8CECECACACCCC)
+, .INIT_05 (256'hF3F3F5F5F1F1F7F7FFFFF9F9FDFDFBFBE4E4E2E2E6E6E0E0E8E8EEEEEAEAECEC)
+, .INIT_06 (256'h646462626666606068686E6E6A6A6C6C73737575717177777F7F79797D7D7B7B)
+, .INIT_07 (256'h444442424646404048484E4E4A4A4C4C53535555515157575F5F59595D5D5B5B)
+, .INIT_08 (256'hA3A3A5A5A1A1A7A7AFAFA9A9ADADABABB4B4B2B2B6B6B0B0B8B8BEBEBABABCBC)
+, .INIT_09 (256'h83838585818187878F8F89898D8D8B8B949492929696909098989E9E9A9A9C9C)
+, .INIT_0A (256'h141412121616101018181E1E1A1A1C1C03030505010107070F0F09090D0D0B0B)
+, .INIT_0B (256'h343432323636303038383E3E3A3A3C3C23232525212127272F2F29292D2D2B2B)
+, .INIT_0C (256'hD4D4D2D2D6D6D0D0D8D8DEDEDADADCDCC3C3C5C5C1C1C7C7CFCFC9C9CDCDCBCB)
+, .INIT_0D (256'hF4F4F2F2F6F6F0F0F8F8FEFEFAFAFCFCE3E3E5E5E1E1E7E7EFEFE9E9EDEDEBEB)
+, .INIT_0E (256'h63636565616167676F6F69696D6D6B6B747472727676707078787E7E7A7A7C7C)
+, .INIT_0F (256'h43434545414147474F4F49494D4D4B4B545452525656505058585E5E5A5A5C5C)
+, .INIT_10 (256'hB8A4B6A2BAA6B4A0BCA8C2AEBEAAC0ACC9B3CBB5C7B1CDB7D5BFCFB9D3BDD1BB)
+, .INIT_11 (256'h948492829686908098889E8E9A8A9C8CA593A795A391A997B19FAB99AF9DAD9B)
+, .INIT_12 (256'h1513171513111917211F1B191F1D1D1B040402020606000008080E0E0A0A0C0C)
+, .INIT_13 (256'h39333B3537313D37453F3F39433D413B282426222A2624202C28322E2E2A302C)
+, .INIT_14 (256'hEDD3EFD5EBD1F1D7F9DFF3D9F7DDF5DBDCC4DAC2DEC6D8C0E0C8E6CEE2CAE4CC)
+, .INIT_15 (256'h11F313F50FF115F71DFF17F91BFD19FB00E4FEE202E6FCE004E80AEE06EA08EC)
+, .INIT_16 (256'h70646E6272666C6074687A6E766A786C817383757F7185778D7F87798B7D897B)
+, .INIT_17 (256'h4C444A424E4648405048564E524A544C5D535F555B516157695F6359675D655B)
+, .INIT_18 (256'hB7A3B9A5B5A1BBA7C3AFBDA9C1ADBFABCAB4C8B2CCB6C6B0CEB8D4BED0BAD2BC)
+, .INIT_19 (256'h93839585918197879F8F99899D8D9B8BA694A492A896A290AA98B09EAC9AAE9C)
+, .INIT_1A (256'h16141412181612101A18201E1C1A1E1C03030505010107070F0F09090D0D0B0B)
+, .INIT_1B (256'h3A3438323C3636303E38443E403A423C2723292525212B27332F2D29312D2F2B)
+, .INIT_1C (256'hEED4ECD2F0D6EAD0F2D8F8DEF4DAF6DCDBC3DDC5D9C1DFC7E7CFE1C9E5CDE3CB)
+, .INIT_1D (256'h12F410F214F60EF016F81CFE18FA1AFCFFE301E5FDE103E70BEF05E909ED07EB)
+, .INIT_1E (256'h6F6371656D6173677B6F7569796D776B8274807284767E7086788C7E887A8A7C)
+, .INIT_1F (256'h4B434D4549414F47574F5149554D534B5E545C5260565A506258685E645A665C)
+, .INIT_20 (256'hCCA4CAA2CEA6C8A0D0A8D6AED2AAD4ACDFB3E1B5DDB1E3B7EBBFE5B9E9BDE7BB)
+, .INIT_21 (256'hA484A282A686A080A888AE8EAA8AAC8CB793B995B591BB97C39FBD99C19DBF9B)
+, .INIT_22 (256'h1713191515111B17231F1D19211D1F1B040402020606000008080E0E0A0A0C0C)
+, .INIT_23 (256'h3F3341353D3143374B3F4539493D473B2C242A222E2628203028362E322A342C)
+, .INIT_24 (256'h07D309D505D10BD713DF0DD911DD0FDBF4C4F2C2F6C6F0C0F8C8FECEFACAFCCC)
+, .INIT_25 (256'h2FF331F52DF133F73BFF35F939FD37FB1CE41AE21EE618E020E826EE22EA24EC)
+, .INIT_26 (256'h7C647A627E6678608068866E826A846C8F7391758D7193779B7F9579997D977B)
+, .INIT_27 (256'h544452425646504058485E4E5A4A5C4C6753695565516B57735F6D59715D6F5B)
+, .INIT_28 (256'hCBA3CDA5C9A1CFA7D7AFD1A9D5ADD3ABE0B4DEB2E2B6DCB0E4B8EABEE6BAE8BC)
+, .INIT_29 (256'hA383A585A181A787AF8FA989AD8DAB8BB894B692BA96B490BC98C29EBE9AC09C)
+, .INIT_2A (256'h181416121A1614101C18221E1E1A201C03030505010107070F0F09090D0D0B0B)
+, .INIT_2B (256'h40343E3242363C3044384A3E463A483C2B232D2529212F27372F3129352D332B)
+, .INIT_2C (256'h08D406D20AD604D00CD812DE0EDA10DCF3C3F5C5F1C1F7C7FFCFF9C9FDCDFBCB)
+, .INIT_2D (256'h30F42EF232F62CF034F83AFE36FA38FC1BE31DE519E11FE727EF21E925ED23EB)
+, .INIT_2E (256'h7B637D6579617F67876F8169856D836B90748E7292768C7094789A7E967A987C)
+, .INIT_2F (256'h53435545514157475F4F59495D4D5B4B685466526A5664506C58725E6E5A705C)
+, .INIT_30 (256'hE0A4DEA2E2A6DCA0E4A8EAAEE6AAE8ACF5B3F7B5F3B1F9B701BFFBB9FFBDFDBB)
+, .INIT_31 (256'hB484B282B686B080B888BE8EBA8ABC8CC993CB95C791CD97D59FCF99D39DD19B)
+, .INIT_32 (256'h19131B1517111D17251F1F19231D211B040402020606000008080E0E0A0A0C0C)
+, .INIT_33 (256'h4533473543314937513F4B394F3D4D3B30242E2232262C2034283A2E362A382C)
+, .INIT_34 (256'h21D323D51FD125D72DDF27D92BDD29DB0CC40AC20EC608C010C816CE12CA14CC)
+, .INIT_35 (256'h4DF34FF54BF151F759FF53F957FD55FB38E436E23AE634E03CE842EE3EEA40EC)
+, .INIT_36 (256'h886486628A6684608C68926E8E6A906C9D739F759B71A177A97FA379A77DA57B)
+, .INIT_37 (256'h5C445A425E4658406048664E624A644C715373556F5175577D5F77597B5D795B)
+, .INIT_38 (256'hDFA3E1A5DDA1E3A7EBAFE5A9E9ADE7ABF6B4F4B2F8B6F2B0FAB800BEFCBAFEBC)
+, .INIT_39 (256'hB383B585B181B787BF8FB989BD8DBB8BCA94C892CC96C690CE98D49ED09AD29C)
+, .INIT_3A (256'h1A1418121C1616101E18241E201A221C03030505010107070F0F09090D0D0B0B)
+, .INIT_3B (256'h46344432483642304A38503E4C3A4E3C2F2331252D2133273B2F3529392D372B)
+, .INIT_3C (256'h22D420D224D61ED026D82CDE28DA2ADC0BC30DC509C10FC717CF11C915CD13CB)
+, .INIT_3D (256'h4EF44CF250F64AF052F858FE54FA56FC37E339E535E13BE743EF3DE941ED3FEB)
+, .INIT_3E (256'h8763896585618B67936F8D69916D8F6B9E749C72A0769A70A278A87EA47AA67C)
+, .INIT_3F (256'h5B435D4559415F47674F6149654D634B7254705274566E5076587C5E785A7A5C)
+, .INITP_00 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)
+, .INITP_01 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)
+, .INITP_02 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)
+, .INITP_03 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)
+, .INITP_04 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)
+, .INITP_05 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)
+, .INITP_06 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)
+, .INITP_07 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)

input_data/clt_tile22_x1489_y951.dat

+// Pixels input range: 0.000000 ... 390.304718
+//1490.0	951.0	
+//Full Bayer fpga tile data
+177d 2fbe 19b7  2941 16c6 288f 1899 3143 1d9d 3c50 1e6e 4236 1c09 3fa9 2155 493c 23e9 3ed5 1cd6  39e8 19bd 294b 
+379e 18f8 3370  150d 3443 1618 36c9 15bf 36c9 1ba0 3ea6 1f33 4248 1c68 4337 1e66 4603 21b1 3dc6  2008 3b20 1842 
+1a79 2aa7 14ab  2527 1453 25d2 1351 2529 13fd 2944 1a1b 3dfb 1d9f 4082 1c6f 377c 1ba6 3b85 1da2  3b88 2157 3e03 
+
+3879 14b4 3443  14b5 35ef 1565 3372 13b3 30ff 14b6 395d 1d97 4334 1b3f 3ce0 16d0 3520 1787 3c01  18a0 3eab 2008 
+12fa 1ff6 13fc  2941 1503 2c17 14ab 247e 14ab 2730 1a1b 3844 1ed6 4235 16c9 252d 166e 2ab0 1457  27e7 17e0 314b 
+329b 145d 3958  16cc 37a0 18f9 35f2 195a 3dbe 1b3d 415d 1d97 638a 5ce5 4cbc 195c 3883 16d0 32a7  1676 3962 161c 
+1721 2e43 166a  2b5f 13a5 29f5 1c6c 3775 1e04 3452 195a 35e4 261c 6e90 1e07 3ab3 1e07 36b0 183e  2cda 1507 2333 
+3879 150c 329e  14b5 3518 189b 3a39 1b3d 3bf8 195a 5c00 1e64 4334 189d 4424 26e6 5e26 1ecd 3dc6  18a0 37aa 1361 
+134f 2329 13a5  288e 1a18 313f 19b8 3082 1454 2c19 6194 6a51 1a7c 2893 1a7e 4856 5216 4dc4 1ed9  2d94 13a9 29fe 
+31cb 12b4 35ef  1727 3958 17e0 3cda 189c 37a3 16cd 46f2 183f 3cdd 1ba1 4161 1ecd 4fb2 2006 4516  1c07 3b20 1adf 
+1669 293e 177e  29f4 1503 288e 1351 21e1 14ab 2528 1505 2d8f 1a1b 3d25 1ae0 3087 1a1c 3914 1da2  3b87 17e0 314a 
+31cb 1616 36c7  14b5 329e 1408 30ff 1409 35f2 150e 3881 18fc 3ea6 1add 3b1d 1ade 36cf 1ade 3ce3  1cd0 3962 19bd 
+13fb 21dd 14aa  21df 166a 313f 183b 2942 1504 25d3 155e 2945 183c 3206 16c9 2f09 183d 35e6 195c  3394 19bc 35e9 
+336e 150c 3519  1671 36c7 183d 387e 14b6 3446 1566 3448 13b4 351d 189d 35f7 15c1 3960 18fd 3a41  17e5 3886 16d1 
+15b4 27db 177e  2ccf 160f 2f01 14ab 247d 13fd 2cd2 1780 2945 17de 2fc5 13ff 252c 1725 3087 1457  21e6 13a9 2332 
+36c5 1616 329e  150d 302f 1408 3446 15bf 395b 15bf 37a5 140a 3375 19ba 344b 14b8 35f7 1568 31d6  13b6 3522 1676 
+160e 288b 15b5  27dc 1252 2098 1504 2d8b 1a19 2aaa 1352 1ffa 1455 2e49 1255 252b 14ad 2733 1457  27e5 12fe 228b 
+30fb 14b4 3030  1565 37a1 135d 2dd1 14b6 3446 1409 2e9d 1619 3449 189d 31d4 130b 32a5 161b 337a  1462 3039 116f 
+13fb 1e1b 13fc  213b 13a5 288d 177f 2e47 1351 25d3 12fc 1ffa 12fc 2944 1613 21e4 12fd 2733 13a9  20a0 1256 20a0 
+
+302e 120d 31cd  12b4 30fe 1b9f 4245 1c03 3372 13b3 31d2 13b4 351e 183f 3520 12b7 32a5 1461 2f6d  12b8 2d10 1361 
+134f 2281 12a6  25d1 1957 272d 1958 2d8b 166b 1f59 1352 27e1 189a 2fc4 1506 1f5d 115d 1e21 1256  1e23 12aa 23da 
+329c 111a 329e  135d 3030 145e 351c 15bf 31d0 120f 3034 12b6 3449 1674 32a5 1510 2b82 111d 2f6d  1212 31d7 11c0 
+// 28 padding 0
+0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0
+
+
+//Full Bayer fpga tile data
+177d 2fbe 19b7  2941 16c6 288f 1899 3143 1d9d 3c50 1e6e 4236 1c09 3fa9 2155 493c 23e9 3ed5 1cd6  39e8 19bd 294b 
+379e 18f8 3370  150d 3443 1618 36c9 15bf 36c9 1ba0 3ea6 1f33 4248 1c68 4337 1e66 4603 21b1 3dc6  2008 3b20 1842 
+1a79 2aa7 14ab  2527 1453 25d2 1351 2529 13fd 2944 1a1b 3dfb 1d9f 4082 1c6f 377c 1ba6 3b85 1da2  3b88 2157 3e03 
+
+3879 14b4 3443  14b5 35ef 1565 3372 13b3 30ff 14b6 395d 1d97 4334 1b3f 3ce0 16d0 3520 1787 3c01  18a0 3eab 2008 
+12fa 1ff6 13fc  2941 1503 2c17 14ab 247e 14ab 2730 1a1b 3844 1ed6 4235 16c9 252d 166e 2ab0 1457  27e7 17e0 314b 
+329b 145d 3958  16cc 37a0 18f9 35f2 195a 3dbe 1b3d 415d 1d97 638a 5ce5 4cbc 195c 3883 16d0 32a7  1676 3962 161c 
+1721 2e43 166a  2b5f 13a5 29f5 1c6c 3775 1e04 3452 195a 35e4 261c 6e90 1e07 3ab3 1e07 36b0 183e  2cda 1507 2333 
+3879 150c 329e  14b5 3518 189b 3a39 1b3d 3bf8 195a 5c00 1e64 4334 189d 4424 26e6 5e26 1ecd 3dc6  18a0 37aa 1361 
+134f 2329 13a5  288e 1a18 313f 19b8 3082 1454 2c19 6194 6a51 1a7c 2893 1a7e 4856 5216 4dc4 1ed9  2d94 13a9 29fe 
+31cb 12b4 35ef  1727 3958 17e0 3cda 189c 37a3 16cd 46f2 183f 3cdd 1ba1 4161 1ecd 4fb2 2006 4516  1c07 3b20 1adf 
+1669 293e 177e  29f4 1503 288e 1351 21e1 14ab 2528 1505 2d8f 1a1b 3d25 1ae0 3087 1a1c 3914 1da2  3b87 17e0 314a 
+31cb 1616 36c7  14b5 329e 1408 30ff 1409 35f2 150e 3881 18fc 3ea6 1add 3b1d 1ade 36cf 1ade 3ce3  1cd0 3962 19bd 
+13fb 21dd 14aa  21df 166a 313f 183b 2942 1504 25d3 155e 2945 183c 3206 16c9 2f09 183d 35e6 195c  3394 19bc 35e9 
+336e 150c 3519  1671 36c7 183d 387e 14b6 3446 1566 3448 13b4 351d 189d 35f7 15c1 3960 18fd 3a41  17e5 3886 16d1 
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+
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+// 28 padding 0
+0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0
+ 
\ No newline at end of file

mclt_test_02.sav

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+[*] Fri Dec 22 06:19:20 2017
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+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
+@28
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
+mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
+@1401200
+-mclt_wnd_mul
+@1000200
+-mclt_bayer_fold
+-mclt_bayer
+@800200
+-mono
+@22
+mclt_test_02.mclt16x16_i.mpixel_a[7:0]
+@28
+mclt_test_02.mclt16x16_i.mpixel_re
+@22
+mclt_test_02.mclt16x16_i.mpixel_d[15:0]
+@200
+-
+@1000200
+-mono
+[pattern_trace] 1
+[pattern_trace] 0