### Working on MCLT version for Bayer data, exploiting symmetry of DTT of

`checker board data (half zeros)`
parent f69ec863
This diff is collapsed.
 ... ... @@ -18,9 +18,10 @@ from __future__ import division # ''' Calculate ROM for MCLT fold indices: A0..A1 - variant, folding to the same 8x8 sample A2..A4 - sample column in folded 8x8 tile A5..A7 - sample row in folded 8x8 tile A0..A2 - sample column in folded 8x8 tile A3..A5 - sample row in folded 8x8 tile A6..A7 - variant, folding to the same 8x8 sample D0..D4 - pixel column in 16x16 tile D5..D7 - pixel row in 16x16 tile D8 - negate for mode 0 (CC) ... ... @@ -207,9 +208,9 @@ def create_fold(n = 8): # n - DCT and window size ''' Calculate ROM for MCLT fold indices: A0..A1 - variant, folding to the same 8x8 sample A2..A4 - sample column in folded 8x8 tile A5..A7 - sample row in folded 8x8 tile A0..A2 - sample column in folded 8x8 tile A3..A5 - sample row in folded 8x8 tile A6..A7 - variant, folding to the same 8x8 sample D0..D4 - pixel column in 16x16 tile D5..D7 - pixel row in 16x16 tile D8 - negate for mode 0 (CC) ... ...
 ... ... @@ -79,7 +79,7 @@ module dsp_ma_preadd #( 2'b01, 2'b01}; initial begin \$display("dsp_ma_preadd, using DSP48E1"); \$display("dsp_ma_preadd, using DSP48E1. FIXME: implement BREG=2 for undef INSTANTIATE_DSP48E1"); end DSP48E1 #( ... ...
 ... ... @@ -286,8 +286,6 @@ D11 - negate for mode 3 (SS) .clk_a (clk), // input .addr_a ({2'b0,in_cntr[1:0],in_cntr[7:2]}), // input[9:0] /// .en_a (in_busy), // input /// .regen_a (in_busy), // input .en_a (in_busy), // input .regen_a (in_busy), // input .we_a (1'b0), // input ... ... @@ -303,7 +301,7 @@ D11 - negate for mode 3 (SS) .data_in_b (18'b0) // input[17:0] ); // Latency = 5 // Latency = 6 mclt_wnd_mul #( .SHIFT_WIDTH (SHIFT_WIDTH), .COORD_WIDTH (COORD_WIDTH), ... ... @@ -315,7 +313,8 @@ D11 - negate for mode 3 (SS) .x_in (mpix_a_w[3:0]), // input[3:0] .y_in (mpix_a_w[7:4]), // input[3:0] .x_shft (x_shft_r2), // input[7:0] .y_shft (y_shft_r2), // input[7:0] .y_shft (y_shft_r2), // input[7:0] .zero_in (1'b0), // input TODO: covert from mpix_use_r? .wnd_out (window_w) // output[17:0] valid with in_busy ); ... ... @@ -349,7 +348,6 @@ D11 - negate for mode 3 (SS) ) dly_var_first_i ( .clk (clk), // input .rst (rst), // input /// .dly (4'h8), // input[3:0] .dly (4'h9), // input[3:0] .din (in_busy && (in_cntr[1:0] == 0)), // input[0:0] .dout (var_first_d) // output[0:0] ... ...
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
 ... ... @@ -43,12 +43,13 @@ module mclt_wnd_mul#( parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM parameter OUT_WIDTH = 18 // bits in window value (positive) )( input clk, //!< system clock, posedge input en, //!< re (both re and ren - just for power) input [3:0] x_in, //!< tile pixel X input [3:0] y_in, //!< tile pixel Y input clk, //!< system clock, posedge input en, //!< re (both re and ren - just for power) input [3:0] x_in, //!< tile pixel X input [3:0] y_in, //!< tile pixel Y input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y input zero_in, // set window to zero (2 cycles after other inputs) output signed [OUT_WIDTH - 1 : 0] wnd_out ); wire [COORD_WIDTH - 1 : 0] x_full; ... ... @@ -77,7 +78,7 @@ module mclt_wnd_mul#( wnd_out_x_r <= wnd_out_x; wnd_out_y_r <= wnd_out_y; // zero <= {zero, x_zero | y_zero}; zero <= x_zero | y_zero; zero <= x_zero | y_zero | zero_in; wnd_out_r <= wnd_out_w; // wnd_out_x_r * wnd_out_y_r; end ... ...