Loading sensor/sens_lepton3.v +7 −6 Original line number Diff line number Diff line Loading @@ -304,12 +304,13 @@ module sens_lepton3 #( (dbg_sel[1]?( dbg_sel[0]? dbg_sources[3]:dbg_sources[2]):( dbg_sel[0]? dbg_sources[1]: dbg_sources[0])); assign dbg_sources[0] = dbg_running; assign dbg_sources[2:1] = dbg_vsync_rdy; assign dbg_sources[3] = dbg_state[0]; // discard_segment; assign dbg_sources[4] = dbg_state[1]; // in_busy; assign dbg_sources[5] = dbg_state[2]; // out_busy; assign dbg_sources[6] = dbg_state[3]; // hact; assign dbg_sources[7] = dbg_state[4]; // dbg_will_sync; // dbg_segment_stb; // sof; assign dbg_sources[1] = dbg_will_sync; // assign dbg_sources[2] = dbg_vsync_rdy[1]; // assign dbg_sources[3] = discard_segment; // dbg_state[0]; // assign dbg_sources[4] = in_busy; // dbg_state[1]; // assign dbg_sources[5] = out_busy; // dbg_state[2]; // assign dbg_sources[6] = hact; // dbg_state[3]; // assign dbg_sources[7] = sof; // dbg_state[4]; // //dbg_will_sync dbg_state Loading sensor/vospi_segment_61.v +2 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ module vospi_segment_61#( parameter VOSPI_SEGMENT_FIRST = 1, parameter VOSPI_SEGMENT_LAST = 4, parameter VOSPI_PACKET_FIRST = 0, parameter VOSPI_PACKET_LAST = 60, parameter VOSPI_PACKET_LAST = 60, // with telemetry parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF Loading @@ -61,6 +61,7 @@ module vospi_segment_61#( input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk input vsync_use, // if set - wait for vsync to read a segment input resync_disable, // disable re-synchronizing packets using discard signature @pclk // input use_telemetry, // use 61- packets per segment (last segment = 60), 0 - 60 packets // runs a single frame // SPI signals output spi_clken, // enable clock on spi_clk Loading simulation_modules/simul_lwir160x120_vospi.v +2 −1 Original line number Diff line number Diff line Loading @@ -48,6 +48,7 @@ module simul_lwir160x120_vospi # ( parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz parameter SEGMENTS_SEQ = 8, // 12 With ITAR parameter SEGMENT_START = 7, // 0, parameter FRAME_DELAY = 100, // mclk period to start first frame 1 parameter MS_PERIOD = 25 // ahould actually be 25000 Loading Loading @@ -360,7 +361,7 @@ always @ (posedge mclk) begin if (segment_run) packed_data[copy_wa_full] <= copy_din; // copy_d; if (rst) segments_cntr <= 0; if (rst) segments_cntr <= SEGMENT_START; else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1); Loading x393_vospi.bit (5.7 MiB) File changed.No diff preview for this file type. View original file View changed file x393_vospi.timing_summary_impl +1056 −1041 File changed.Preview size limit exceeded, changes collapsed. Show changes Loading
sensor/sens_lepton3.v +7 −6 Original line number Diff line number Diff line Loading @@ -304,12 +304,13 @@ module sens_lepton3 #( (dbg_sel[1]?( dbg_sel[0]? dbg_sources[3]:dbg_sources[2]):( dbg_sel[0]? dbg_sources[1]: dbg_sources[0])); assign dbg_sources[0] = dbg_running; assign dbg_sources[2:1] = dbg_vsync_rdy; assign dbg_sources[3] = dbg_state[0]; // discard_segment; assign dbg_sources[4] = dbg_state[1]; // in_busy; assign dbg_sources[5] = dbg_state[2]; // out_busy; assign dbg_sources[6] = dbg_state[3]; // hact; assign dbg_sources[7] = dbg_state[4]; // dbg_will_sync; // dbg_segment_stb; // sof; assign dbg_sources[1] = dbg_will_sync; // assign dbg_sources[2] = dbg_vsync_rdy[1]; // assign dbg_sources[3] = discard_segment; // dbg_state[0]; // assign dbg_sources[4] = in_busy; // dbg_state[1]; // assign dbg_sources[5] = out_busy; // dbg_state[2]; // assign dbg_sources[6] = hact; // dbg_state[3]; // assign dbg_sources[7] = sof; // dbg_state[4]; // //dbg_will_sync dbg_state Loading
sensor/vospi_segment_61.v +2 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ module vospi_segment_61#( parameter VOSPI_SEGMENT_FIRST = 1, parameter VOSPI_SEGMENT_LAST = 4, parameter VOSPI_PACKET_FIRST = 0, parameter VOSPI_PACKET_LAST = 60, parameter VOSPI_PACKET_LAST = 60, // with telemetry parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF Loading @@ -61,6 +61,7 @@ module vospi_segment_61#( input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk input vsync_use, // if set - wait for vsync to read a segment input resync_disable, // disable re-synchronizing packets using discard signature @pclk // input use_telemetry, // use 61- packets per segment (last segment = 60), 0 - 60 packets // runs a single frame // SPI signals output spi_clken, // enable clock on spi_clk Loading
simulation_modules/simul_lwir160x120_vospi.v +2 −1 Original line number Diff line number Diff line Loading @@ -48,6 +48,7 @@ module simul_lwir160x120_vospi # ( parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz parameter SEGMENTS_SEQ = 8, // 12 With ITAR parameter SEGMENT_START = 7, // 0, parameter FRAME_DELAY = 100, // mclk period to start first frame 1 parameter MS_PERIOD = 25 // ahould actually be 25000 Loading Loading @@ -360,7 +361,7 @@ always @ (posedge mclk) begin if (segment_run) packed_data[copy_wa_full] <= copy_din; // copy_d; if (rst) segments_cntr <= 0; if (rst) segments_cntr <= SEGMENT_START; else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1); Loading
x393_vospi.bit (5.7 MiB) File changed.No diff preview for this file type. View original file View changed file
x393_vospi.timing_summary_impl +1056 −1041 File changed.Preview size limit exceeded, changes collapsed. Show changes