Skip to content

X
x393
Commit c4d0f3bc authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Debugging mclt bayer

parent 1b250b27
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 426 additions and 258 deletions
dsp/dsp_ma_preadd.v
View file @ c4d0f3bc
...@@ -42,7 +42,8 @@ module dsp_ma_preadd #( ...@@ -42,7 +42,8 @@ module dsp_ma_preadd #(
parameter B_WIDTH = 18, parameter B_WIDTH = 18,
parameter A_WIDTH = 25, parameter A_WIDTH = 25,
parameter P_WIDTH = 48, parameter P_WIDTH = 48,
parameter BREG = 1) // means number in series, so "2" always reads the second parameter AREG = 1,
parameter BREG = 1) // means number in series, so "2" always reads the second
( (
input clk, input clk,
input rst, input rst,
...@@ -86,7 +87,7 @@ module dsp_ma_preadd #( ...@@ -86,7 +87,7 @@ module dsp_ma_preadd #(
.ACASCREG (1), .ACASCREG (1),
.ADREG (1), .ADREG (1),
.ALUMODEREG (1), .ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second .AREG (AREG), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"), .AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"), // "DIRECT", "CASCADE" .A_INPUT ("DIRECT"), // "DIRECT", "CASCADE"
.BCASCREG (1), .BCASCREG (1),
...@@ -206,20 +207,36 @@ module dsp_ma_preadd #( ...@@ -206,20 +207,36 @@ module dsp_ma_preadd #(
generate generate
case (AREG)
1 : begin
always @(posedge clk) begin
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain;
end
end
2 : begin
always @(posedge clk) begin
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= a1_reg;
end
end
endcase
case (BREG) case (BREG)
1 : begin 1 : begin
always @(posedge clk) begin always @(posedge clk) begin
if (rst) b2_reg <= 18'b0; if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin; else if (ceb2) b2_reg <= bin;
end end
end end
2 : begin 2 : begin
always @(posedge clk) begin always @(posedge clk) begin
if (rst) b2_reg <= 18'b0; if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= b1_reg; else if (ceb2) b2_reg <= b1_reg;
end end
end end
endcase endcase
endgenerate endgenerate
...@@ -228,14 +245,14 @@ module dsp_ma_preadd #( ...@@ -228,14 +245,14 @@ module dsp_ma_preadd #(
else if (ceb1) b1_reg <= bin; else if (ceb1) b1_reg <= bin;
if (rst) b2_reg <= 0; // if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin; // else if (ceb2) b2_reg <= bin;
if (rst) a1_reg <= 0; if (rst) a1_reg <= 0;
else if (cea1) a1_reg <= ain; else if (cea1) a1_reg <= ain;
if (rst) a2_reg <= 0; // if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain; // else if (cea2) a2_reg <= ain;
if (rst) d_reg <= 0; if (rst) d_reg <= 0;
else if (ced) d_reg <= din; else if (ced) d_reg <= din;
......
dsp/mclt16x16_bayer.v
View file @ c4d0f3bc
This diff is collapsed.
dsp/mclt_bayer_fold.v
View file @ c4d0f3bc
...@@ -42,7 +42,7 @@ module mclt_bayer_fold#( ...@@ -42,7 +42,7 @@ module mclt_bayer_fold#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional) parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
// parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency // parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency
// parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
// parameter PIXEL_WIDTH = 16, // input pixel width (unsigned) // parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18 // input pixel width (unsigned) parameter WND_WIDTH = 18 // input pixel width (unsigned)
...@@ -71,12 +71,15 @@ module mclt_bayer_fold#( ...@@ -71,12 +71,15 @@ module mclt_bayer_fold#(
output pix_page, //!< copy pixel page (should be externally combined with first color) output pix_page, //!< copy pixel page (should be externally combined with first color)
output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive
output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
output [14:0] phases, //!< other signals // output [14:0] phases, //!< other signals
output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker) output [6:0] phases, //!< other signals
output var_pre2_first,//!< two ahead of first of 2 fold variants (4 for monochrome, 2 left for checker)
// output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker)
output reg pre_last_in //!< pre last data in output reg pre_last_in //!< pre last data in
); );
reg [6:0] in_cntr; // input phase counter reg [6:0] in_cntr; // input phase counter
reg [14:0] run_r; // run phase // reg [14:0] run_r; // run phase
reg [6:0] run_r; // run phase
reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr) reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
...@@ -102,8 +105,9 @@ module mclt_bayer_fold#( ...@@ -102,8 +105,9 @@ module mclt_bayer_fold#(
wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out
wire var_first_d; // adding subtracting first variant of 2 folds wire var_first_d; // adding subtracting first variant of 2 folds
// reg var_pre_first;
assign phases = run_r; assign phases = run_r;
assign var_pre2_first = var_first_d;
// wire [ 3:0] bayer_1hot = { mpix_a_w[4] & mpix_a_w[0], // wire [ 3:0] bayer_1hot = { mpix_a_w[4] & mpix_a_w[0],
// mpix_a_w[4] & ~mpix_a_w[0], // mpix_a_w[4] & ~mpix_a_w[0],
...@@ -117,7 +121,8 @@ module mclt_bayer_fold#( ...@@ -117,7 +121,8 @@ module mclt_bayer_fold#(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst) run_r <= 0; if (rst) run_r <= 0;
else run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))}; // else run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
else run_r <= {run_r[5:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
if (!run_r[0]) in_cntr <= 0; if (!run_r[0]) in_cntr <= 0;
else in_cntr <= in_cntr + 1; else in_cntr <= in_cntr + 1;
...@@ -144,11 +149,14 @@ module mclt_bayer_fold#( ...@@ -144,11 +149,14 @@ module mclt_bayer_fold#(
/// if (in_cntr == 2) valid_rows_r <= valid_rows_r0; /// if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
/// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]); /// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);
/// if (run_r[9]) var_pre_first <= var_first_d;
if (run_r[10]) begin /// if (run_r[10]) begin
var_first <= var_first_d; // var_first <= var_first_d;
end /// var_first <= var_pre_first;
/// end
pre_last_in <= in_cntr[6:0] == 7'h7d; pre_last_in <= in_cntr[6:0] == 7'h7d;
...@@ -184,32 +192,19 @@ module mclt_bayer_fold#( ...@@ -184,32 +192,19 @@ module mclt_bayer_fold#(
); );
// Matching window latency with pixel data latency // Matching window latency with pixel data latency
wire [3:0] addr_dly = ADDR_DLY;
dly_var #( dly_var #(
.WIDTH(11), .WIDTH(11),
.DLY_WIDTH(4) .DLY_WIDTH(4)
) dly_pixel_addr_i ( ) dly_pixel_addr_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher // .dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher
.dly (addr_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({pre_page, run_r[3], pix_a_r}), // input[0:0] .din ({pre_page, run_r[3], pix_a_r}), // input[0:0]
.dout ({pix_page, pix_re, pix_addr}) // output[0:0] .dout ({pix_page, pix_re, pix_addr}) // output[0:0]
); );
/*
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_blank_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h0), // TODO: put correct value!
.din (blank_r), // input[0:0]
.dout (blank_d) // output[0:0]
);
*/
// Latency = 6 // Latency = 6
mclt_wnd_mul #( mclt_wnd_mul #(
.SHIFT_WIDTH (SHIFT_WIDTH), .SHIFT_WIDTH (SHIFT_WIDTH),
...@@ -243,7 +238,8 @@ module mclt_bayer_fold#( ...@@ -243,7 +238,8 @@ module mclt_bayer_fold#(
) dly_var_first_i ( ) dly_var_first_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h9), // input[3:0] // .dly (4'h9), // input[3:0]
.dly (4'h8), // input[3:0]
.din (run_r[0] && (in_cntr[0] == 0)), // input[0:0] .din (run_r[0] && (in_cntr[0] == 0)), // input[0:0]
.dout (var_first_d) // output[0:0] .dout (var_first_d) // output[0:0]
); );
......
dsp/phase_rotator.v
View file @ c4d0f3bc
...@@ -80,7 +80,9 @@ module phase_rotator#( ...@@ -80,7 +80,9 @@ module phase_rotator#(
// 0xxxxxx (>0) nnn s s xxxxxx nnn 0 0 // 0xxxxxx (>0) nnn s s xxxxxx nnn 0 0
reg [5:0] start_d; // delayed versions of start (TODO: adjust length) reg [5:0] start_d; // delayed versions of start (TODO: adjust length)
reg [7:0] cntr_h; // input sample counter reg [7:0] cntr_h_consec; // input sample counter
wire [7:0] cntr_h = DECIMATE ? {cntr_h_consec[6:2], ODD ? 1'b1: 1'b0, cntr_h_consec[1:0]}: cntr_h_consec;
reg run_h; reg run_h;
wire [7:0] cntr_v; // delayed sample counter wire [7:0] cntr_v; // delayed sample counter
wire run_v; wire run_v;
...@@ -117,12 +119,12 @@ module phase_rotator#( ...@@ -117,12 +119,12 @@ module phase_rotator#(
if (start_d[3]) shift_vr <= shift_v0; if (start_d[3]) shift_vr <= shift_v0;
if (start_d[4]) inv_checker_r2 <= inv_checker_r; if (start_d[4]) inv_checker_r2 <= inv_checker_r;
if (rst) run_h <= 0; if (rst) run_h <= 0;
else if (start) run_h <= 1; else if (start) run_h <= 1;
else if (&cntr_h[7:1] && (cntr_h[0] || DECIMATE)) run_h <= 0; else if (&cntr_h_consec[6:0] && (cntr_h[7] || DECIMATE)) run_h <= 0;
if (!run_h) cntr_h <= ODD; if (!run_h) cntr_h_consec <= 0;
else cntr_h <= cntr_h + (1 << DECIMATE); else cntr_h_consec <= cntr_h_consec + 1;
// combine horizontal and vertical counters and shifts to feed to ROM // combine horizontal and vertical counters and shifts to feed to ROM
hv_index <= mux_v ? cntr_v[4:2] : cntr_h[7:5]; // input data "down first" (transposed) hv_index <= mux_v ? cntr_v[4:2] : cntr_h[7:5]; // input data "down first" (transposed)
...@@ -247,7 +249,7 @@ module phase_rotator#( ...@@ -247,7 +249,7 @@ module phase_rotator#(
fd_dv <= pre_dv; fd_dv <= pre_dv;
if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH]; if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH];
pre_first_out <= cntr_h[7:0] == 8'hd; pre_first_out <= cntr_h_consec[7:0] == 8'hd;
end end
......
mclt_test_02.sav
View file @ c4d0f3bc
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment