Finished converting event_logger to use serial (byte-parallal) timestamp messages (c2b29afd) · Commits · Elphel / x393

logger/event_logger.v

+12 −96

Original line number	Original line	Diff line number	Diff line
	@@ -60,18 +60,15 @@ module event_logger#(
	output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]		output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
	output status_rq, // input request to send status downstream		output status_rq, // input request to send status downstream
	input status_start, // Acknowledge of the first status packet byte (address)		input status_start, // Acknowledge of the first status packet byte (address)
	// input we, // write enable (lower 16 bits, high - next cycle)
	// input wa, // write address(1)/data(0)		output ts_local_snap, // @posedge xclk request to take a local time snapshot
	// input [15:0] di, // 16-bit data in (32 multiplexed)		input ts_local_stb, // @posedge xclk one clock pulse before receiving a local TS data
	input [19:0] usec, // un-latched timestamp microseconds		input [7:0] ts_local_data, // @posedge xclk local timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
	input [31:0] sec, // un-latched timestamp seconds
	input [GPIO_N-1:0] ext_di,		input [GPIO_N-1:0] ext_di,
	output [GPIO_N-1:0] ext_do,		output [GPIO_N-1:0] ext_do,
	output [GPIO_N-1:0] ext_en,		output [GPIO_N-1:0] ext_en,

	// input [31:0] ts_rcv_sec, // [31:0] timestamp seconds received over the sync line
	// input [19:0] ts_rcv_usec, // [19:0] timestamp microseconds received over the sync line
	// input ts_stb, // strobe when received timestamp is valid - single negedge sclk cycle

	// byte-parallel timestamps from 4 sesnors channels (in triggered mode all are the same, different only in free running mode)		// byte-parallel timestamps from 4 sesnors channels (in triggered mode all are the same, different only in free running mode)
	// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds		// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
	@@ -112,7 +109,6 @@ module event_logger#(
	reg we_period;		reg we_period;
	reg we_bit_duration;		reg we_bit_duration;
	reg we_message;		reg we_message;
	// reg we_config;
	reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]		reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
	reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable		reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
	reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable		reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
	@@ -121,15 +117,10 @@ module event_logger#(
	reg we_config_debug; // bit 14, 15 - enable - enable logging external timestamps		reg we_config_debug; // bit 14, 15 - enable - enable logging external timestamps
	reg we_bitHalfPeriod;		reg we_bitHalfPeriod;

	// reg we_config_rst; // bit 16, 17 - enable - reset modules
	// reg we_config_debug; // bits 21:18, 22 - enable
	// reg [15:0] di_d;
	// reg di_d2;

	reg [1:0] config_imu;		reg [1:0] config_imu;
	reg [3:0] config_gps;		reg [3:0] config_gps;
	reg [4:0] config_msg;		reg [4:0] config_msg;
	// reg [3:0] config_syn;
	reg config_rst;		reg config_rst;
	reg [3:0] config_debug;		reg [3:0] config_debug;
	reg [15:0] bitHalfPeriod;// serial gps speed - number of xclk pulses in half bit period		reg [15:0] bitHalfPeriod;// serial gps speed - number of xclk pulses in half bit period
	@@ -138,7 +129,6 @@ module event_logger#(
	wire we_config_imu_xclk; // copy config_imu_mclk (@mclk) to config_imu (@xclk)		wire we_config_imu_xclk; // copy config_imu_mclk (@mclk) to config_imu (@xclk)
	wire we_config_gps_xclk;		wire we_config_gps_xclk;
	wire we_config_msg_xclk;		wire we_config_msg_xclk;
	// wire we_config_syn_xclk;
	wire we_config_rst_xclk;		wire we_config_rst_xclk;
	wire we_config_debug_xclk;		wire we_config_debug_xclk;
	wire we_bitHalfPeriod_xclk;		wire we_bitHalfPeriod_xclk;
	@@ -153,27 +143,13 @@ module event_logger#(
	reg [3:0] config_debug_mclk;		reg [3:0] config_debug_mclk;
	reg [15:0] bitHalfPeriod_mclk;		reg [15:0] bitHalfPeriod_mclk;

	// reg [1:0] config_imu_pre;
	// reg [3:0] config_gps_pre;
	// reg [4:0] config_msg_pre;
	// reg config_syn_pre;
	// reg config_rst_pre;
	// reg [3:0] config_debug_pre;


	reg enable_gps;		reg enable_gps;
	reg enable_msg;		reg enable_msg;
	// reg [3:0] enable_syn;
	wire [3:0] enable_syn_mclk;		wire [3:0] enable_syn_mclk;

	reg enable_timestamps;		reg enable_timestamps;
	wire message_trig;		wire message_trig;

	// reg ts_stb_rq;
	// reg [1:0] ext_ts_stb;

	// wire ts_stb_xclk; // re-clocked to posedge xclk

	wire gps_ts_stb, ser_do,ser_do_stb;		wire gps_ts_stb, ser_do,ser_do_stb;
	wire [15:0] imu_data;		wire [15:0] imu_data;
	wire [15:0] nmea_data;		wire [15:0] nmea_data;
	@@ -216,24 +192,6 @@ module event_logger#(
	wire cmd_we;		wire cmd_we;
	wire cmd_status;		wire cmd_status;



	/*
	assign ext_en[11:0]= {5'b0,
	(config_imu[1:0]==2'h3)?1'b1:1'b0,
	1'b0,
	(config_imu[1:0]==2'h2)?1'b1:1'b0,
	1'b0,
	(config_imu[1:0]==2'h1)?1'b1:1'b0,
	(config_imu[1:0]!=2'h0)?{sda_en,scl_en}:2'h0};
	assign ext_do[11:0]= {5'b0,
	(config_imu[1:0]==2'h3)?mosi:1'b0,
	1'b0,
	(config_imu[1:0]==2'h2)?mosi:1'b0,
	1'b0,
	(config_imu[1:0]==2'h1)?mosi:1'b0,
	(config_imu[1:0]!=2'h0)?{sda,scl}:2'h0};
	*/
	assign ext_en = {{(GPIO_N-5){1'b0}},		assign ext_en = {{(GPIO_N-5){1'b0}},
	(config_imu[1:0]==2'h2)?1'b1:1'b0,		(config_imu[1:0]==2'h2)?1'b1:1'b0,
	1'b0,		1'b0,
	@@ -252,33 +210,11 @@ module event_logger#(
	assign ser_di= config_gps[1]?		assign ser_di= config_gps[1]?
	(config_gps[0]?1'b0 :ext_di[4]):		(config_gps[0]?1'b0 :ext_di[4]):
	(config_gps[0]?ext_di[2]:1'b0);		(config_gps[0]?ext_di[2]:1'b0);
	// if (we_config_gps) config_gps_mclk[3:0] <= di_d[ 6:3]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable

	assign gps_pulse1sec=config_gps[2]^(config_gps[1]?		assign gps_pulse1sec=config_gps[2]^(config_gps[1]?
	(config_gps[0]?1'b0 :ext_di[5]):		(config_gps[0]?1'b0 :ext_di[5]):
	(config_gps[0]?ext_di[3]:1'b0));		(config_gps[0]?ext_di[3]:1'b0));

	//sngl_wire
	/*
	// always @(config_msg[3:0] or ext_di[11:0]) begin
	always @* begin
	case (config_msg[3:0])
	4'h0: pre_message_trig = ext_di[0];
	4'h1: pre_message_trig = ext_di[1];
	4'h2: pre_message_trig = ext_di[2];
	4'h3: pre_message_trig = ext_di[3];
	4'h4: pre_message_trig = ext_di[4];
	4'h5: pre_message_trig = ext_di[5];
	4'h6: pre_message_trig = ext_di[6];
	4'h7: pre_message_trig = ext_di[7];
	4'h8: pre_message_trig = ext_di[8]; // internal optocoupler, use invert 5'h18
	4'h9: pre_message_trig = ext_di[9];
	4'ha: pre_message_trig = ext_di[10];// external optocoupler, use invert 5'h1a
	4'hb: pre_message_trig = ext_di[10];
	default:pre_message_trig = 1'b0;
	endcase
	end
	*/
	assign pre_message_trig = ext_di16[config_msg[3:0]];		assign pre_message_trig = ext_di16[config_msg[3:0]];

	assign message_trig= config_msg[4]^pre_message_trig;		assign message_trig= config_msg[4]^pre_message_trig;
	@@ -302,18 +238,6 @@ module event_logger#(
	end		end


	// re-sync single pulse @ negedge sclk - ts_stb to @posedge xclk
	/*
	always @ (posedge ext_ts_stb[1] or negedge mclk) begin
	if (ext_ts_stb[1]) ts_stb_rq <= 1'b0;
	else if (config_rst_mclk) ts_stb_rq <= 1'b0;
	else if (ts_stb) ts_stb_rq <= 1'b1;
	end
	always @ (posedge xclk) begin
	ext_ts_stb[1:0] <= {ext_ts_stb[0] & ~ext_ts_stb[1],ts_stb_rq};
	end
	*/

	always @ (posedge mclk) begin // was negedge		always @ (posedge mclk) begin // was negedge
	if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;		if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
	we_d <= cmd_we && !cmd_a;		we_d <= cmd_we && !cmd_a;
	@@ -350,13 +274,10 @@ module event_logger#(
	if (we_config_imu_xclk) config_imu <= config_imu_mclk;		if (we_config_imu_xclk) config_imu <= config_imu_mclk;
	if (we_config_gps_xclk) config_gps <= config_gps_mclk;		if (we_config_gps_xclk) config_gps <= config_gps_mclk;
	if (we_config_msg_xclk) config_msg <= config_msg_mclk;		if (we_config_msg_xclk) config_msg <= config_msg_mclk;
	// if (we_config_syn_xclk) config_syn <= config_syn_mclk;
	if (we_config_rst_xclk) config_rst <= config_rst_mclk;		if (we_config_rst_xclk) config_rst <= config_rst_mclk;
	if (we_config_debug_xclk) config_debug <= config_debug_mclk;		if (we_config_debug_xclk) config_debug <= config_debug_mclk;
	// enable_gps <= (config_gps[1:0] != 2'h0) && !config_rst;
	enable_gps <= (^config_gps[1:0]) && !config_rst; // both 00 and 11 - disable		enable_gps <= (^config_gps[1:0]) && !config_rst; // both 00 and 11 - disable
	enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst;		enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst;
	// enable_syn <= config_rst? 4'b0 : config_syn;
	enable_timestamps <= !config_rst;		enable_timestamps <= !config_rst;
	end		end

	@@ -374,19 +295,14 @@ module event_logger#(
	16'h0); // replace 16'h0 with some pattern to debug output		16'h0); // replace 16'h0 with some pattern to debug output
	end		end

	// pulse_cross_clock i_ts_stb_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ts_stb), .out_pulse(ts_stb_xclk),.busy());
	// generate strobes to copy configuration data from mclk to xclk domain		// generate strobes to copy configuration data from mclk to xclk domain
	pulse_cross_clock i_we_config_imu_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());		pulse_cross_clock i_we_config_imu_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_imu), .out_pulse(we_config_imu_xclk),.busy());
	pulse_cross_clock i_we_config_gps_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());		pulse_cross_clock i_we_config_gps_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_gps), .out_pulse(we_config_gps_xclk),.busy());
	pulse_cross_clock i_we_config_msg_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());		pulse_cross_clock i_we_config_msg_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_msg), .out_pulse(we_config_msg_xclk),.busy());
	// pulse_cross_clock i_we_config_syn_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_syn), .out_pulse(we_config_syn_xclk),.busy());
	pulse_cross_clock i_we_config_rst_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());		pulse_cross_clock i_we_config_rst_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_rst), .out_pulse(we_config_rst_xclk),.busy());
	pulse_cross_clock i_we_config_debug_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());		pulse_cross_clock i_we_config_debug_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_config_debug), .out_pulse(we_config_debug_xclk),.busy());
	pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());		pulse_cross_clock i_we_bitHalfPeriod_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(we_bitHalfPeriod), .out_pulse(we_bitHalfPeriod_xclk),.busy());




	cmd_deser #(		cmd_deser #(
	.ADDR (LOGGER_ADDR),		.ADDR (LOGGER_ADDR),
	.ADDR_MASK (LOGGER_MASK),		.ADDR_MASK (LOGGER_MASK),
	@@ -480,15 +396,15 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
	.rdata (extts_data[15:0])); // data out (16 bits)		.rdata (extts_data[15:0])); // data out (16 bits)

	imu_timestamps393 i_imu_timestamps (		imu_timestamps393 i_imu_timestamps (
	.sclk (mclk), // 160MHz, negedge
	.xclk (xclk), // 80 MHz, posedge		.xclk (xclk), // 80 MHz, posedge
	.rst (!enable_timestamps), // reset (@posedge xclk)		.rst (!enable_timestamps), // reset (@posedge xclk)
	.sec (sec[31:0]), // running seconds (@negedge sclk)		.ts_snap (ts_local_snap), // output (@posedge xclk) - get local TS snapshot
	.usec (usec[19:0]), // running microseconds (@negedge sclk)		.ts_stb (ts_local_stb), // input (@posedge xclk) - 1 xclk before local ts data
	.ts_rq (timestamp_request_long[3:0]), // requests to create timestamps (4 channels), @posedge xclk		.ts_data (ts_local_data), // input[7:0] (@posedge xclk) - local TS data
	.ts_ackn (timestamp_ackn[3:0]), // timestamp for this channel is stored		.ts_rq (timestamp_request_long[3:0]), // input[3:0] requests to create timestamps (4 channels), @posedge xclk
	.ra ({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high		.ts_ackn (timestamp_ackn[3:0]), // output[3:0] timestamp for this channel is stored
	.dout (timestamps_rdata[15:0])); // output data		.ra ({channel[1:0],timestamp_sel[1:0]}), // input[3:0]read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
			.dout (timestamps_rdata[15:0])); // output[15:0] output data

	wire debug_unused_a; // SuppressThisWarning Veditor (unused)		wire debug_unused_a; // SuppressThisWarning Veditor (unused)
	rs232_rcv393 i_rs232_rcv (		rs232_rcv393 i_rs232_rcv (

logger/imu_exttime393.v

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -101,11 +101,11 @@ module imu_exttime393(

	if (pre_copy_w) sel_chn <= chn_enc_w;		if (pre_copy_w) sel_chn <= chn_enc_w;

	if (!copy_selected[1]) copy_cntr <= 0;		if (!copy_selected[1]) copy_cntr <= 4; // reverse order - timestamp message start with seconds, here usec first
	else copy_cntr <= copy_cntr + 1;		else copy_cntr <= copy_cntr + 1;

	copy_data_r <= copy_data; // previous data is low byte		copy_data_r <= copy_data; // previous data is low byte
	// write x16 timestamp data to RAM, inser channel number into unused microseconds byte		// write x16 timestamp data to RAM, insert channel number into unused microseconds byte
	if (copy_selected[1] && copy_cntr[0]) ts_ram[copy_cntr[2:1]] <= {copy_selected[0]?copy_data:{6'b0,sel_chn},copy_data_r};		if (copy_selected[1] && copy_cntr[0]) ts_ram[copy_cntr[2:1]] <= {copy_selected[0]?copy_data:{6'b0,sel_chn},copy_data_r};

	end		end

logger/imu_timestamps393.v

+68 −125

Original line number	Original line	Diff line number	Diff line
	@@ -21,132 +21,75 @@
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module imu_timestamps393(		module imu_timestamps393(
	sclk, // 160MHz, negedge		input xclk, // 80 MHz, posedge
	xclk, // 80 MHz, posedge		input rst, // sync reset (@posedge xclk)
	rst, // reset (@posedge xclk)		output reg ts_snap, // request to take a local time snapshot
	sec, // running seconds (@negedge sclk)		input ts_stb, // one clock pulse before receiving a local TS data
	usec, // running microseconds (@negedge sclk)		input [7:0] ts_data, // local timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
	ts_rq,// requests to create timestamps (4 channels), @posedge xclk
	ts_ackn, // timestamp for this channel is stored
	ra, // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
	dout);// output data
	input sclk;
	input xclk;
	input rst;
	input [31:0] sec;
	input [19:0] usec;
	input [ 3:0] ts_rq;
	output [ 3:0] ts_ackn;
	input [ 3:0] ra;
	output [15:0] dout;

	reg [31:0] sec_latched;
	reg [19:0] usec_latched;
	reg [15:0] ts_mux;

	reg [ 3:0] wa;
	reg srst;
	reg [3:0] rq_d;
	reg [3:0] rq_d2;
	reg [3:0] rq_r;
	reg [3:0] rq_sclk;
	reg [3:0] rq_sclk2;
	reg [3:0] pri_sclk;
	reg [3:0] pri_sclk_d;
	reg [3:0] rst_rq;
	reg [9:0] proc;
	wire wstart;
	reg we;
	wire [3:0] wrst_rq;
	reg [3:0] ts_preackn;
	reg [3:0] ts_ackn;
	assign wstart=\|pri_sclk[3:0] && (pri_sclk[3:0] != pri_sclk_d[3:0]);
	assign wrst_rq[3:0]={wa[3]&wa[2],wa[3]&~wa[2],~wa[3]&wa[2],~wa[3]&~wa[2]} & {4{proc[5]}};
	always @ (posedge xclk) begin
	rq_d[3:0] <= ts_rq[3:0];
	rq_d2[3:0] <= rq_d[3:0];
	end

	always @ (negedge sclk) begin		input [3:0] ts_rq,// requests to create timestamps (4 channels), @posedge xclk
	srst <= rst;		output [3:0] ts_ackn, // timestamp for this channel is stored
	rq_sclk[3:0] <= srst?4'h0:(~rst_rq[3:0] & (rq_r[3:0] \| rq_sclk[3:0])) ;		input [3:0] ra, // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
	rq_sclk2[3:0] <= srst?4'h0:(~rst_rq[3:0] & rq_sclk[3:0]) ;		output [15:0] dout);// output data
	pri_sclk[3:0] <= {rq_sclk2[3] & ~\|rq_sclk2[2:0],		reg ts_rcv;
	rq_sclk2[2] & ~\|rq_sclk2[1:0],		reg ts_busy;
	rq_sclk2[1] & ~rq_sclk2[0],		reg [1:0] chn; // channel for which timestamp is bein requested/received
	rq_sclk2[0]};		wire [3:0] rq_pri; // 1-hot prioritized timestamp request
	pri_sclk_d[3:0] <= pri_sclk[3:0];		wire [1:0] rq_enc; // encoded request channel
	proc[9:0] <= {proc[9:0], wstart};		reg [2:0] cntr; // ts rcv counter
	if (proc[0]) wa[3:2] <= {\|pri_sclk_d[3:2], pri_sclk_d[3] \| pri_sclk_d[1]};		wire pre_snap;
	if (proc[0]) sec_latched[31:0] <= sec[31:0];		reg [7:0] ts_data_r; // previous value of ts_data
	if (proc[0]) usec_latched[19:0] <= usec[19:0];		reg [15:0] ts_ram[0:15];
	// if (proc[2]) ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec[19:16]};		reg rcv_last; // receiving last byte (usec MSB)
	casex({proc[8],proc[6],proc[4],proc[2]})		reg [3:0] ts_ackn_r;
	// 4'bXXX1: ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec_latched[19:16]};		wire [3:0] chn1hot;
	// 4'bXX1X: ts_mux[15:0] <= usec_latched[15: 0];		wire pre_ackn;
	// 4'bX1XX: ts_mux[15:0] <= sec_latched[31:16];
	// 4'b1XXX: ts_mux[15:0] <= sec_latched[15: 0];		assign rq_pri = {ts_rq[3] & ~(\|ts_rq[2:0]),
	4'bXXX1: ts_mux[15:0] <= usec_latched[15: 0];		ts_rq[2] & ~(\|ts_rq[1:0]),
	4'bXX1X: ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec_latched[19:16]};		ts_rq[1] & ~ ts_rq[0],
	4'bX1XX: ts_mux[15:0] <= sec_latched[15: 0];		ts_rq[0]};
	4'b1XXX: ts_mux[15:0] <= sec_latched[31:16];		assign rq_enc = {rq_pri[3] \| rq_pri[2],
			rq_pri[3] \| rq_pri[1]};
	endcase
	we <= proc[3] \|\| proc[5] \|\| proc[7] \|\| proc[9];		assign pre_snap = (\|ts_rq) && !ts_busy;
	if (proc[2]) wa[1:0] <= 2'b0;		assign chn1hot = {chn[1] & chn[0], chn[1] & ~chn[0], ~chn[1] & chn[0], ~chn[1] & ~chn[0]};
	else if (we) wa[1:0] <= wa[1:0] + 1;		assign pre_ackn = ts_rcv && (cntr == 3'h6);
	rst_rq[3:0] <= wrst_rq[3:0] \| {4{srst}};
	end
	always @ (posedge xclk or posedge rq_sclk2[0]) begin		assign ts_ackn = ts_ackn_r;
	if (rq_sclk2[0]) rq_r[0] <= 1'b0;
	else if (srst) rq_r[0] <= 1'b0;
	else if (rq_d[0] && !rq_d2[0]) rq_r[0] <= 1'b1;
	end
	always @ (posedge xclk or posedge rq_sclk2[1]) begin
	if (rq_sclk2[1]) rq_r[1] <= 1'b0;
	else if (srst) rq_r[1] <= 1'b0;
	else if (rq_d[1] && !rq_d2[1]) rq_r[1] <= 1'b1;
	end
	always @ (posedge xclk or posedge rq_sclk2[2]) begin
	if (rq_sclk2[2]) rq_r[2] <= 1'b0;
	else if (srst) rq_r[2] <= 1'b0;
	else if (rq_d[2] && !rq_d2[2]) rq_r[2] <= 1'b1;
	end
	always @ (posedge xclk or posedge rq_sclk2[3]) begin
	if (rq_sclk2[3]) rq_r[3] <= 1'b0;
	else if (srst) rq_r[3] <= 1'b0;
	else if (rq_d[3] && !rq_d2[3]) rq_r[3] <= 1'b1;
	end

	always @ (posedge xclk or posedge rst_rq[0]) begin
	if (rst_rq[0]) ts_preackn[0] <= 1'b1;
	else if (!ts_rq[0]) ts_preackn[0] <= 1'b0;
	end
	always @ (posedge xclk or posedge rst_rq[1]) begin
	if (rst_rq[1]) ts_preackn[1] <= 1'b1;
	else if (!ts_rq[1]) ts_preackn[1] <= 1'b0;
	end
	always @ (posedge xclk or posedge rst_rq[2]) begin
	if (rst_rq[2]) ts_preackn[2] <= 1'b1;
	else if (!ts_rq[2]) ts_preackn[2] <= 1'b0;
	end
	always @ (posedge xclk or posedge rst_rq[3]) begin
	if (rst_rq[3]) ts_preackn[3] <= 1'b1;
	else if (!ts_rq[3]) ts_preackn[3] <= 1'b0;
	end

	always @ (posedge xclk) begin		always @ (posedge xclk) begin
	ts_ackn[3:0] <= ts_preackn[3:0] & ts_rq[3:0];		ts_snap <= pre_snap && !rst;

			if (ts_rcv) ts_data_r <= ts_data;

			if (rst) ts_busy <= 0;
			else if (pre_snap) ts_busy <= 1;
			else if (ts_rcv && (cntr == 3'h6)) ts_busy <= 0; // adjust 6?

			rcv_last <= ts_rcv && (cntr == 3'h6);

			if (rst) ts_rcv <= 0;
			else if (ts_stb) ts_rcv <= 1;
			else if (rcv_last) ts_rcv <= 0;

			if (!rcv) cntr <= 0;
			else cntr <= cntr + 1;
			if (pre_snap) chn <= rq_enc;
			// insert channel instead of the usec MSB, swap usec <-> sec
			if (ts_rcv && cntr[0]) ts_ram[{chn, ~cntr[2], cntr[1]}] <= {rcv_last ? {6'b0,chn} : ts_data, ts_data_r};

			if (rst) ts_ackn_r <= 4'hf;
			else ts_ackn_r <= ts_rq & (ts_ackn_r \| (chn1hot & {4{pre_ackn}}));




	end		end

	myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(4))		assign dout[15:0] = ts_ram[ra];
	i_ts (.D(ts_mux[15:0]),
	.WE(we), // we_d, decoded sub_address
	.clk(!sclk),
	.AW(wa[3:0]),
	.AR(ra[3:0]),
	.QW(),
	.QR(dout[15:0]));

	endmodule		endmodule

timing/timing393.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -99,7 +99,7 @@ module timing393 #(
	output [7:0] ts_data_chn3, // byte-wide serialized timestamp message received or local		output [7:0] ts_data_chn3, // byte-wide serialized timestamp message received or local

	// timestamp for the event logger		// timestamp for the event logger
	input lclk, // clock used by the evebt logger		input lclk, // clock used by the event logger
	input ts_logger_snap, // request from the logger to take a snapshot		input ts_logger_snap, // request from the logger to take a snapshot
	output ts_logger_stb, // one clock pulse before sending TS data		output ts_logger_stb, // one clock pulse before sending TS data
	output [7:0] ts_logger_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)		output [7:0] ts_logger_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)

Admin message