preparing for testing membridge module on the target system

.project

@@ -62,77 +62,77 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150428234540494.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150430123759800.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150428234540494.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150430123759800.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150428234740722.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150430123957882.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150428234540494.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150430123759800.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150428234740722.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150430123957882.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-place-20150428234740722.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-place-20150430123957882.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-route-20150428234740722.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-route-20150430123957882.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150428234540494.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150430123759800.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

py393/test_mcntrl.py

@@ -56,6 +56,7 @@ import x393_mcntrl_buffers
 import x393_mcntrl_tests
 import x393_mcntrl_eyepatterns
 import x393_mcntrl_adjust
+import x393_mcntrl_membridge
 import vrlg
 __all__ = []
 __version__ = 0.1
@@ -330,7 +331,7 @@ USAGE
     x393Tests=       x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
     x393Eyepatterns= x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)
     x393Adjust=      x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)
-    
+    X393Membridge=   x393_mcntrl_membridge.X393McntrlMembridge(verbose,args.simulated)
     '''
     print ("----------------------")
     print("x393_mem.__dict__="+str(x393_mem.__dict__))
@@ -354,6 +355,8 @@ USAGE
     extractTasks(x393_mcntrl_tests.X393McntrlTests,x393Tests)
     extractTasks(x393_mcntrl_eyepatterns.X393McntrlEyepattern,x393Eyepatterns)
     extractTasks(x393_mcntrl_adjust.X393McntrlAdjust,x393Adjust)
+    extractTasks(x393_mcntrl_membridge.X393McntrlMembridge,X393Membridge)
+    
 
     for cmdLine in commands:
         print ('Running task: '+str(cmdLine))

py393/vrlg.py

@@ -121,14 +121,16 @@ def restore_default(vname=None):
 
 DFLT_REFRESH_ADDR__TYPE = str
 NUM_CYCLES_09__RAW = str
+MEMBRIDGE_SIZE64__TYPE = str
 DQSTRI_LAST__TYPE = str
 DLY_LD_MASK__TYPE = str
 STATUS_MSB_RSHFT__TYPE = str
 MCONTR_BUF0_RD_ADDR = int
 MCNTRL_SCANLINE_WINDOW_WH__RAW = str
 MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
+WSEL = int
 MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
-MCNTRL_PS_EN_RST__TYPE = str
+LD_DLY_LANE1_IDELAY = int
 MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
 MCNTRL_TILED_CHN4_ADDR = int
 WINDOW_Y0__RAW = str
@@ -146,26 +148,29 @@ TILED_STARTX__TYPE = str
 HIGH_PERFORMANCE_MODE__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
 MCONTR_TOP_16BIT_ADDR__TYPE = str
+AFI_LO_ADDR64__TYPE = str
 WBUF_DLY_WLV__TYPE = str
 TEST01_SUSPEND = int
 MCONTR_TOP_16BIT_CHN_EN = int
 NUM_XFER_BITS__TYPE = str
+AFI_SIZE64 = int
 DLY_LANE1_IDELAY__TYPE = str
 REF_JITTER1__RAW = str
 MCNTRL_TILED_MASK__TYPE = str
-MCONTR_BUF1_WR_ADDR = int
+MCNTRL_SCANLINE_MASK__TYPE = str
 DFLT_DQ_TRI_ON_PATTERN = int
 MCONTR_PHY_0BIT_SDRST_ACT = int
 DEFAULT_STATUS_MODE = int
+MEMBRIDGE_START64__TYPE = str
 TILED_EXTRA_PAGES__TYPE = str
 DLY_LD__TYPE = str
 MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
 MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
 STATUS_2LSB_SHFT__TYPE = str
 DFLT_WBUF_DELAY__RAW = str
-DLY_LANE1_ODELAY__TYPE = str
+MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
 TILE_VSTEP__RAW = str
-MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
+MEMBRIDGE_LEN64__TYPE = str
 NUM_CYCLES_04 = int
 NUM_CYCLES_05 = int
 DLY_LD = int
@@ -180,7 +185,7 @@ MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
 NUM_CYCLES_13__RAW = str
 MCONTR_BUF0_RD_ADDR__TYPE = str
 STATUS_ADDR__RAW = str
-MCNTRL_SCANLINE_MASK__TYPE = str
+DLY_LANE0_IDELAY__TYPE = str
 MCNTRL_PS_ADDR__TYPE = str
 WINDOW_WIDTH__RAW = str
 CHNBUF_READ_LATENCY = int
@@ -199,7 +204,8 @@ MCNTRL_TILED_TILE_WHS = int
 FRAME_START_ADDRESS__TYPE = str
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
 MCNTRL_TILED_STATUS_CNTRL__RAW = str
-DQSTRI_FIRST = int
+MEMBRIDGE_ADDR__RAW = str
+DLY_PHASE = int
 DFLT_DQS_TRI_OFF_PATTERN = int
 NUM_CYCLES_03__TYPE = str
 MCONTR_TOP_16BIT_CHN_EN__TYPE = str
@@ -211,8 +217,9 @@ VERBOSE = int
 DLY_LANE1_ODELAY = long
 MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
 CMD_DONE_BIT__TYPE = str
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
 MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
-DLY_LANE0_IDELAY = long
+CLKFBOUT_DIV_AXIHP = int
 NUM_CYCLES_13__TYPE = str
 AXI_RD_ADDR_BITS__RAW = str
 MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
@@ -220,11 +227,13 @@ MCONTR_WR_MASK__RAW = str
 MCNTRL_TILED_WINDOW_STARTXY = int
 MCONTR_TOP_0BIT_MCONTR_EN = int
 SCANLINE_EXTRA_PAGES__RAW = str
+MEMBRIDGE_LEN64__RAW = str
 MCONTR_PHY_16BIT_EXTRA = int
 MCONTR_ARBIT_ADDR_MASK__TYPE = str
 TEST01_NEXT_PAGE__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR = int
+NUM_CYCLES_LOW_BIT = int
 CLKFBOUT_MULT_REF = int
 NUM_CYCLES_14__RAW = str
 MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
@@ -254,7 +263,7 @@ MCONTR_BUF2_WR_ADDR__RAW = str
 NUM_CYCLES_11__TYPE = str
 MCNTRL_SCANLINE_STARTADDR__TYPE = str
 WBUF_DLY_DFLT__RAW = str
-DLY_PHASE = int
+DQSTRI_FIRST = int
 LD_DLY_CMDA__TYPE = str
 DLY_CMDA_ODELAY__TYPE = str
 LD_DLY_CMDA = int
@@ -267,10 +276,13 @@ MCNTRL_SCANLINE_MASK = int
 TILE_HEIGHT = int
 AXI_WR_ADDR_BITS__TYPE = str
 MCNTRL_PS_MASK = int
+MEMBRIDGE_CTRL = int
 MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
+COLADDR_NUMBER = int
 MCONTR_PHY_STATUS_CNTRL = int
 MCNTRL_PS_ADDR__RAW = str
 MCONTR_BUF2_RD_ADDR__TYPE = str
+CLKFBOUT_DIV_AXIHP__RAW = str
 TILED_STARTX__RAW = str
 WRITE_BLOCK_OFFSET__TYPE = str
 STATUS_ADDR_MASK = int
@@ -279,7 +291,7 @@ AXI_WR_ADDR_BITS = int
 TEST01_NEXT_PAGE = int
 CLKFBOUT_MULT__RAW = str
 MAX_TILE_HEIGHT__RAW = str
-INITIALIZE_OFFSET__TYPE = str
+MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
 IBUF_LOW_PWR = str
 CONTROL_ADDR = int
 DQSTRI_FIRST__TYPE = str
@@ -318,7 +330,9 @@ LD_DLY_LANE1_ODELAY__RAW = str
 MCNTRL_TILED_WINDOW_WH__TYPE = str
 MCONTR_WR_MASK__TYPE = str
 SS_MOD_PERIOD__RAW = str
+MEMBRIDGE_WIDTH64__TYPE = str
 MAX_TILE_HEIGHT = int
+AFI_LO_ADDR64__RAW = str
 MCNTRL_SCANLINE_STARTADDR__RAW = str
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
@@ -329,8 +343,10 @@ MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
 MCONTR_PHY_16BIT_WBUF_DELAY = int
 DEFAULT_STATUS_MODE__RAW = str
 DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
+TILE_HEIGHT__RAW = str
 FRAME_WIDTH_BITS = int
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
+MEMBRIDGE_STATUS_CNTRL = int
 SLEW_CMDA__TYPE = str
 MCONTR_RD_MASK__TYPE = str
 READ_BLOCK_OFFSET__RAW = str
@@ -339,6 +355,7 @@ SLEW_DQ__RAW = str
 FRAME_HEIGHT_BITS__TYPE = str
 DLY_DQS_IDELAY = long
 MCONTR_BUF3_RD_ADDR__TYPE = str
+MEMBRIDGE_ADDR = int
 DLY_DQ_ODELAY__TYPE = str
 MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
 MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
@@ -352,11 +369,13 @@ DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
 MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
 SCANLINE_EXTRA_PAGES__TYPE = str
 PHASE_WIDTH__RAW = str
+MEMBRIDGE_START64 = int
+MEMBRIDGE_SIZE64__RAW = str
 DFLT_DQS_PATTERN = int
 DLY_LANE0_DQS_WLV_IDELAY__RAW = str
 MCNTRL_TEST01_CHN2_MODE__TYPE = str
 DLY_LANE1_IDELAY__RAW = str
-MCONTR_BUF1_RD_ADDR = int
+MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
 SLEW_CLK = str
 LD_DLY_LANE1_ODELAY__TYPE = str
 MCNTRL_PS_STATUS_CNTRL = int
@@ -365,7 +384,7 @@ SS_MODE__TYPE = str
 MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
 WINDOW_Y0__TYPE = str
 MCONTR_PHY_0BIT_DLY_RST__TYPE = str
-MCONTR_BUF1_WR_ADDR__TYPE = str
+CLKFBOUT_MULT_AXIHP__RAW = str
 BUFFER_DEPTH32__TYPE = str
 MCONTR_TOP_16BIT_STATUS_CNTRL = int
 MCONTR_BUF4_RD_ADDR__RAW = str
@@ -380,8 +399,10 @@ DLY_CMDA = long
 DLY_LANE0_IDELAY__RAW = str
 MCONTR_ARBIT_ADDR = int
 MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
+MEMBRIDGE_CTRL__RAW = str
 CLKFBOUT_DIV_REF__TYPE = str
 NUM_CYCLES_04__TYPE = str
+WSEL__RAW = str
 MCNTRL_SCANLINE_MODE__RAW = str
 READ_PATTERN_OFFSET__TYPE = str
 MCNTRL_TILED_PENDING_CNTR_BITS = int
@@ -390,14 +411,15 @@ MAX_TILE_WIDTH__TYPE = str
 MCONTR_CMD_WR_ADDR = int
 MCONTR_BUF3_RD_ADDR__RAW = str
 CLKIN_PERIOD = int
-MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
+DLY_LANE1_ODELAY__TYPE = str
+RSEL__TYPE = str
 MCNTRL_TEST01_MASK__RAW = str
 MCONTR_PHY_16BIT_ADDR_MASK = int
 MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
 HIGH_PERFORMANCE_MODE = str
 NUM_CYCLES_07__RAW = str
 DQTRI_LAST__RAW = str
-MCONTR_BUF1_RD_ADDR__RAW = str
+TILE_WIDTH = int
 CLKFBOUT_PHASE = float
 DFLT_DQM_PATTERN = int
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
@@ -438,8 +460,8 @@ MCNTRL_PS_CMD__RAW = str
 MCONTR_BUF3_WR_ADDR = int
 NEWPAR = int
 MCNTRL_PS_MASK__RAW = str
+AFI_SIZE64__RAW = str
 MCONTR_PHY_0BIT_CKE_EN = int
-MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
 BUFFER_DEPTH32 = int
 MCNTRL_TILED_CHN2_ADDR__TYPE = str
 SLEW_DQS = str
@@ -447,6 +469,7 @@ DFLT_REFRESH_ADDR = int
 MCONTR_WR_MASK = int
 MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
 TEST01_SUSPEND__RAW = str
+MEMBRIDGE_STATUS_CNTRL__TYPE = str
 T_REFI__TYPE = str
 STATUS_DEPTH__RAW = str
 DFLT_DQ_TRI_ON_PATTERN__TYPE = str
@@ -454,7 +477,6 @@ MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
 TEST01_START_FRAME = int
 DQTRI_FIRST__TYPE = str
 MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
-DLY_LANE0_IDELAY__TYPE = str
 T_RFC__RAW = str
 DLY_CMDA__TYPE = str
 CLKFBOUT_MULT__TYPE = str
@@ -477,20 +499,24 @@ COLADDR_NUMBER__TYPE = str
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
 TEST01_SUSPEND__TYPE = str
 PICKLE = str
+AFI_SIZE64__TYPE = str
 NUM_CYCLES_15__RAW = str
 MCONTR_PHY_0BIT_ADDR_MASK = int
 MCNTRL_TILED_TILE_WHS__TYPE = str
 DLY_DQ_IDELAY = long
 WINDOW_X0 = int
 DFLT_WBUF_DELAY__TYPE = str
-MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
+INITIALIZE_OFFSET__TYPE = str
 LD_DLY_LANE0_ODELAY = int
 SCANLINE_EXTRA_PAGES = int
 READ_PATTERN_OFFSET__RAW = str
 MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
-TILE_HEIGHT__RAW = str
+MEMBRIDGE_LEN64 = int
+MEMBRIDGE_SIZE64 = int
 PICKLE__TYPE = str
 MCONTR_PHY_0BIT_CKE_EN__TYPE = str
+AFI_LO_ADDR64 = int
+RSEL = int
 MCNTRL_TILED_MODE__TYPE = str
 DIVCLK_DIVIDE = int
 NUM_CYCLES_07__TYPE = str
@@ -512,23 +538,25 @@ MCONTR_PHY_0BIT_DLY_RST = int
 MCONTR_PHY_16BIT_ADDR__TYPE = str
 TILED_STARTY = int
 TILED_STARTX = int
+MEMBRIDGE_MASK__TYPE = str
 AXI_WR_ADDR_BITS__RAW = str
 MCONTR_BUF3_RD_ADDR = int
 DFLT_REFRESH_PERIOD__TYPE = str
 MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
 MCNTRL_TILED_MASK = int
 NUM_CYCLES_03__RAW = str
-MCONTR_BUF1_WR_ADDR__RAW = str
+CLKFBOUT_PHASE__TYPE = str
 MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
 DLY_LANE1_DQS_WLV_IDELAY = long
 MCNTRL_TILED_WINDOW_WH = int
-CLKFBOUT_PHASE__TYPE = str
 NUM_CYCLES_06__RAW = str
 MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
 NUM_XFER_BITS__RAW = str
 MCNTRL_TILED_WINDOW_STARTXY__RAW = str
+CLKFBOUT_MULT_AXIHP = int
 DLY_CMDA_ODELAY = long
 MCONTR_TOP_0BIT_ADDR = int
+MEMBRIDGE_LO_ADDR64__TYPE = str
 MCNTRL_SCANLINE_MODE = int
 MCONTR_ARBIT_ADDR_MASK = int
 NUM_CYCLES_05__RAW = str
@@ -541,6 +569,7 @@ MCONTR_TOP_0BIT_REFRESH_EN = int
 MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
 SLEW_CMDA__RAW = str
 MCNTRL_TEST01_CHN2_MODE__RAW = str
+CLKFBOUT_MULT_AXIHP__TYPE = str
 LD_DLY_PHASE__RAW = str
 MCONTR_TOP_STATUS_REG_ADDR__RAW = str
 MCONTR_ARBIT_ADDR__TYPE = str
@@ -560,12 +589,13 @@ MCONTR_BUF2_RD_ADDR = int
 MCONTR_BUF2_WR_ADDR__TYPE = str
 NUM_CYCLES_02__TYPE = str
 DQTRI_LAST__TYPE = str
-TILE_WIDTH = int
+TEST_INITIAL_BURST = int
 FRAME_HEIGHT_BITS__RAW = str
 MCNTRL_TILED_STARTADDR = int
 WINDOW_HEIGHT__TYPE = str
 MCNTRL_TILED_FRAME_FULL_WIDTH = int
 TILE_HEIGHT__TYPE = str
+CLKFBOUT_DIV_AXIHP__TYPE = str
 MCNTRL_TILED_CHN4_ADDR__TYPE = str
 FRAME_HEIGHT_BITS = int
 MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
@@ -590,15 +620,16 @@ REF_JITTER1__TYPE = str
 MCNTRL_SCANLINE_MODE__TYPE = str
 MCONTR_PHY_16BIT_PATTERNS_TRI = int
 DLY_CMDA__RAW = str
-NUM_CYCLES_LOW_BIT = int
+MEMBRIDGE_MASK = int
 READ_BLOCK_OFFSET = int
 T_REFI__RAW = str
 STATUS_MSB_RSHFT = int
 BUFFER_DEPTH32__RAW = str
+RSEL__RAW = str
 CLKIN_PERIOD__TYPE = str
 DIVCLK_DIVIDE__RAW = str
 DLY_LANE0_ODELAY__TYPE = str
-COLADDR_NUMBER = int
+DLY_LANE0_IDELAY = long
 SDCLK_PHASE__TYPE = str
 SCANLINE_STARTY__TYPE = str
 REFRESH_OFFSET__RAW = str
@@ -607,14 +638,17 @@ MCNTRL_TEST01_CHN1_MODE__RAW = str
 MCONTR_BUF4_RD_ADDR__TYPE = str
 LD_DLY_LANE0_ODELAY__TYPE = str
 MCONTR_TOP_16BIT_ADDR__RAW = str
+MEMBRIDGE_LO_ADDR64 = int
 MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
 DFLT_DQS_TRI_ON_PATTERN__TYPE = str
 MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
 TILED_KEEP_OPEN__RAW = str
 MCNTRL_SCANLINE_STARTADDR = int
+MEMBRIDGE_WIDTH64__RAW = str
 MCONTR_TOP_0BIT_ADDR__TYPE = str
 CLKFBOUT_MULT_REF__TYPE = str
 MCNTRL_PS_CMD__TYPE = str
+MEMBRIDGE_START64__RAW = str
 STATUS_MSB_RSHFT__RAW = str
 STATUS_PSHIFTER_RDY_MASK = int
 NUM_CYCLES_04__RAW = str
@@ -632,6 +666,8 @@ MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
 VERBOSE__RAW = str
 WBUF_DLY_WLV = int
 MCONTR_BUF3_WR_ADDR__RAW = str
+MEMBRIDGE_LO_ADDR64__RAW = str
+MEMBRIDGE_WIDTH64 = int
 MCNTRL_TEST01_CHN3_MODE = int
 LD_DLY_PHASE__TYPE = str
 MCONTR_PHY_0BIT_ADDR__TYPE = str
@@ -644,11 +680,12 @@ STATUS_ADDR_MASK__RAW = str
 MCNTRL_SCANLINE_CHN3_ADDR = int
 DLY_SET__TYPE = str
 MCONTR_TOP_16BIT_ADDR = int
-MCONTR_BUF1_RD_ADDR__TYPE = str
 DLY_DM_ODELAY = long
+MEMBRIDGE_STATUS_CNTRL__RAW = str
 MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
 DFLT_DQS_TRI_OFF_PATTERN__RAW = str
 FRAME_FULL_WIDTH = int
+MEMBRIDGE_STATUS_REG = int
 NUM_CYCLES_13 = int
 NUM_CYCLES_12 = int
 NUM_CYCLES_11 = int
@@ -690,7 +727,7 @@ CLKIN_PERIOD__RAW = str
 INITIALIZE_OFFSET = int
 MCNTRL_PS_MASK__TYPE = str
 CLK_DIV_PHASE__RAW = str
-LD_DLY_LANE1_IDELAY = int
+MCNTRL_PS_EN_RST__TYPE = str
 MCONTR_PHY_16BIT_PATTERNS__TYPE = str
 MCONTR_PHY_0BIT_CKE_EN__RAW = str
 PICKLE__RAW = str
@@ -727,6 +764,7 @@ MCLK_PHASE__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD = int
 T_REFI = int
 MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
+WSEL__TYPE = str
 STATUS_SEQ_SHFT__TYPE = str
 DFLT_CHN_EN__TYPE = str
 MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
@@ -747,15 +785,17 @@ SS_EN = str
 DLY_LANE0_ODELAY = long
 CLKFBOUT_DIV_REF = int
 WRITELEV_OFFSET = int
+MEMBRIDGE_ADDR__TYPE = str
 MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
 VERBOSE__TYPE = str
 TILED_KEEP_OPEN = int
 MCNTRL_SCANLINE_MASK__RAW = str
 MCNTRL_SCANLINE_WINDOW_STARTXY = int
-TEST_INITIAL_BURST = int
 MCONTR_ARBIT_ADDR__RAW = str
+MEMBRIDGE_MASK__RAW = str
 MCNTRL_TEST01_ADDR = int
 MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
+MEMBRIDGE_CTRL__TYPE = str
 MCONTR_BUF4_WR_ADDR__RAW = str
 TILED_KEEP_OPEN__TYPE = str
 CONTROL_ADDR_MASK__TYPE = str
@@ -771,6 +811,7 @@ REFRESH_OFFSET__TYPE = str
 DFLT_INV_CLK_DIV__TYPE = str
 MAX_TILE_WIDTH = int
 CHNBUF_READ_LATENCY__RAW = str
+MEMBRIDGE_STATUS_REG__TYPE = str
 MCONTR_BUF4_RD_ADDR = int
 SS_MOD_PERIOD__TYPE = str
 MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
@@ -783,6 +824,7 @@ INITIALIZE_OFFSET__RAW = str
 CMD_DONE_BIT__RAW = str
 MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
 CLK_DIV_PHASE = float
+MEMBRIDGE_STATUS_REG__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
 MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
 MCONTR_BUF0_WR_ADDR__TYPE = str

py393/x393_axi_control_status.py

@@ -187,19 +187,19 @@ class X393AxiControlStatus(object):
                               timeout=10.0):          # maximal timeout (0 - no timeout)
         """
         Poll specified status register until some condition is matched
-        <status_address> -         status register address (currently 0..255)
-        <status_control_address> - control register address (to control status generation)
-        <status_mode>            - status generation mode:
-                                  0: disable status generation,
-                                  1: single status request,
-                                  2: auto status, keep specified seq number,
-                                  4: auto, inc sequence number 
-        <pattern> -                26-bit pattern to match
-        <mask> -                   26-bit mask to enable pattern matching (0-s - ignore)
-        <invert_match> -           invert match (wait until matching condition becomes false)
-        <wait_seq>-                wait for the correct sequence number, if False - assume always correct
-        <timeout>                  maximal time to wait for condition
-        Return 1 if success, 0 - if timeout
+        @param status_address   status register address (currently 0..255)
+        @param status_control_address> - control register address (to control status generation)
+        @param status_mode status generation mode:
+                             0: disable status generation,
+                             1: single status request,
+                             2: auto status, keep specified seq number,
+                             4: auto, inc sequence number 
+        @param pattern       26-bit pattern to match
+        @param mask          26-bit mask to enable pattern matching (0-s - ignore)
+        @param invert_match  invert match (wait until matching condition becomes false)
+        @param wait_seq      wait for the correct sequence number, if False - assume always correct
+        @param timeout       maximal time to wait for condition
+        @return 1 if success, 0 - if timeout
         """
         match=False
         endTime=None
@@ -245,10 +245,11 @@ class X393AxiControlStatus(object):
         print ("MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR:%s"%(hx(self.read_status(vrlg.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),8)))
         print ("MCNTRL_TILED_STATUS_REG_CHN2_ADDR:   %s"%(hx(self.read_status(vrlg.MCNTRL_TILED_STATUS_REG_CHN2_ADDR),8)))
         print ("MCNTRL_TILED_STATUS_REG_CHN4_ADDR:   %s"%(hx(self.read_status(vrlg.MCNTRL_TILED_STATUS_REG_CHN4_ADDR),8)))
-        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),8)))
+#        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),8)))
         print ("MCNTRL_TEST01_STATUS_REG_CHN2_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),8)))
         print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8)))
         print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR:  %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))
+        print ("MEMBRIDGE_STATUS_REG:                %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8)))
 
     def program_status(self,
                        base_addr,   # input [29:0] base_addr;
@@ -289,10 +290,11 @@ class X393AxiControlStatus(object):
         self.program_status (vrlg.MCNTRL_SCANLINE_CHN3_ADDR, vrlg.MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num)# //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
         self.program_status (vrlg.MCNTRL_TILED_CHN2_ADDR,    vrlg.MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num)# //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
         self.program_status (vrlg.MCNTRL_TILED_CHN4_ADDR,    vrlg.MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num)#; //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
-        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
+#        self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
         self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
         self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,
         self.program_status (vrlg.MCNTRL_TEST01_ADDR,        vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
+        self.program_status (vrlg.MEMBRIDGE_ADDR,            vrlg.MEMBRIDGE_STATUS_CNTRL,         mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
         
     def enable_cmda(self,
                     en): # input en;

py393/x393_mcntrl_adjust.py

@@ -5007,6 +5007,7 @@ write_settings= {
                     quiet=3):
         """
         @param tasks - "*" - load bitfile
+                       "I" - initialize memory, set defaults
                        "C" cmda, "W' - write levelling, "R" - read levelling (DQI-DQSI), "P" -  dqs input phase (DQSI-PHASE),
                        "O" - output timing (DQ odelay vs  DQS odelay), "A" - address/bank lines output delays, "Z" - print results,
                        "B" - select R/W brances and get the optimal phase

py393/x393_mcntrl_buffers.py

@@ -77,7 +77,7 @@ class X393McntrlBuffers(object):
         if self.DEBUG_MODE > 1:
             print("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%dt"%(chn, page, startX, startY,num_bursts))
         if   chn == 0:  start_addr=vrlg.MCONTR_BUF0_WR_ADDR + (page << 8)
-        elif chn == 1:  start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
+#        elif chn == 1:  start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
         elif chn == 2:  start_addr=vrlg.MCONTR_BUF2_WR_ADDR + (page << 8)
         elif chn == 3:  start_addr=vrlg.MCONTR_BUF3_WR_ADDR + (page << 8)
         elif chn == 4:  start_addr=vrlg.MCONTR_BUF4_WR_ADDR + (page << 8)
@@ -154,7 +154,7 @@ class X393McntrlBuffers(object):
             print("===")    
         start_addr=-1
         if   chn==0:start_addr=vrlg.MCONTR_BUF0_WR_ADDR + (page << 8)
-        elif chn==1:start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
+#        elif chn==1:start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
         elif chn==2:start_addr=vrlg.MCONTR_BUF2_WR_ADDR + (page << 8)
         elif chn==3:start_addr=vrlg.MCONTR_BUF3_WR_ADDR + (page << 8)
         elif chn==4:start_addr=vrlg.MCONTR_BUF4_WR_ADDR + (page << 8)
@@ -221,7 +221,7 @@ class X393McntrlBuffers(object):
         """
         start_addr=-1
         if   chn==0:  start_addr=vrlg.MCONTR_BUF0_RD_ADDR + (page << 8)
-        elif chn==1:  start_addr=vrlg.MCONTR_BUF1_RD_ADDR + (page << 8)
+#        elif chn==1:  start_addr=vrlg.MCONTR_BUF1_RD_ADDR + (page << 8)
         elif chn==2:  start_addr=vrlg.MCONTR_BUF2_RD_ADDR + (page << 8)
         elif chn==3:  start_addr=vrlg.MCONTR_BUF3_RD_ADDR + (page << 8)
         elif chn==4:  start_addr=vrlg.MCONTR_BUF4_RD_ADDR + (page << 8)

py393/x393_mcntrl_tests.py

@@ -333,22 +333,24 @@ class X393McntrlTests(object):
         pages_per_row= (window_width>>vrlg.NUM_XFER_BITS)+(0,1)[(window_width & ((1<<vrlg.NUM_XFER_BITS))-1)==0] # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
         print("====== test_scanline_write: channel=%d, extra_pages=%d,  wait_done=%d"%
                                                 (channel,    extra_pages,     wait_done))
+        '''
         if   channel == 1:
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
             status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
             status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
             test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
-        elif channel ==  3:
+        '''            
+        if channel ==  3:
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN3_ADDR
             status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
             status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
             test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
         else:
-            print("**** ERROR: Invalid channel, only 1 and 3 are valid")
+            print("**** ERROR: Invalid channel, only 3 is valid")
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
-            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
-            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
-            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
+            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
+            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
+            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
 
         mode=   self.func_encode_mode_scanline(
                     extra_pages,
@@ -452,22 +454,24 @@ class X393McntrlTests(object):
 
         print("====== test_scanline_read: channel=%d, extra_pages=%d,  show_data=%d"%
                                              (channel,    extra_pages,     show_data))
+        '''
         if   channel == 1:
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
             status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
             status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
             test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
-        elif channel == 3:
+        '''
+        if channel == 3:
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN3_ADDR
             status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
             status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
             test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
         else:
-            print("**** ERROR: Invalid channel, only 1 and 3 are valid")
+            print("**** ERROR: Invalid channel, only 3 is valid")
             start_addr=             vrlg.MCNTRL_SCANLINE_CHN1_ADDR
-            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR
-            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_STATUS_CNTRL
-            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN1_MODE
+            status_address=         vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
+            status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
+            test_mode_address=      vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
         mode=   self.func_encode_mode_scanline(
                                                extra_pages,
                                                0, # write_mem,

py393/x393_mem.py

@@ -44,11 +44,12 @@ class X393Mem(object):
     def __init__(self, debug_mode=1,dry_mode=True):
         self.DEBUG_MODE=debug_mode
         self.DRY_MODE=dry_mode
-    def write_mem (self,addr, data):
+    def write_mem (self,addr, data,quiet=1):
         """
         Write 32-bit word to physical memory
-        <addr> - physical byte address
-        <data> - 32-bit data to write
+        @param addr - physical byte address
+        @param data - 32-bit data to write
+        @param quiet - reduce output
         """
         if self.DRY_MODE:
             print ("simulated: write_mem(0x%x,0x%x)"%(addr,data))
@@ -62,7 +63,7 @@ class X393Mem(object):
             packedData=struct.pack(self.ENDIAN+"L",data)
             d=struct.unpack(self.ENDIAN+"L",packedData)[0]
             mm[page_offs:page_offs+4]=packedData
-            if self.DEBUG_MODE > 2:
+            if quiet <1:
                 print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
         '''    
         if MONITOR_EMIO and VEBOSE:
@@ -74,10 +75,11 @@ class X393Mem(object):
                 exit (0)
         '''    
 
-    def read_mem (self,addr):
+    def read_mem (self,addr,quiet=1):
         '''
-         Read 32-bit word from physical memory
-         <addr> - physical byte address
+        Read 32-bit word from physical memory
+        @param addr  physical byte address
+        @param quiet - reduce output
         '''    
         if self.DRY_MODE:
             print ("simulated: read_mem(0x%x)"%(addr))
@@ -90,45 +92,102 @@ class X393Mem(object):
             mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
             data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
             d=data[0]
-            if self.DEBUG_MODE > 2:
+            if quiet < 1:
                 print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
             return d
-#        mm.close() #probably not needed with "with"
-    def mem_dump (self,start_addr,end_addr=0):
+
+    def mem_dump (self, start_addr, end_addr=1, byte_mode=4):
         '''
          Read and print memory range from physical memory
-         <start_addr> - physical byte start address
-         <end_addr> - physical byte end address (inclusive)
-         Returns list of read values
+         @param start_addr physical byte start address
+         @param end_addr  physical byte end address (inclusive), if negative/less than start_addr - number of items
+         @param byte_mode number of bytes per item (1,2,4,8)
+         @return list of read values
         '''
+        frmt_bytes={1:'B',2:'H',4:'L',8:'Q'}
+        bytes_per_line_mask={1:0x1f,2:0x1f,4:0x3f,8:0x3f}
+        default_byte_mode=4
+        if not byte_mode in frmt_bytes.keys():
+            print ("Invalid byte mode: '%s'. Only %s are supported. Using %d"%(str(byte_mode),str(frmt_bytes.keys()),default_byte_mode))
+            byte_mode=default_byte_mode
+        data_frmt=  "%%0%dx"%(2*byte_mode)
+        simul_mask= (1 << (8*byte_mode)) -1
+        addr_mask=0xffffffff ^ (byte_mode-1)
+        start_addr &= addr_mask
+        if end_addr < start_addr:
+            end_addr=start_addr + abs(end_addr*byte_mode) -1
+        end_addr  &= addr_mask
+#       align start address to 32-bit word even if the mode is byte/short        
         start_addr &= 0xfffffffc
-        end_addr &=   0xfffffffc
-        if end_addr<start_addr:
-            end_addr = start_addr
+        print_mask=bytes_per_line_mask[byte_mode]
         rslt=[]
         if self.DRY_MODE:
-            rslt=range(start_addr,end_addr+1,4)
+            rslt=[d & simul_mask for d in range(start_addr,end_addr+byte_mode,byte_mode)]
         else:
             with open("/dev/mem", "r+b") as f:
-                for addr in range (start_addr,end_addr+4,4):
+                for addr in range (start_addr,end_addr+byte_mode,byte_mode):
                     page_addr=addr & (~(self.PAGE_SIZE-1))
                     page_offs=addr-page_addr
                     if (page_addr>=0x80000000):
                         page_addr-= (1<<32)
                     mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
-                    data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
+                    data=struct.unpack_from(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs)
                     rslt.append(data[0])
                     
-        for addr in range (start_addr,end_addr+4,4):
-            if (addr == start_addr) or ((addr & 0x3f) == 0):
+        for addr in range (start_addr,end_addr+byte_mode,byte_mode):
+            if (addr == start_addr) or ((addr & print_mask) == 0):
                 if self.DRY_MODE:
                     print ("\nsimulated: 0x%08x:"%addr,end="")
                 else:     
                     print ("\n0x%08x:"%addr,end="")
-            d=rslt[(addr-start_addr) >> 2]
-            print ("%08x "%d,end=""),
+            d=rslt[(addr-start_addr) // byte_mode]
+            print (data_frmt%(d),end=" ")
         print("")
         return rslt    
+
+    def mem_fill (self, start_addr, start_data=0, end_addr=1, inc_data=0, byte_mode=4):
+        '''
+         Read and print memory range from physical memory
+         @param start_addr physical byte start address
+         @param start_data data/start data to write
+         @param end_addr  physical byte end address (inclusive), if negative/less than start_addr - number of items
+         @param inc_data increment each next item by this value
+         @param byte_mode number of bytes per item (1,2,4,8)
+        '''
+        frmt_bytes={1:'B',2:'H',4:'L',8:'Q'}
+        default_byte_mode=4
+        if not byte_mode in frmt_bytes.keys():
+            print ("Invalid byte mode: '%s'. Only %s are supported. Using %d"%(str(byte_mode),str(frmt_bytes.keys()),default_byte_mode))
+            byte_mode=default_byte_mode
+        data_mask= (1 << (8*byte_mode)) -1
+        addr_mask=0xffffffff ^ (byte_mode-1)
+        start_addr &= addr_mask
+        if end_addr < start_addr:
+            end_addr=start_addr + abs(end_addr*byte_mode) -1
+        end_addr  &= addr_mask
+#       align start address to 32-bit word even if the mode is byte/short        
+        start_addr &= 0xfffffffc
+        if self.DRY_MODE:
+            print ("Simulated mem_fill(0x%x, 0x%x, 0x%x, 0x%x, %d)"%(start_addr, start_data, end_addr, inc_data, byte_mode))
+            data_frmt=  "%%0%dx"%(2*byte_mode)
+            for addr in range (start_addr,end_addr+byte_mode,byte_mode):
+                data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
+                page_addr=addr & (~(self.PAGE_SIZE-1))
+                page_offs=addr-page_addr
+                if (page_addr>=0x80000000):
+                    page_addr-= (1<<32)
+                print (("0x%08x: "+ data_frmt)%(addr,data))
+        else:
+            with open("/dev/mem", "r+b") as f:
+                for addr in range (start_addr,end_addr+byte_mode,byte_mode):
+                    data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
+                    page_addr=addr & (~(self.PAGE_SIZE-1))
+                    page_offs=addr-page_addr
+                    if (page_addr>=0x80000000):
+                        page_addr-= (1<<32)
+                    mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
+                    struct.pack_into(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs, data)
+    
     '''
     Read/write slave AXI using byte addresses relative to the AXI memory region
     '''

x393_testbench01.sav

 [*]
 [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
-[*] Thu Apr 30 18:06:37 2015
+[*] Thu Apr 30 18:37:14 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150430115913649.lxt"
-[dumpfile_mtime] "Thu Apr 30 18:02:38 2015"
-[dumpfile_size] 174024137
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150430120701234.lxt"
+[dumpfile_mtime] "Thu Apr 30 18:10:21 2015"
+[dumpfile_size] 174023349
 [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
 [timestart] 37450000
 [size] 1823 1180
@@ -15,7 +15,7 @@
 [treeopen] x393_testbench01.simul_axi_hp_wr_i.
 [treeopen] x393_testbench01.x393_i.
 [sst_width] 301
-[signals_width] 333
+[signals_width] 446
 [sst_expanded] 1
 [sst_vpaned_height] 367
 @800200
@@ -370,7 +370,6 @@ x393_testbench01.simul_axi_hp_wr_i.wresp_re[0]
 x393_testbench01.x393_i.membridge_i.afi_bvalid[0]
 x393_testbench01.x393_i.membridge_i.afi_bvalid_r[0]
 @22
-x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
 x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
 x393_testbench01.x393_i.membridge_i.wresp_conf[7:0]
 x393_testbench01.x393_i.membridge_i.axi_wr_pending[7:0]
@@ -589,17 +588,8 @@ x393_testbench01.x393_i.membridge_i.wr_id[4:0]
 @28
 x393_testbench01.x393_i.membridge_i.wr_mode[0]
 x393_testbench01.x393_i.membridge_i.wr_start[0]
-@c00022
-x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-@28
-(0)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(1)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(2)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(3)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(4)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(5)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(6)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
-(7)x393_testbench01.x393_i.membridge_i.wresp_pending[7:0]
+@c00200
+-x393_testbench01.x393_i.membridge_i.wresp_pending
 @1401200
 -group_end
 @28

x393_testbench01.tf

@@ -1405,103 +1405,6 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
     end
 endtask
 
-task membridge_setup;
-    input [28:0] len64;    // number of 64-bit words to transfer
-    input [28:0] width64;  // frame width in 64-bit words
-    input [28:0] start64;  // relative start adderss of the transfer (set to 0 when writing lo_addr64)
-    input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words 
-    input [28:0] size64;    // size of the system memory range in 64-bit words
-     
-    begin
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LO_ADDR64,        {3'b0,lo_addr64});    
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_SIZE64,           {3'b0,size64});    
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_START64,          {3'b0,start64});    
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LEN64,            {3'b0,len64});    
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_WIDTH64,          {3'b0,width64});    
-    end
-endtask
-
-task membridge_start;
-    input continue;    // 0 start from start64, 1 - continue from where it was
-    begin
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL,         {29'b0,continue,2'b11});    
-    end
-endtask
-
-task membridge_en; // SuppressThisWarning VEditor - may be unused
-    input en;    // not needed to start, pauses axi if set to 0 whil running, resets "done" status bit
-    begin
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL,         {31'b0,en});    
-    end
-endtask
-
-
-task afi_setup;
-    input   [1:0] port_num;
-    begin
-        afi_write_reg(port_num,  'h0, 0); // AFI_RDCHAN_CTRL
-        afi_write_reg(port_num,  'h4, 7); // AFI_RDCHAN_ISSUINGCAP
-        afi_write_reg(port_num,  'h8, 0); // AFI_RDQOS
-        //afi_write_reg(port_num,  'hc, 0); // AFI_RDDATAFIFO_LEVEL
-        //afi_write_reg(port_num, 'h10, 0); // AFI_RDDEBUG
-        afi_write_reg(port_num, 'h14, 'hf00); // AFI_WRCHAN_CTRL
-        afi_write_reg(port_num, 'h18, 0); // AFI_WRCHAN_ISSUINGCAP
-        afi_write_reg(port_num, 'h1c, 0); // AFI_WRQOS
-        //afi_write_reg(port_num,  'h20, 0); // AFI_WRDATAFIFO_LEVEL
-        //afi_write_reg(port_num, 'h24, 0); // AFI_WRDEBUG
-    end
-endtask
-
-task afi_write_reg;
-    input   [1:0] port_num;
-    input integer rel_baddr; // relative byte address
-    input  [31:0] data;
-    begin
-       ps_write_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), data);
-    end
-endtask
-
-task afi_read_reg; // SuppressThisWarning VEditor - may be unused
-    input   [1:0] port_num;
-    input integer rel_baddr; // relative byte address
-    input  verbose;
-    begin
-       ps_read_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), verbose);
-    end
-endtask
-
-task ps_write_reg;
-    input [31:0] ps_reg_addr;
-    input [31:0] ps_reg_data;
-    begin
-        @(posedge HCLK);
-        PS_REG_ADDR <= ps_reg_addr;
-        PS_REG_DIN <= ps_reg_data;
-        PS_REG_WR <= 1'b1;
-        @(posedge HCLK);
-        PS_REG_ADDR <= 'bx;
-        PS_REG_DIN <= 'bx;
-        PS_REG_WR <= 1'b0;
-    end
-endtask
-
-task ps_read_reg;
-    input [31:0] ps_reg_addr;
-    input verbose;
-    begin
-        @(posedge HCLK);
-        PS_REG_ADDR <= ps_reg_addr;
-        PS_REG_RD <= 1'b1;
-        @(posedge HCLK);
-        PS_REG_ADDR <= 'bx;
-        PS_REG_DIN <= 'bx;
-        PS_REG_WR <= 1'b0;
-        @(negedge HCLK);
-        if (verbose) begin
-            $display("ps_read_reg(%x) -> %x @%t",ps_reg_addr,PS_RDATA,$time);
-        end
-    end
-endtask
 
 // above - move to include
 
@@ -2102,7 +2005,7 @@ task enable_memcntrl_en_dis;
     end
 endtask
 */
-
+`include "includes/x393_tasks_afi.vh" // SuppressThisWarning VEditor - may be unused
 `include "includes/x393_tasks_mcntrl_en_dis_priority.vh"
 `include "includes/x393_tasks_mcntrl_buffers.vh"
 `include "includes/x393_tasks_pio_sequences.vh"