simulating/bug fixing

.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_0_SimulationTopFile=x393_testbench01.tf
-FPGA_project_1_SimulationTopModule=x393_testbench01
+FPGA_project_0_SimulationTopFile=x393_testbench02.tf
+FPGA_project_1_SimulationTopModule=x393_testbench02
 FPGA_project_2_ImplementationTopFile=x393.v
 FPGA_project_4_part=xc7z030fbg484-1
 com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->

includes/x393_localparams.vh

@@ -117,7 +117,11 @@
     
     localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT;
     localparam FRAME_START_ADDRESS=      'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
-    localparam FRAME_START_ADDRESS_INC=  'h 800;
+    localparam FRAME_START_ADDRESS_INC=  'h800;
+    localparam LAST_BUF_FRAME =           1;
+    localparam CAMSYNC_DELAY =            200;  
+    
+    
     localparam       FRAME_FULL_WIDTH=    'h0c0;  // Padded line length (8-row increment), in 8-bursts (16 bytes)
   
 //  localparam       AFI_LO_ADDR64=       'h4000; // start of the system memory range in 64-bit words
@@ -157,3 +161,4 @@
   
   localparam       TEST_INITIAL_BURST=   4; // 3;
   
+    
\ No newline at end of file

includes/x393_parameters.vh

@@ -431,7 +431,7 @@
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =        12,
     parameter SENSOR_FIFO_2DEPTH =       4,
-    parameter SENSOR_FIFO_DELAY =        4'd7,
+    parameter SENSOR_FIFO_DELAY =        4'd5, // 7,
     // other parameters for histogram_saxi module
     parameter HIST_SAXI_ADDR_MASK =      'h7f0,
       parameter HIST_SAXI_MODE_WIDTH =   8,
@@ -615,11 +615,13 @@
     parameter CAMSYNC_TRIG_DELAY1 =        'h5, // setup input trigger delay
     parameter CAMSYNC_TRIG_DELAY2 =        'h6, // setup input trigger delay
     parameter CAMSYNC_TRIG_DELAY3 =        'h7, // setup input trigger delay
-    parameter CAMSYNC_SNDEN_BIT =          'h1, // enable writing ts_snd_en
-    parameter CAMSYNC_EXTERNAL_BIT =       'h3, // enable writing ts_external (0 - local timestamp in the frame header)
-    parameter CAMSYNC_TRIGGERED_BIT =      'h5, // triggered mode ( 0- async)
-    parameter CAMSYNC_MASTER_BIT =         'h8, // select a 2-bit master channel (master delay may be used as a flash delay)
-    parameter CAMSYNC_CHN_EN_BIT =         'hd, // per-channel enable timestamp generation
+
+    parameter CAMSYNC_EN_BIT =             'h0, // enable module (0 - reset)
+    parameter CAMSYNC_SNDEN_BIT =          'h2, // enable writing ts_snd_en
+    parameter CAMSYNC_EXTERNAL_BIT =       'h4, // enable writing ts_external (0 - local timestamp in the frame header)
+    parameter CAMSYNC_TRIGGERED_BIT =      'h6, // triggered mode ( 0- async)
+    parameter CAMSYNC_MASTER_BIT =         'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
+    parameter CAMSYNC_CHN_EN_BIT =         'he, // per-channel enable timestamp generation
     parameter CAMSYNC_PRE_MAGIC =          6'b110100,
     parameter CAMSYNC_POST_MAGIC =         6'b001101,
     

includes/x393_simulation_parameters.vh

@@ -28,16 +28,16 @@
     parameter       SIMUL_AXI_READ_WIDTH=16,
     
     parameter       MEMCLK_PERIOD = 5.0,
-    parameter       FCLK0_PERIOD = 10.417,
+    parameter       FCLK0_PERIOD =  41.667, //  10.417, 24MHz
     parameter       FCLK1_PERIOD =  0.0,
     
-    parameter SENSOR12BITS_LLINE   =   192,   //   1664;//   line duration in clocks
-    parameter SENSOR12BITS_NCOLS   =    66,   //58; //56; // 129; //128;   //1288;
-    parameter SENSOR12BITS_NROWS   =    18,   // 16;   //   1032;
-    parameter SENSOR12BITS_NROWB   =     1,   // number of "blank rows" from vact to 1-st hact
-    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
+//    parameter SENSOR12BITS_LLINE   =   192,   //   1664;//   line duration in clocks
+//    parameter SENSOR12BITS_NCOLS   =    66,   //58; //56; // 129; //128;   //1288;
+//    parameter SENSOR12BITS_NROWS   =    18,   // 16;   //   1032;
+//    parameter SENSOR12BITS_NROWB   =     1,   // number of "blank rows" from vact to 1-st hact
+//    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
 //    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
-    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
+//    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
     parameter SENSOR12BITS_NGPL =        8,   // bpf to hact
     parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
     //parameter tMD   =   14;    //
@@ -45,15 +45,17 @@
     parameter SENSOR12BITS_TMD =         4,   //
     parameter SENSOR12BITS_TDDO =        2,   //   some confusion here - let's assume that it is from DCLK to Data out
     parameter SENSOR12BITS_TDDO1 =       5,   //
-    parameter SENSOR12BITS_TRIGDLY =     8,   // delay between trigger input and start of output (VACT) in lines
-    parameter SENSOR12BITS_RAMP =        1,   // 1 - ramp, 0 - random (now - sensor.dat)
-    parameter SENSOR12BITS_NEW_BAYER =   0,   // 0 - "old" tiles (16x16, 1 - new - (18x18)   
+//    parameter SENSOR12BITS_TRIGDLY =     8,   // delay between trigger input and start of output (VACT) in lines
+//    parameter SENSOR12BITS_RAMP =        1,   // 1 - ramp, 0 - random (now - sensor.dat)
+//    parameter SENSOR12BITS_NEW_BAYER =   0,   // 0 - "old" tiles (16x16, 1 - new - (18x18)   
 
     parameter HISTOGRAM_LEFT =           0,   //2;   // left   
     parameter HISTOGRAM_TOP =            2,   // top
     parameter HISTOGRAM_WIDTH =          6,   // width
     parameter HISTOGRAM_HEIGHT =         6,   // height
     parameter HISTOGRAM_STRAT_PAGE =    20'h12345,
+    parameter FRAME_WIDTH_ROUND_BITS =  9,  // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
+    
     parameter WOI_WIDTH=                64
     
     
\ No newline at end of file

sensor/sens_parallel12.v

@@ -181,7 +181,6 @@ module  sens_parallel12 #(
     wire           hact_ext;     // received hact signal
     reg            hact_ext_r;   // received hact signal, delayed by 1 clock
     reg            hact_r;       // received or regenerated hact  
-    
     assign set_pxd_delay =   set_idelay[2:0];
     assign set_other_delay = set_idelay[3];
     assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin};
@@ -602,8 +601,8 @@ module  sens_parallel12 #(
 //        .CLKOUT4_USE_FINE_PS("FALSE"),
 //        .CLKOUT5_USE_FINE_PS("FALSE"),
 //        .CLKOUT6_USE_FINE_PS("FALSE"),
-        .CLKOUT0_DIVIDE_F    (4.000),
-        .CLKOUT1_DIVIDE      (8),
+        .CLKOUT0_DIVIDE_F    (8.000),
+        .CLKOUT1_DIVIDE      (4),
 //        .CLKOUT2_DIVIDE      (1),
 //        .CLKOUT3_DIVIDE      (1),
 //        .CLKOUT4_DIVIDE(1),

sensor/sens_sync.v

@@ -121,8 +121,8 @@ module  sens_sync#(
         if (pre_sof_out || !trigger_mode_pclk) overdue <= 1'b0;
         else if (trig_in_pclk)                 overdue <= trig_r;
         
-        if (!en || !trigger_mode_pclk) trig_r <=0;
-        else if (trig_in)              trig_r <= ~trig_r;
+        if (!en || !trigger_mode_pclk  || sof_in) trig_r <=0;
+        else if (trig_in_pclk)                    trig_r <= ~trig_r;
 
         // enforce minimal frame period (applies to both normal and delayed pulse (Make it only in free-running mode?)
         if (!en || !(&period_cntr)) period_dly <= 0;

sensor/sensor_channel.v

@@ -141,7 +141,7 @@ module  sensor_channel#(
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =      12,
     parameter SENSOR_FIFO_2DEPTH =     4,
-    parameter SENSOR_FIFO_DELAY =      7,
+    parameter SENSOR_FIFO_DELAY =      5, // 7,
     
     
     // sens_parallel12 other parameters

sensor/sensor_fifo.v

@@ -23,7 +23,7 @@
 module  sensor_fifo #(
     parameter SENSOR_DATA_WIDTH = 12,
     parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
-    parameter SENSOR_FIFO_DELAY = 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
+    parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
 )(
 //    input                          rst,
     input                          iclk, // input -synchronous clock
@@ -45,7 +45,8 @@ module  sensor_fifo #(
     reg                          sof_r,eof_r;
     wire we;
     // output clock domain
-    wire pre_re,re_w,re;
+//    wire                        pre_re;
+    wire                        re; // re_w,re;
     reg                         re_r;
     reg                   [1:0] pre_hact;
     reg                         hact_out_r;
@@ -86,14 +87,44 @@ module  sensor_fifo #(
     );
     
     // output clock domain
-    assign pre_re = nempty && !re_r;
-    assign re_w = re_r && nempty; // to protect from false positive on nempty
-    assign re = (re_w && !pre_hact) || hact_out_r;
+//    assign pre_re = nempty && !re_r;
+// Generating first read (for hact), then wait to fill half FIFO and continue continuous read until hact end
+//    assign re_w = re_r && nempty; // to protect from false positive on nempty
+//    assign re = (re_w && !pre_hact) || hact_out_r; // no check for nempty - producing un-interrupted stream
+    assign re = (re_r && nempty && !pre_hact[0]) || hact_out_r; // no check for nempty - producing un-interrupted stream
     assign pxd_out= pxd_r;
     assign data_valid = hact_out_r;
     assign sof = sof_r;
     assign eof = eof_r;
 
+    always @(posedge pclk) begin
+        if (prst) re_r <= 0;
+        else      re_r <= nempty && !re_r && !pre_hact[0]; // only generate one cycle (after SOF of HACT)
+
+        if    (prst) pre_hact[0] <= 0;
+        else if (re) pre_hact[0] <= hact_w;
+
+        if    (prst) pre_hact[1] <= 0;
+        else         pre_hact[1] <= pre_hact[0];
+
+
+        if    (prst) pxd_r <= 0;
+        else if (re) pxd_r <= pxd_w;
+
+        if      (prst)            hact_out_r <= 0;
+        else if (hact_out_start)  hact_out_r <= 1;
+//        else if (!hact_w)        hact_out_r <= 0;
+        else if (!(hact_w && re)) hact_out_r <= 0;
+
+        if (prst) sof_r <= 0;
+        else      sof_r <= re && sof_w;
+
+        if (prst) eof_r <= 0;
+        else      eof_r <= re && eof_w;
+
+    end
+     
+/*
     always @(posedge iclk) begin
         if (irst) re_r <= 0;
         else      re_r <= pre_re;
@@ -118,7 +149,7 @@ module  sensor_fifo #(
         else      eof_r <= re && eof_w;
 
     end
-    
+*/    
 
 
 endmodule

sensor/sensors393.v

@@ -140,7 +140,7 @@ module  sensors393 #(
     //sensor_fifo parameters
     parameter SENSOR_DATA_WIDTH =        12,
     parameter SENSOR_FIFO_2DEPTH =       4,
-    parameter SENSOR_FIFO_DELAY =        7,
+    parameter SENSOR_FIFO_DELAY =        5, // 7,
     // other parameters for histogram_saxi module
     parameter HIST_SAXI_ADDR_MASK =      'h7f0,
       parameter HIST_SAXI_MODE_WIDTH =   8,

simulation_modules/simul_saxi_gp_wr.v

@@ -163,10 +163,21 @@ Alex
             2'h0: next_wr_address_w[11:0] <= write_address[11:0];
             2'h1: next_wr_address_w[11:0] <= write_address[11:0] + (1 << wsize);
             2'h2:   case (wsize)
-                        2'h3:  next_wr_address_w[11:0] <= {(write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]},write_address[2:0]}; 
-                        2'h2:  next_wr_address_w[11:0] <= {(write_address[11:2] + 1) & {6'h3f, ~wlen[3:0]},write_address[1:0]}; 
-                        2'h1:  next_wr_address_w[11:0] <= {(write_address[11:1] + 1) & {7'h7f, ~wlen[3:0]},write_address[0:0]}; 
-                        2'h0:  next_wr_address_w[11:0] <=  (write_address[11:0] + 1) & {8'hff, ~wlen[3:0]}; 
+                        2'h3:  begin
+                                   next_wr_address_w[11:3] <= (write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]};
+                                   next_wr_address_w[ 2:0] <= write_address[2:0]; 
+                               end
+                        2'h2:  begin
+                                   next_wr_address_w[11:2] <= (write_address[11:2] + 1) & {6'h3f, ~wlen[3:0]};
+                                   next_wr_address_w[ 1:0] <=  write_address[1:0]; 
+                               end 
+                        2'h1:  begin
+                                   next_wr_address_w[11:1] <= (write_address[11:1] + 1) & {7'h7f, ~wlen[3:0]};
+                                   next_wr_address_w[0:0]    <= write_address[0:0];
+                               end  
+                        2'h0:  begin
+                                next_wr_address_w[11:0] <=  (write_address[11:0] + 1) & {8'hff, ~wlen[3:0]}; 
+                               end 
                     endcase
             2'h3: next_wr_address_w[11:0] <= 12'bx;          
         endcase

simulation_modules/simul_sensor12bits.v

@@ -174,7 +174,7 @@ end
 
 always @ (posedge MCLK) begin
 //   #1   stopped= !arst1 || (stoppedd  && !ARO) ;
-   #1   stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, ective low
+   #1   stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, active low
    #1   arst1=ARST;
 end
 

timing/rtc393.v

@@ -54,7 +54,7 @@ module  rtc393 #(
 //    output reg                    snap);       // take a snapshot (externally)
     
     wire  [31:0] cmd_data;
-    wire   [2:0] cmd_a;
+    wire   [1:0] cmd_a;
     wire         cmd_we; 
 
     wire         set_usec_w;  
@@ -125,7 +125,7 @@ module  rtc393 #(
         else if (refclk2x_mclk)         pre_cntr <= pre_cntr - 1;
         
         if (!enable_rtc) halfusec <= 0;
-        else             halfusec <= {halfusec[2:0], (|pre_cntr)?1'b0:1'b1};
+        else             halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
         
         if (set_usec_w)      pend_set_cntr <= 1'b0; // just to get rid of undefined
         if (set_sec_w)       pend_set_cntr <= 1'b1;
@@ -160,7 +160,7 @@ module  rtc393 #(
         .ADDR       (RTC_ADDR),
         .ADDR_MASK  (RTC_MASK),
         .NUM_CYCLES (6),
-        .ADDR_WIDTH (3),
+        .ADDR_WIDTH (2),
         .DATA_WIDTH (32)
     ) cmd_deser_32bit_i (
         .rst        (1'b0),     //rst),      // input

timing/timestamp_snapshot.v

@@ -29,7 +29,7 @@ module  timestamp_snapshot(
     input                sclk,
     input                srst, // @ posedge sclk - sync reset
     input                snap,
-    output               pre_stb, // one clock pulse before sending TS data
+    output reg           pre_stb, // one clock pulse before sending TS data
     output reg     [7:0] ts_data  // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
 );
     wire         snap_tclk;
@@ -38,8 +38,9 @@ module  timestamp_snapshot(
     reg          pulse_busy_r;
     reg    [2:0] cntr;
     reg          snd;
+    wire         pre_stb_w;
 
-    assign pre_stb = !pulse_busy && pulse_busy_r;
+    assign pre_stb_w = !pulse_busy && pulse_busy_r;
     
     always @ (posedge tclk) begin
         if (snap_tclk) sec_usec_snap <= {usec,sec};
@@ -49,6 +50,7 @@ module  timestamp_snapshot(
         if      (srst)                         snd <= 0;
         else if (!pulse_busy && pulse_busy_r)  snd <= 1;
         else if ((&cntr) || snap)              snd <= 0;
+        pre_stb <= pre_stb_w;
     end
 
     always @(posedge sclk) begin

timing/timing393.v

@@ -35,11 +35,12 @@ module  timing393       #(
     parameter CAMSYNC_TRIG_DELAY1 =             'h5, // setup input trigger delay
     parameter CAMSYNC_TRIG_DELAY2 =             'h6, // setup input trigger delay
     parameter CAMSYNC_TRIG_DELAY3 =             'h7, // setup input trigger delay
-    parameter CAMSYNC_SNDEN_BIT =               'h1, // enable writing ts_snd_en
-    parameter CAMSYNC_EXTERNAL_BIT =            'h3, // enable writing ts_external (0 - local timestamp in the frame header)
-    parameter CAMSYNC_TRIGGERED_BIT =           'h5, // triggered mode ( 0- async)
-    parameter CAMSYNC_MASTER_BIT =              'h8, // select a 2-bit master channel (master delay may be used as a flash delay)
-    parameter CAMSYNC_CHN_EN_BIT =              'hd, // per-channel enable timestamp generation
+    parameter CAMSYNC_EN_BIT =                  'h0, // enable module (0 - reset)
+    parameter CAMSYNC_SNDEN_BIT =               'h2, // enable writing ts_snd_en
+    parameter CAMSYNC_EXTERNAL_BIT =            'h4, // enable writing ts_external (0 - local timestamp in the frame header)
+    parameter CAMSYNC_TRIGGERED_BIT =           'h6, // triggered mode ( 0- async)
+    parameter CAMSYNC_MASTER_BIT =              'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
+    parameter CAMSYNC_CHN_EN_BIT =              'he, // per-channel enable timestamp generation
     parameter CAMSYNC_PRE_MAGIC =               6'b110100,
     parameter CAMSYNC_POST_MAGIC =              6'b001101,
     
@@ -223,6 +224,7 @@ module  timing393       #(
         .CAMSYNC_TRIG_DELAY1    (CAMSYNC_TRIG_DELAY1),
         .CAMSYNC_TRIG_DELAY2    (CAMSYNC_TRIG_DELAY2),
         .CAMSYNC_TRIG_DELAY3    (CAMSYNC_TRIG_DELAY3),
+        .CAMSYNC_EN_BIT         (CAMSYNC_EN_BIT),
         .CAMSYNC_SNDEN_BIT      (CAMSYNC_SNDEN_BIT),
         .CAMSYNC_EXTERNAL_BIT   (CAMSYNC_EXTERNAL_BIT),
         .CAMSYNC_TRIGGERED_BIT  (CAMSYNC_TRIGGERED_BIT),

x393.v

@@ -1835,6 +1835,7 @@ assign axi_grst = axi_rst_pre;
         .CAMSYNC_TRIG_DELAY1   (CAMSYNC_TRIG_DELAY1),
         .CAMSYNC_TRIG_DELAY2   (CAMSYNC_TRIG_DELAY2),
         .CAMSYNC_TRIG_DELAY3   (CAMSYNC_TRIG_DELAY3),
+        .CAMSYNC_EN_BIT        (CAMSYNC_EN_BIT),
         .CAMSYNC_SNDEN_BIT     (CAMSYNC_SNDEN_BIT),
         .CAMSYNC_EXTERNAL_BIT  (CAMSYNC_EXTERNAL_BIT),
         .CAMSYNC_TRIGGERED_BIT (CAMSYNC_TRIGGERED_BIT),