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x393
Commit bcaa005d authored by Andrey Filippov's avatar Andrey Filippov
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simulating/bug fixing

parent 9afdf9d6
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.settings/com.elphel.vdt.FPGA_project.prefs
View file @ bcaa005d
FPGA_project_0_SimulationTopFile=x393_testbench01.tf FPGA_project_0_SimulationTopFile=x393_testbench02.tf
FPGA_project_1_SimulationTopModule=x393_testbench01 FPGA_project_1_SimulationTopModule=x393_testbench02
FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@-> com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
......
includes/x393_localparams.vh
View file @ bcaa005d
...@@ -117,7 +117,11 @@ ...@@ -117,7 +117,11 @@
localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT; localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT;
localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
localparam FRAME_START_ADDRESS_INC= 'h 800; localparam FRAME_START_ADDRESS_INC= 'h800;
localparam LAST_BUF_FRAME = 1;
localparam CAMSYNC_DELAY = 200;
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes) localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
// localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words // localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words
...@@ -156,4 +160,5 @@ ...@@ -156,4 +160,5 @@
localparam TEST01_SUSPEND= 4; // SuppressThisWarning VEditor - not used localparam TEST01_SUSPEND= 4; // SuppressThisWarning VEditor - not used
localparam TEST_INITIAL_BURST= 4; // 3; localparam TEST_INITIAL_BURST= 4; // 3;
\ No newline at end of file
includes/x393_parameters.vh
View file @ bcaa005d
...@@ -431,7 +431,7 @@ ...@@ -431,7 +431,7 @@
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 4'd7, parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
// other parameters for histogram_saxi module // other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8, parameter HIST_SAXI_MODE_WIDTH = 8,
...@@ -615,11 +615,13 @@ ...@@ -615,11 +615,13 @@
parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay
parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en
parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset)
parameter CAMSYNC_TRIGGERED_BIT = 'h5, // triggered mode ( 0- async) parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en
parameter CAMSYNC_MASTER_BIT = 'h8, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header)
parameter CAMSYNC_CHN_EN_BIT = 'hd, // per-channel enable timestamp generation parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async)
parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101, parameter CAMSYNC_POST_MAGIC = 6'b001101,
......
includes/x393_simulation_parameters.vh
View file @ bcaa005d
...@@ -28,16 +28,16 @@ ...@@ -28,16 +28,16 @@
parameter SIMUL_AXI_READ_WIDTH=16, parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0, parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 10.417, parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
parameter FCLK1_PERIOD = 0.0, parameter FCLK1_PERIOD = 0.0,
parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks // parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288; // parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288;
parameter SENSOR12BITS_NROWS = 18, // 16; // 1032; // parameter SENSOR12BITS_NROWS = 18, // 16; // 1032;
parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact // parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact
parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
parameter SENSOR12BITS_NBPF = 20, //16; // bpf length // parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR12BITS_NGPL = 8, // bpf to hact parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; // //parameter tMD = 14; //
...@@ -45,15 +45,17 @@ ...@@ -45,15 +45,17 @@
parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TDDO1 = 5, //
parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) // parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) // parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
parameter HISTOGRAM_LEFT = 0, //2; // left parameter HISTOGRAM_LEFT = 0, //2; // left
parameter HISTOGRAM_TOP = 2, // top parameter HISTOGRAM_TOP = 2, // top
parameter HISTOGRAM_WIDTH = 6, // width parameter HISTOGRAM_WIDTH = 6, // width
parameter HISTOGRAM_HEIGHT = 6, // height parameter HISTOGRAM_HEIGHT = 6, // height
parameter HISTOGRAM_STRAT_PAGE = 20'h12345, parameter HISTOGRAM_STRAT_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64 parameter WOI_WIDTH= 64
\ No newline at end of file
sensor/sens_parallel12.v
View file @ bcaa005d
...@@ -181,7 +181,6 @@ module sens_parallel12 #( ...@@ -181,7 +181,6 @@ module sens_parallel12 #(
wire hact_ext; // received hact signal wire hact_ext; // received hact signal
reg hact_ext_r; // received hact signal, delayed by 1 clock reg hact_ext_r; // received hact signal, delayed by 1 clock
reg hact_r; // received or regenerated hact reg hact_r; // received or regenerated hact
assign set_pxd_delay = set_idelay[2:0]; assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3]; assign set_other_delay = set_idelay[3];
assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin}; assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin};
...@@ -602,8 +601,8 @@ module sens_parallel12 #( ...@@ -602,8 +601,8 @@ module sens_parallel12 #(
// .CLKOUT4_USE_FINE_PS("FALSE"), // .CLKOUT4_USE_FINE_PS("FALSE"),
// .CLKOUT5_USE_FINE_PS("FALSE"), // .CLKOUT5_USE_FINE_PS("FALSE"),
// .CLKOUT6_USE_FINE_PS("FALSE"), // .CLKOUT6_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (4.000), .CLKOUT0_DIVIDE_F (8.000),
.CLKOUT1_DIVIDE (8), .CLKOUT1_DIVIDE (4),
// .CLKOUT2_DIVIDE (1), // .CLKOUT2_DIVIDE (1),
// .CLKOUT3_DIVIDE (1), // .CLKOUT3_DIVIDE (1),
// .CLKOUT4_DIVIDE(1), // .CLKOUT4_DIVIDE(1),
......
sensor/sens_sync.v
View file @ bcaa005d
...@@ -113,7 +113,7 @@ module sens_sync#( ...@@ -113,7 +113,7 @@ module sens_sync#(
else if (!sof_dly) lines_left <= line_dly_pclk; else if (!sof_dly) lines_left <= line_dly_pclk;
else if (hact_single) lines_left <= lines_left - 1; else if (hact_single) lines_left <= lines_left - 1;
trigger_mode_pclk <= trigger_mode; trigger_mode_pclk <= trigger_mode;
if (!trigger_mode_pclk || !en) en_vacts_free<= 1'b1; if (!trigger_mode_pclk || !en) en_vacts_free<= 1'b1;
else if (sof_in) en_vacts_free<= 1'b0; else if (sof_in) en_vacts_free<= 1'b0;
...@@ -121,8 +121,8 @@ module sens_sync#( ...@@ -121,8 +121,8 @@ module sens_sync#(
if (pre_sof_out || !trigger_mode_pclk) overdue <= 1'b0; if (pre_sof_out || !trigger_mode_pclk) overdue <= 1'b0;
else if (trig_in_pclk) overdue <= trig_r; else if (trig_in_pclk) overdue <= trig_r;
if (!en || !trigger_mode_pclk) trig_r <=0; if (!en || !trigger_mode_pclk || sof_in) trig_r <=0;
else if (trig_in) trig_r <= ~trig_r; else if (trig_in_pclk) trig_r <= ~trig_r;
// enforce minimal frame period (applies to both normal and delayed pulse (Make it only in free-running mode?) // enforce minimal frame period (applies to both normal and delayed pulse (Make it only in free-running mode?)
if (!en || !(&period_cntr)) period_dly <= 0; if (!en || !(&period_cntr)) period_dly <= 0;
......
sensor/sensor_channel.v
View file @ bcaa005d
...@@ -141,7 +141,7 @@ module sensor_channel#( ...@@ -141,7 +141,7 @@ module sensor_channel#(
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 7, parameter SENSOR_FIFO_DELAY = 5, // 7,
// sens_parallel12 other parameters // sens_parallel12 other parameters
......
sensor/sensor_fifo.v
View file @ bcaa005d
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
module sensor_fifo #( module sensor_fifo #(
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)( )(
// input rst, // input rst,
input iclk, // input -synchronous clock input iclk, // input -synchronous clock
...@@ -45,7 +45,8 @@ module sensor_fifo #( ...@@ -45,7 +45,8 @@ module sensor_fifo #(
reg sof_r,eof_r; reg sof_r,eof_r;
wire we; wire we;
// output clock domain // output clock domain
wire pre_re,re_w,re; // wire pre_re;
wire re; // re_w,re;
reg re_r; reg re_r;
reg [1:0] pre_hact; reg [1:0] pre_hact;
reg hact_out_r; reg hact_out_r;
...@@ -86,14 +87,44 @@ module sensor_fifo #( ...@@ -86,14 +87,44 @@ module sensor_fifo #(
); );
// output clock domain // output clock domain
assign pre_re = nempty && !re_r; // assign pre_re = nempty && !re_r;
assign re_w = re_r && nempty; // to protect from false positive on nempty // Generating first read (for hact), then wait to fill half FIFO and continue continuous read until hact end
assign re = (re_w && !pre_hact) || hact_out_r; // assign re_w = re_r && nempty; // to protect from false positive on nempty
// assign re = (re_w && !pre_hact) || hact_out_r; // no check for nempty - producing un-interrupted stream
assign re = (re_r && nempty && !pre_hact[0]) || hact_out_r; // no check for nempty - producing un-interrupted stream
assign pxd_out= pxd_r; assign pxd_out= pxd_r;
assign data_valid = hact_out_r; assign data_valid = hact_out_r;
assign sof = sof_r; assign sof = sof_r;
assign eof = eof_r; assign eof = eof_r;
always @(posedge pclk) begin
if (prst) re_r <= 0;
else re_r <= nempty && !re_r && !pre_hact[0]; // only generate one cycle (after SOF of HACT)
if (prst) pre_hact[0] <= 0;
else if (re) pre_hact[0] <= hact_w;
if (prst) pre_hact[1] <= 0;
else pre_hact[1] <= pre_hact[0];
if (prst) pxd_r <= 0;
else if (re) pxd_r <= pxd_w;
if (prst) hact_out_r <= 0;
else if (hact_out_start) hact_out_r <= 1;
// else if (!hact_w) hact_out_r <= 0;
else if (!(hact_w && re)) hact_out_r <= 0;
if (prst) sof_r <= 0;
else sof_r <= re && sof_w;
if (prst) eof_r <= 0;
else eof_r <= re && eof_w;
end
/*
always @(posedge iclk) begin always @(posedge iclk) begin
if (irst) re_r <= 0; if (irst) re_r <= 0;
else re_r <= pre_re; else re_r <= pre_re;
...@@ -118,7 +149,7 @@ module sensor_fifo #( ...@@ -118,7 +149,7 @@ module sensor_fifo #(
else eof_r <= re && eof_w; else eof_r <= re && eof_w;
end end
*/
endmodule endmodule
......
sensor/sensors393.v
View file @ bcaa005d
...@@ -140,7 +140,7 @@ module sensors393 #( ...@@ -140,7 +140,7 @@ module sensors393 #(
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 7, parameter SENSOR_FIFO_DELAY = 5, // 7,
// other parameters for histogram_saxi module // other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8, parameter HIST_SAXI_MODE_WIDTH = 8,
......
simulation_modules/simul_saxi_gp_wr.v
View file @ bcaa005d
...@@ -163,10 +163,21 @@ Alex ...@@ -163,10 +163,21 @@ Alex
2'h0: next_wr_address_w[11:0] <= write_address[11:0]; 2'h0: next_wr_address_w[11:0] <= write_address[11:0];
2'h1: next_wr_address_w[11:0] <= write_address[11:0] + (1 << wsize); 2'h1: next_wr_address_w[11:0] <= write_address[11:0] + (1 << wsize);
2'h2: case (wsize) 2'h2: case (wsize)
2'h3: next_wr_address_w[11:0] <= {(write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]},write_address[2:0]}; 2'h3: begin
2'h2: next_wr_address_w[11:0] <= {(write_address[11:2] + 1) & {6'h3f, ~wlen[3:0]},write_address[1:0]}; next_wr_address_w[11:3] <= (write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]};
2'h1: next_wr_address_w[11:0] <= {(write_address[11:1] + 1) & {7'h7f, ~wlen[3:0]},write_address[0:0]}; next_wr_address_w[ 2:0] <= write_address[2:0];
2'h0: next_wr_address_w[11:0] <= (write_address[11:0] + 1) & {8'hff, ~wlen[3:0]}; end
2'h2: begin
next_wr_address_w[11:2] <= (write_address[11:2] + 1) & {6'h3f, ~wlen[3:0]};
next_wr_address_w[ 1:0] <= write_address[1:0];
end
2'h1: begin
next_wr_address_w[11:1] <= (write_address[11:1] + 1) & {7'h7f, ~wlen[3:0]};
next_wr_address_w[0:0] <= write_address[0:0];
end
2'h0: begin
next_wr_address_w[11:0] <= (write_address[11:0] + 1) & {8'hff, ~wlen[3:0]};
end
endcase endcase
2'h3: next_wr_address_w[11:0] <= 12'bx; 2'h3: next_wr_address_w[11:0] <= 12'bx;
endcase endcase
......
simulation_modules/simul_sensor12bits.v
View file @ bcaa005d
...@@ -174,7 +174,7 @@ end ...@@ -174,7 +174,7 @@ end
always @ (posedge MCLK) begin always @ (posedge MCLK) begin
// #1 stopped= !arst1 || (stoppedd && !ARO) ; // #1 stopped= !arst1 || (stoppedd && !ARO) ;
#1 stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, ective low #1 stopped= !arst1 || ((stoppedd || (state== s_frame_done)) && ARO) ; /// ARO tow TRIGGER, active low
#1 arst1=ARST; #1 arst1=ARST;
end end
......
timing/camsync393.v
View file @ bcaa005d
...@@ -30,26 +30,27 @@ ...@@ -30,26 +30,27 @@
//`define GENERATE_TRIG_OVERDUE 1 //`define GENERATE_TRIG_OVERDUE 1
`undef GENERATE_TRIG_OVERDUE `undef GENERATE_TRIG_OVERDUE
module camsync393 #( module camsync393 #(
parameter CAMSYNC_ADDR = 'h160, //TODO: assign valid address parameter CAMSYNC_ADDR = 'h160, //TODO: assign valid address
parameter CAMSYNC_MASK = 'h7f8, parameter CAMSYNC_MASK = 'h7f8,
parameter CAMSYNC_MODE = 'h0, parameter CAMSYNC_MODE = 'h0,
parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source
parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s) parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s)
parameter CAMSYNC_TRIG_PERIOD = 'h3, // setup output trigger period parameter CAMSYNC_TRIG_PERIOD = 'h3, // setup output trigger period
parameter CAMSYNC_TRIG_DELAY0 = 'h4, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY0 = 'h4, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay
parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset)
parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en
parameter CAMSYNC_TRIGGERED_BIT = 'h5, // triggered mode ( 0- async) parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header)
parameter CAMSYNC_MASTER_BIT = 'h8, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async)
parameter CAMSYNC_CHN_EN_BIT = 'hd, // per-channel enable timestamp generation parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101 parameter CAMSYNC_POST_MAGIC = 6'b001101
)( )(
// input rst, // global reset // input rst, // global reset
...@@ -143,7 +144,10 @@ module camsync393 #( ...@@ -143,7 +144,10 @@ module camsync393 #(
output ts_rcv_stb_chn3, // 1 clock before ts_rcv_data is valid output ts_rcv_stb_chn3, // 1 clock before ts_rcv_data is valid
output [7:0] ts_rcv_data_chn3 // byte-wide serialized timestamp message received or local output [7:0] ts_rcv_data_chn3 // byte-wide serialized timestamp message received or local
); );
reg en = 0; // enable camsync module
// wire rst = mrst || !en;
wire en_pclk;
wire eprst = prst || !en_pclk;
reg ts_snd_en; // enable sending timestamp over sync line reg ts_snd_en; // enable sending timestamp over sync line
reg ts_external; // 1 - use external timestamp, if available. 0 - always use local ts reg ts_external; // 1 - use external timestamp, if available. 0 - always use local ts
reg triggered_mode_r; reg triggered_mode_r;
...@@ -334,7 +338,7 @@ module camsync393 #( ...@@ -334,7 +338,7 @@ module camsync393 #(
assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10], assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10],
cmd_data[8],cmd_data[6],cmd_data[4],cmd_data[2],cmd_data[0]}; cmd_data[8],cmd_data[6],cmd_data[4],cmd_data[2],cmd_data[0]};
assign triggered_mode = triggered_mode_r; assign triggered_mode = triggered_mode_r;
assign {ts_snap_mclk_chn3, ts_snap_mclk_chn2, ts_snap_mclk_chn1, ts_snap_mclk_chn0 } = triggered_mode? ts_snap_triggered_mclk: frame_sync; assign {ts_snap_mclk_chn3, ts_snap_mclk_chn2, ts_snap_mclk_chn1, ts_snap_mclk_chn0 } = {4{en}} & (triggered_mode? ts_snap_triggered_mclk: frame_sync);
// keep previous value if 2'b01 // keep previous value if 2'b01
// assign input_use_w = pre_input_use | (~pre_input_use & pre_input_pattern & input_use); // assign input_use_w = pre_input_use | (~pre_input_use & pre_input_pattern & input_use);
wire [9:0] input_mask = pre_input_pattern | ~pre_input_use; wire [9:0] input_mask = pre_input_pattern | ~pre_input_use;
...@@ -352,6 +356,7 @@ module camsync393 #( ...@@ -352,6 +356,7 @@ module camsync393 #(
always @(posedge mclk) begin always @(posedge mclk) begin
if (set_mode_reg_w) begin if (set_mode_reg_w) begin
en <= cmd_data[CAMSYNC_EN_BIT];
if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1]; if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1];
if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1]; if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
if (cmd_data[CAMSYNC_TRIGGERED_BIT]) triggered_mode_r <= cmd_data[CAMSYNC_TRIGGERED_BIT - 1]; if (cmd_data[CAMSYNC_TRIGGERED_BIT]) triggered_mode_r <= cmd_data[CAMSYNC_TRIGGERED_BIT - 1];
...@@ -359,7 +364,11 @@ module camsync393 #( ...@@ -359,7 +364,11 @@ module camsync393 #(
if (cmd_data[CAMSYNC_CHN_EN_BIT]) chn_en <= cmd_data[CAMSYNC_CHN_EN_BIT - 1 -: 4]; if (cmd_data[CAMSYNC_CHN_EN_BIT]) chn_en <= cmd_data[CAMSYNC_CHN_EN_BIT - 1 -: 4];
end end
if (mrst) input_use <= 0; if (mrst) input_use <= 0;
else if (set_trig_src_w) begin if (!en) begin
input_use <= 0;
input_pattern <= 0;
pre_input_use_intern <= 0; // use internal source for triggering
end else if (set_trig_src_w) begin
input_use <= input_use_w; input_use <= input_use_w;
input_pattern <= input_pattern_w; input_pattern <= input_pattern_w;
pre_input_use_intern <= (input_use_w == 0); // use internal source for triggering pre_input_use_intern <= (input_use_w == 0); // use internal source for triggering
...@@ -381,7 +390,11 @@ module camsync393 #( ...@@ -381,7 +390,11 @@ module camsync393 #(
input_dly_chn3[31:0] <= cmd_data[31:0]; input_dly_chn3[31:0] <= cmd_data[31:0];
end end
if (set_trig_dst_w) begin if (!en) begin
gpio_out_en_r[9:0] <= 0;
gpio_active[9:0] <= 0;
testmode <= 0;
end else if (set_trig_dst_w) begin
gpio_out_en_r[9:0] <= gpio_out_en_w; gpio_out_en_r[9:0] <= gpio_out_en_w;
gpio_active[9:0] <= gpio_active_w; gpio_active[9:0] <= gpio_active_w;
testmode <= cmd_data[24]; testmode <= cmd_data[24];
...@@ -402,8 +415,9 @@ module camsync393 #( ...@@ -402,8 +415,9 @@ module camsync393 #(
start <= start0; start <= start0;
start_d <= start; start_d <= start;
start_en <= (repeat_period[31:0]!=0); start_en <= en && (repeat_period[31:0]!=0);
if (set_period) rep_en <= !high_zero; if (!en) rep_en <= 0;
else if (set_period) rep_en <= !high_zero;
end end
always @ (posedge pclk) begin always @ (posedge pclk) begin
case (master_chn) case (master_chn)
...@@ -433,7 +447,8 @@ module camsync393 #( ...@@ -433,7 +447,8 @@ module camsync393 #(
input_use_intern <= pre_input_use_intern; input_use_intern <= pre_input_use_intern;
ts_external_pclk<= ts_external && !input_use_intern; ts_external_pclk<= ts_external && !input_use_intern;
start_pclk[2:0] <= {(restart && rep_en) || (start_pclk[1] && !restart_cntr_run[1] && !restart_cntr_run[0] && !start_pclk[2]), start_pclk[2:0] <= {(restart && rep_en) ||
(start_pclk[1] && !restart_cntr_run[1] && !restart_cntr_run[0] && !start_pclk[2]),
start_pclk[0], start_pclk[0],
start_to_pclk && !start_pclk[0]}; start_to_pclk && !start_pclk[0]};
restart_cntr_run[1:0] <= {restart_cntr_run[0],start_en && (start_pclk[2] || (restart_cntr_run[0] && (restart_cntr[31:2] !=0)))}; restart_cntr_run[1:0] <= {restart_cntr_run[0],start_en && (start_pclk[2] || (restart_cntr_run[0] && (restart_cntr[31:2] !=0)))};
...@@ -466,7 +481,7 @@ module camsync393 #( ...@@ -466,7 +481,7 @@ module camsync393 #(
end end
always @ (posedge pclk) begin always @ (posedge pclk) begin
if (prst) dly_cntr_run <= 0; if (eprst) dly_cntr_run <= 0;
else if (!triggered_mode_pclk) dly_cntr_run <= 0; else if (!triggered_mode_pclk) dly_cntr_run <= 0;
else if (start_dly) dly_cntr_run <= 4'hf; else if (start_dly) dly_cntr_run <= 4'hf;
else dly_cntr_run <= dly_cntr_run & else dly_cntr_run <= dly_cntr_run &
...@@ -478,11 +493,11 @@ module camsync393 #( ...@@ -478,11 +493,11 @@ module camsync393 #(
`ifdef GENERATE_TRIG_OVERDUE `ifdef GENERATE_TRIG_OVERDUE
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) trigger_r <= 0; if (rst) trigger_r <= 0;
else if (!triggered_mode) trigger_r <= 0; else if (!triggered_mode) trigger_r <= 0;
else trigger_r <= ~frame_sync & (trig_r_mclk ^ trigger_r); else trigger_r <= ~frame_sync & (trig_r_mclk ^ trigger_r);
if (mrst) overdue <= 0; if (rst) overdue <= 0;
else if (!triggered_mode) overdue <= 0; else if (!triggered_mode) overdue <= 0;
else overdue <= ((overdue ^ trigger_r) & trig_r_mclk) ^ overdue; else overdue <= ((overdue ^ trigger_r) & trig_r_mclk) ^ overdue;
...@@ -683,25 +698,35 @@ module camsync393 #( ...@@ -683,25 +698,35 @@ module camsync393 #(
.tdata (ts_rcv_data_chn3) // output[7:0] reg .tdata (ts_rcv_data_chn3) // output[7:0] reg
); );
level_cross_clocks #(
.WIDTH(1),
.REGISTER(2)
) level_cross_clocks_en_pclki (
.clk (pclk), // input
.d_in (en), // input[0:0]
.d_out (en_pclk) // output[0:0]
);
assign {ts_rcv_stb_chn3, ts_rcv_stb_chn2, ts_rcv_stb_chn1, ts_rcv_stb_chn0}= ts_stb; assign {ts_rcv_stb_chn3, ts_rcv_stb_chn2, ts_rcv_stb_chn1, ts_rcv_stb_chn0}= ts_stb;
pulse_cross_clock i_start_to_pclk (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(start_d && start_en), .out_pulse(start_to_pclk),.busy()); pulse_cross_clock i_start_to_pclk (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(start_d && start_en), .out_pulse(start_to_pclk),.busy());
pulse_cross_clock i_ts_snap_mclk0 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy()); pulse_cross_clock i_ts_snap_mclk0 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy());
pulse_cross_clock i_ts_snap_mclk1 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy()); pulse_cross_clock i_ts_snap_mclk1 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy());
pulse_cross_clock i_ts_snap_mclk2 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy()); pulse_cross_clock i_ts_snap_mclk2 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
pulse_cross_clock i_ts_snap_mclk3 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy()); pulse_cross_clock i_ts_snap_mclk3 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());
pulse_cross_clock i_rcv_done_mclk (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy()); pulse_cross_clock i_rcv_done_mclk (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());
pulse_cross_clock i_local_got_pclk0(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[0]), .out_pulse(local_got_pclk[0]),.busy()); pulse_cross_clock i_local_got_pclk0(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[0]), .out_pulse(local_got_pclk[0]),.busy());
pulse_cross_clock i_local_got_pclk1(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[1]), .out_pulse(local_got_pclk[1]),.busy()); pulse_cross_clock i_local_got_pclk1(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[1]), .out_pulse(local_got_pclk[1]),.busy());
pulse_cross_clock i_local_got_pclk2(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[2]), .out_pulse(local_got_pclk[2]),.busy()); pulse_cross_clock i_local_got_pclk2(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[2]), .out_pulse(local_got_pclk[2]),.busy());
pulse_cross_clock i_local_got_pclk3(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[3]), .out_pulse(local_got_pclk[3]),.busy()); pulse_cross_clock i_local_got_pclk3(.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(local_got[3]), .out_pulse(local_got_pclk[3]),.busy());
pulse_cross_clock i_trig_r_mclk0 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[0]), .out_pulse(trig_r_mclk[0]),.busy()); pulse_cross_clock i_trig_r_mclk0 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[0]), .out_pulse(trig_r_mclk[0]),.busy());
pulse_cross_clock i_trig_r_mclk1 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[1]), .out_pulse(trig_r_mclk[1]),.busy()); pulse_cross_clock i_trig_r_mclk1 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[1]), .out_pulse(trig_r_mclk[1]),.busy());
pulse_cross_clock i_trig_r_mclk2 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[2]), .out_pulse(trig_r_mclk[2]),.busy()); pulse_cross_clock i_trig_r_mclk2 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[2]), .out_pulse(trig_r_mclk[2]),.busy());
pulse_cross_clock i_trig_r_mclk3 (.rst(prst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[3]), .out_pulse(trig_r_mclk[3]),.busy()); pulse_cross_clock i_trig_r_mclk3 (.rst(eprst), .src_clk(pclk), .dst_clk(mclk), .in_pulse(trig_r[3]), .out_pulse(trig_r_mclk[3]),.busy());
endmodule endmodule
timing/rtc393.v
View file @ bcaa005d
...@@ -54,7 +54,7 @@ module rtc393 #( ...@@ -54,7 +54,7 @@ module rtc393 #(
// output reg snap); // take a snapshot (externally) // output reg snap); // take a snapshot (externally)
wire [31:0] cmd_data; wire [31:0] cmd_data;
wire [2:0] cmd_a; wire [1:0] cmd_a;
wire cmd_we; wire cmd_we;
wire set_usec_w; wire set_usec_w;
...@@ -125,7 +125,7 @@ module rtc393 #( ...@@ -125,7 +125,7 @@ module rtc393 #(
else if (refclk2x_mclk) pre_cntr <= pre_cntr - 1; else if (refclk2x_mclk) pre_cntr <= pre_cntr - 1;
if (!enable_rtc) halfusec <= 0; if (!enable_rtc) halfusec <= 0;
else halfusec <= {halfusec[2:0], (|pre_cntr)?1'b0:1'b1}; else halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
if (set_usec_w) pend_set_cntr <= 1'b0; // just to get rid of undefined if (set_usec_w) pend_set_cntr <= 1'b0; // just to get rid of undefined
if (set_sec_w) pend_set_cntr <= 1'b1; if (set_sec_w) pend_set_cntr <= 1'b1;
...@@ -160,7 +160,7 @@ module rtc393 #( ...@@ -160,7 +160,7 @@ module rtc393 #(
.ADDR (RTC_ADDR), .ADDR (RTC_ADDR),
.ADDR_MASK (RTC_MASK), .ADDR_MASK (RTC_MASK),
.NUM_CYCLES (6), .NUM_CYCLES (6),
.ADDR_WIDTH (3), .ADDR_WIDTH (2),
.DATA_WIDTH (32) .DATA_WIDTH (32)
) cmd_deser_32bit_i ( ) cmd_deser_32bit_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
......
timing/timestamp_snapshot.v
View file @ bcaa005d
...@@ -29,7 +29,7 @@ module timestamp_snapshot( ...@@ -29,7 +29,7 @@ module timestamp_snapshot(
input sclk, input sclk,
input srst, // @ posedge sclk - sync reset input srst, // @ posedge sclk - sync reset
input snap, input snap,
output pre_stb, // one clock pulse before sending TS data output reg pre_stb, // one clock pulse before sending TS data
output reg [7:0] ts_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0) output reg [7:0] ts_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
); );
wire snap_tclk; wire snap_tclk;
...@@ -38,8 +38,9 @@ module timestamp_snapshot( ...@@ -38,8 +38,9 @@ module timestamp_snapshot(
reg pulse_busy_r; reg pulse_busy_r;
reg [2:0] cntr; reg [2:0] cntr;
reg snd; reg snd;
wire pre_stb_w;
assign pre_stb = !pulse_busy && pulse_busy_r; assign pre_stb_w = !pulse_busy && pulse_busy_r;
always @ (posedge tclk) begin always @ (posedge tclk) begin
if (snap_tclk) sec_usec_snap <= {usec,sec}; if (snap_tclk) sec_usec_snap <= {usec,sec};
...@@ -49,6 +50,7 @@ module timestamp_snapshot( ...@@ -49,6 +50,7 @@ module timestamp_snapshot(
if (srst) snd <= 0; if (srst) snd <= 0;
else if (!pulse_busy && pulse_busy_r) snd <= 1; else if (!pulse_busy && pulse_busy_r) snd <= 1;
else if ((&cntr) || snap) snd <= 0; else if ((&cntr) || snap) snd <= 0;
pre_stb <= pre_stb_w;
end end
always @(posedge sclk) begin always @(posedge sclk) begin
......
timing/timing393.v
View file @ bcaa005d
...@@ -35,11 +35,12 @@ module timing393 #( ...@@ -35,11 +35,12 @@ module timing393 #(
parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay
parameter CAMSYNC_SNDEN_BIT = 'h1, // enable writing ts_snd_en parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset)
parameter CAMSYNC_EXTERNAL_BIT = 'h3, // enable writing ts_external (0 - local timestamp in the frame header) parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en
parameter CAMSYNC_TRIGGERED_BIT = 'h5, // triggered mode ( 0- async) parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header)
parameter CAMSYNC_MASTER_BIT = 'h8, // select a 2-bit master channel (master delay may be used as a flash delay) parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async)
parameter CAMSYNC_CHN_EN_BIT = 'hd, // per-channel enable timestamp generation parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
parameter CAMSYNC_PRE_MAGIC = 6'b110100, parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101, parameter CAMSYNC_POST_MAGIC = 6'b001101,
...@@ -223,6 +224,7 @@ module timing393 #( ...@@ -223,6 +224,7 @@ module timing393 #(
.CAMSYNC_TRIG_DELAY1 (CAMSYNC_TRIG_DELAY1), .CAMSYNC_TRIG_DELAY1 (CAMSYNC_TRIG_DELAY1),
.CAMSYNC_TRIG_DELAY2 (CAMSYNC_TRIG_DELAY2), .CAMSYNC_TRIG_DELAY2 (CAMSYNC_TRIG_DELAY2),
.CAMSYNC_TRIG_DELAY3 (CAMSYNC_TRIG_DELAY3), .CAMSYNC_TRIG_DELAY3 (CAMSYNC_TRIG_DELAY3),
.CAMSYNC_EN_BIT (CAMSYNC_EN_BIT),
.CAMSYNC_SNDEN_BIT (CAMSYNC_SNDEN_BIT), .CAMSYNC_SNDEN_BIT (CAMSYNC_SNDEN_BIT),
.CAMSYNC_EXTERNAL_BIT (CAMSYNC_EXTERNAL_BIT), .CAMSYNC_EXTERNAL_BIT (CAMSYNC_EXTERNAL_BIT),
.CAMSYNC_TRIGGERED_BIT (CAMSYNC_TRIGGERED_BIT), .CAMSYNC_TRIGGERED_BIT (CAMSYNC_TRIGGERED_BIT),
......
x393.v
View file @ bcaa005d
...@@ -1835,6 +1835,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1835,6 +1835,7 @@ assign axi_grst = axi_rst_pre;
.CAMSYNC_TRIG_DELAY1 (CAMSYNC_TRIG_DELAY1), .CAMSYNC_TRIG_DELAY1 (CAMSYNC_TRIG_DELAY1),
.CAMSYNC_TRIG_DELAY2 (CAMSYNC_TRIG_DELAY2), .CAMSYNC_TRIG_DELAY2 (CAMSYNC_TRIG_DELAY2),
.CAMSYNC_TRIG_DELAY3 (CAMSYNC_TRIG_DELAY3), .CAMSYNC_TRIG_DELAY3 (CAMSYNC_TRIG_DELAY3),
.CAMSYNC_EN_BIT (CAMSYNC_EN_BIT),
.CAMSYNC_SNDEN_BIT (CAMSYNC_SNDEN_BIT), .CAMSYNC_SNDEN_BIT (CAMSYNC_SNDEN_BIT),
.CAMSYNC_EXTERNAL_BIT (CAMSYNC_EXTERNAL_BIT), .CAMSYNC_EXTERNAL_BIT (CAMSYNC_EXTERNAL_BIT),
.CAMSYNC_TRIGGERED_BIT (CAMSYNC_TRIGGERED_BIT), .CAMSYNC_TRIGGERED_BIT (CAMSYNC_TRIGGERED_BIT),
......
x393_testbench02.tf
View file @ bcaa005d
...@@ -43,8 +43,11 @@ ...@@ -43,8 +43,11 @@
//`define TEST_TILED_WRITE32 1 //`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1 //`define TEST_TILED_READ32 1
`define TEST_AFI_WRITE 1 //`define TEST_AFI_WRITE 1
`define TEST_AFI_READ 1 //`define TEST_AFI_READ 1
`define TEST_SENSOR 0
module x393_testbench02 #( module x393_testbench02 #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used `include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
...@@ -54,7 +57,7 @@ module x393_testbench02 #( ...@@ -54,7 +57,7 @@ module x393_testbench02 #(
`ifdef IVERILOG `ifdef IVERILOG
// $display("IVERILOG is defined"); // $display("IVERILOG is defined");
`ifdef NON_VDT_ENVIROMENT `ifdef NON_VDT_ENVIROMENT
parameter lxtname="x393.lxt"; parameter fstname="x393.fst";
`else `else
`include "IVERILOG_INCLUDE.v" `include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT `endif // NON_VDT_ENVIROMENT
...@@ -62,12 +65,12 @@ module x393_testbench02 #( ...@@ -62,12 +65,12 @@ module x393_testbench02 #(
// $display("IVERILOG is not defined"); // $display("IVERILOG is not defined");
`ifdef CVC `ifdef CVC
`ifdef NON_VDT_ENVIROMENT `ifdef NON_VDT_ENVIROMENT
parameter lxtname = "x393.fst"; parameter fstname = "x393.fst";
`else // NON_VDT_ENVIROMENT `else // NON_VDT_ENVIROMENT
`include "IVERILOG_INCLUDE.v" `include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT `endif // NON_VDT_ENVIROMENT
`else `else
parameter lxtname = "x393.lxt"; parameter fstname = "x393.fst";
`endif // CVC `endif // CVC
`endif // IVERILOG `endif // IVERILOG
`define DEBUG_WR_SINGLE 1 `define DEBUG_WR_SINGLE 1
...@@ -75,9 +78,14 @@ module x393_testbench02 #( ...@@ -75,9 +78,14 @@ module x393_testbench02 #(
//`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh //`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh `include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used parameter TRIGGER_MODE = 1; // 0 - auto, 1 - triggered
parameter EXT_TRIGGER_MODE = 1 ; // 0 - internal, 1 - external trigger (camsync)
parameter EXTERNAL_TIMESTAMP = 1 ; // embed local timestamp, 1 - embed received timestamp
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// VDT - incorrect real number calculation
// localparam FRAME_COMPRESS_CYCLES_INPUT=(FRAME_COMPRESS_CYCLES * CLK0_PER) /CLK1_PER;
// localparam real FRAME_COMPRESS_CYCLES_INPUT=(CLK0_PER * CLK0_PER);
// ========================== parameters from x353 =================================== // ========================== parameters from x353 ===================================
`ifdef SYNC_COMPRESS `ifdef SYNC_COMPRESS
...@@ -133,7 +141,14 @@ module x393_testbench02 #( ...@@ -133,7 +141,14 @@ module x393_testbench02 #(
parameter FULL_WIDTH= WOI_WIDTH+4; parameter FULL_WIDTH= WOI_WIDTH+4;
localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
// localparam FRAME_COMPRESS_CYCLES = (WOI_WIDTH &'h3fff0) * (WOI_HEIGHT &'h3fff0) * CYCLES_PER_PIXEL + FPGA_XTRA_CYCLES;
// in pixel clocks (camsync now has different clock - 100MHz instead of the 96MHz
// localparam TRIG_PERIOD = VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK); /// maximal sensor can do
localparam TRIG_PERIOD = 5000 ;
// ========================== end of parameters from x353 =================================== // ========================== end of parameters from x353 ===================================
...@@ -166,8 +181,8 @@ assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor ...@@ -166,8 +181,8 @@ assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
assign PX1_MCLK = sns1_dp[0]; // from FPGA to sensor assign PX1_MCLK = sns1_dp[0]; // from FPGA to sensor
assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK}; assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK};
assign PX1_ARST = sns1_dn[7]; assign PX1_ARST = sns1_dn[7];
assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI
assign sns1_scl = PX1_D[1]; // inout PX_SCL assign sns1_clkp = PX1_D[1]; // CNVCLK/TDO
assign PX1_ARO = sns1_ctl; // from FPGA to sensor assign PX1_ARO = sns1_ctl; // from FPGA to sensor
...@@ -460,7 +475,7 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -460,7 +475,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
`else `else
$display("ICARUS is not defined"); $display("ICARUS is not defined");
`endif `endif
$dumpfile(lxtname); $dumpfile(fstname);
// SuppressWarnings VEditor : assigned in $readmem() system task // SuppressWarnings VEditor : assigned in $readmem() system task
...@@ -764,6 +779,14 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -764,6 +779,14 @@ assign #10 gpio_pins[9] = gpio_pins[8];
`endif `endif
`ifdef TEST_SENSOR
TEST_TITLE = "TEST_SENSOR";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
0 ); // input [1:0] num_sensor;
`endif
`ifdef READBACK_DELAYS `ifdef READBACK_DELAYS
TEST_TITLE = "READBACK"; TEST_TITLE = "READBACK";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
...@@ -1763,49 +1786,123 @@ endfunction ...@@ -1763,49 +1786,123 @@ endfunction
// Sensor - related tasks and functions // Sensor - related tasks and functions
task setup_sensor_channel; task setup_sensor_channel;
input trigger_mode; // 0 - auto, 1 - triggered input [1:0] num_sensor;
input ext_trigger_mode; // 0 - internal, 1 - external trigger (camsync)
input external_timestamp; // embed local timestamp, 1 - embed received timestamp
input [31:0] camsync_period;
input [31:0] camsync_delay;
input [31:0] last_buf_frame;
input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
input [31:0] window_height; // 16 bit
input [31:0] window_left;
input [31:0] window_top;
reg trigger_mode; // 0 - auto, 1 - triggered
reg ext_trigger_mode; // 0 - internal, 1 - external trigger (camsync)
reg external_timestamp; // embed local timestamp, 1 - embed received timestamp
reg [31:0] camsync_period;
reg [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
reg [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
reg [31:0] window_height; // 16 bit
reg [31:0] window_left;
reg [31:0] window_top;
reg [31:0] last_buf_frame;
reg [31:0] camsync_delay;
reg [ 3:0] sensor_mask;
// Setting up a single sensor channel 0, sunchannel 0 // Setting up a single sensor channel 0, sunchannel 0
//
begin begin
program_curves( window_height = FULL_HEIGHT;
0, // input [1:0] num_sensor; window_left = 0;
0); // input [1:0] sub_channel; window_top = 0;
window_width = SENSOR_MEMORY_WIDTH_BURSTS;
frame_full_width = SENSOR_MEMORY_FULL_WIDTH_BURSTS;
camsync_period = TRIG_PERIOD;
camsync_delay = CAMSYNC_DELAY;
trigger_mode = TRIGGER_MODE;
ext_trigger_mode = EXT_TRIGGER_MODE;
external_timestamp = EXTERNAL_TIMESTAMP;
last_buf_frame = LAST_BUF_FRAME;
sensor_mask = 1 << num_sensor;
// program_curves(
// num_sensor, // input [1:0] num_sensor;
// 0); // input [1:0] sub_channel;
program_status_gpio (
3, // input [1:0] mode;
0); // input [5:0] seq_num;
program_status_sensor_i2c( program_status_sensor_i2c(
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mode; 3, // input [1:0] mode;
0); //input [5:0] seq_num; 0); //input [5:0] seq_num;
program_status_sensor_io( program_status_sensor_io(
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mode; 3, // input [1:0] mode;
0); //input [5:0] seq_num; 0); //input [5:0] seq_num;
program_status_rtc( // also takes snapshot program_status_rtc( // also takes snapshot
3, // input [1:0] mode; 3, // input [1:0] mode;
0); //input [5:0] seq_num; 0); //input [5:0] seq_num;
set_rtc ( set_rtc (
32'h12345678, // input [31:0] sec; 32'h12345678, // input [31:0] sec;
0, //input [19:0] usec; 0, //input [19:0] usec;
16'h8000); // input [15:0] corr; maximal correction to the rtc 16'h8000); // input [15:0] corr; maximal correction to the rtc
// moved beore camsync to have a valid timestamo w/o special waiting
TEST_TITLE = "MEMORY_SENSOR";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_memory (
num_sensor, // input [1:0] num_sensor;
FRAME_START_ADDRESS, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
FRAME_START_ADDRESS_INC, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top); // input [31:0] window_top;
TEST_TITLE = "CAMSYNC_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
// setup camsync module
set_camsync_period (0); // reset circuitry
set_gpio_ports (
0, // input [1:0] port_soft; // <2 - unchanged, 2 - disable, 3 - enable
3, // input [1:0] port_a; // camsync
0, // input [1:0] port_b; // motors on 353
0); //input [1:0] port_c; // logger
set_camsync_mode (
1'b1, // input en; // 1 - enable module, 0 - reset
{1'b1,1'b1}, // input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
{1'b1,external_timestamp}, // input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
{1'b1,trigger_mode}, // input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
{1'b1, 2'h0}, // input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel
{1'b1, sensor_mask}); // input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels
// setting I/Os after camsync is enabled
reset_camsync_inout (0); // reset input selection
if (ext_trigger_mode)
set_camsync_inout (0, 7, 1 ); // set input selection - ext[7], active high
reset_camsync_inout (1); // reset output selection
set_camsync_inout (1, 6, 1 ); // reset output selection - ext[6], active high
set_camsync_period (SYNC_BIT_LENGTH); ///set (bit_length -1) (should be 2..255)
set_camsync_delay (
0, // input [1:0] sub_chn;
camsync_delay); // input [31:0] dly; // 0 - input selection, 1 - output selection
set_camsync_period (camsync_period); // set period (start generating) - in 353 was after everything else was set
TEST_TITLE = "DELAYS_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_io_dly ( set_sensor_io_dly (
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
128'h33404850_58606870_78808890_98a0a8b0 ); //input [127:0] dly; // {mmsm_phase, bpf, vact, hact, pxd11,...,pxd0] 128'h33404850_58606870_78808890_98a0a8b0 ); //input [127:0] dly; // {mmsm_phase, bpf, vact, hact, pxd11,...,pxd0]
TEST_TITLE = "IO_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_io_width(
num_sensor, // input [1:0] num_sensor;
FULL_WIDTH); // Or use 0 for sensor-generated HACT input [15:0] width; // 0 - use HACT, >0 - generate HACT from start to specified width
set_sensor_io_ctl ( set_sensor_io_ctl (
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mrst; // <2: keep MRST, 2 - MRST low (active), 3 - high (inactive) 3, // input [1:0] mrst; // <2: keep MRST, 2 - MRST low (active), 3 - high (inactive)
3, // input [1:0] arst; // <2: keep ARST, 2 - ARST low (active), 3 - high (inactive) 3, // input [1:0] arst; // <2: keep ARST, 2 - ARST low (active), 3 - high (inactive)
3, // input [1:0] aro; // <2: keep ARO, 2 - set ARO (software controlled) low, 3 - set ARO (software controlled) high 3, // input [1:0] aro; // <2: keep ARO, 2 - set ARO (software controlled) low, 3 - set ARO (software controlled) high
...@@ -1814,7 +1911,7 @@ task setup_sensor_channel; ...@@ -1814,7 +1911,7 @@ task setup_sensor_channel;
0, // input set_delays; // (self-clearing) load all pre-programmed delays 0, // input set_delays; // (self-clearing) load all pre-programmed delays
1'b1, // input set_quadrants; // 0 - keep quadrants settings, 1 - update quadrants 1'b1, // input set_quadrants; // 0 - keep quadrants settings, 1 - update quadrants
6'h24); // data-0, hact - 1, vact - 2 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] 6'h24); // data-0, hact - 1, vact - 2 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
/*
// setup camsync module // setup camsync module
reset_camsync_inout (0); // reset input selection reset_camsync_inout (0); // reset input selection
if (ext_trigger_mode) if (ext_trigger_mode)
...@@ -1829,21 +1926,28 @@ task setup_sensor_channel; ...@@ -1829,21 +1926,28 @@ task setup_sensor_channel;
set_camsync_mode ( set_camsync_mode (
{1'b1,1'b1}, // input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse {1'b1,1'b1}, // input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
{1'b1,external_timestamp}, // input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp {1'b1,external_timestamp}, // input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
{1'b1,ext_trigger_mode}, // input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode {1'b1,trigger_mode}, // input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
{1'b1, 2'h0}, // input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel {1'b1, 2'h0}, // input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel
{1'b1, 4'h3}); // input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels {1'b1, sensor_mask}); // input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels
*/
TEST_TITLE = "I2C_TEST";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_i2c_353; // test soft/sequencer i2c test_i2c_353; // test soft/sequencer i2c
TEST_TITLE = "GAMMA_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_gamma_heights ( set_sensor_gamma_heights (
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
'hffff, // input [15:0] height0_m1; // height of the first sub-frame minus 1 'hffff, // input [15:0] height0_m1; // height of the first sub-frame minus 1
0, //input [15:0] height1_m1; // height of the second sub-frame minus 1 0, // input [15:0] height1_m1; // height of the second sub-frame minus 1
0); //input [15:0] height2_m1; // height of the third sub-frame minus 1 (no need for 4-th) 0); // input [15:0] height2_m1; // height of the third sub-frame minus 1 (no need for 4-th)
// Configure histograms // Configure histograms
TEST_TITLE = "HISTOGRAMS_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_histogram_window ( // 353 did it using command sequencer) set_sensor_histogram_window ( // 353 did it using command sequencer)
0, // input [1:0] num_sensor; // sensor channel number (0..3) num_sensor, // input [1:0] num_sensor; // sensor channel number (0..3)
0, // input [1:0] subchannel; // subchannel number (for multiplexed images) 0, // input [1:0] subchannel; // subchannel number (for multiplexed images)
HISTOGRAM_LEFT, // input [15:0] left; HISTOGRAM_LEFT, // input [15:0] left;
HISTOGRAM_TOP, // input [15:0] top; HISTOGRAM_TOP, // input [15:0] top;
...@@ -1851,8 +1955,8 @@ task setup_sensor_channel; ...@@ -1851,8 +1955,8 @@ task setup_sensor_channel;
HISTOGRAM_HEIGHT-2); // input [15:0] height_m1; // one less than window height. If 0 - use frame bottom margin (end of VACT) HISTOGRAM_HEIGHT-2); // input [15:0] height_m1; // one less than window height. If 0 - use frame bottom margin (end of VACT)
set_sensor_histogram_saxi_addr ( set_sensor_histogram_saxi_addr (
0, // input [1:0] num_sensor; // sensor channel number (0..3) num_sensor, // input [1:0] num_sensor; // sensor channel number (0..3)
0, // input [1:0] subchannel; // subchannel number (for multiplexed images) 0, // input [1:0] subchannel; // subchannel number (for multiplexed images)
HISTOGRAM_STRAT_PAGE); // input [19:0] page; //start address in 4KB pages (1 page - one subchannel histogram) HISTOGRAM_STRAT_PAGE); // input [19:0] page; //start address in 4KB pages (1 page - one subchannel histogram)
set_sensor_histogram_saxi ( set_sensor_histogram_saxi (
...@@ -1884,37 +1988,34 @@ task write_cmd_frame_sequencer; ...@@ -1884,37 +1988,34 @@ task write_cmd_frame_sequencer;
input [31:0] data; // command data input [31:0] data; // command data
*/ */
set_sensor_io_width( // Run after histogram channel is set up?
0, // input [1:0] num_sensor; TEST_TITLE = "SENSOR_SETUP";
FULL_WIDTH); // Or use 0 for sensor-generated HACT input [15:0] width; // 0 - use HACT, >0 - generate HACT from start to specified width $display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_memory (
0, // input [1:0] num_sensor;
FRAME_START_ADDRESS, // input [31:0] frame_sa; // 22-bit frame start address ((3 CA LSBs==0. BA==0)
FRAME_START_ADDRESS_INC, // input [31:0] frame_sa_inc; // 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
last_buf_frame, // input [31:0] last_frame_num; // 16-bit number of the last frame in a buffer
frame_full_width, // input [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left;
window_top); // input [31:0] window_top;
// Run after histogram channel is set up?
set_sensor_mode ( set_sensor_mode (
0, // input [1:0] num_sensor; num_sensor, // input [1:0] num_sensor;
4'h1, // input [3:0] hist_en; // [0..3] 1 - enable histogram modules, disable after processing the started frame 4'h1, // input [3:0] hist_en; // [0..3] 1 - enable histogram modules, disable after processing the started frame
4'h1, // input [3:0] hist_nrst; // [4..7] 0 - immediately reset histogram module 4'h1, // input [3:0] hist_nrst; // [4..7] 0 - immediately reset histogram module
1'b1, // input chn_en; // [8] 1 - enable sensor channel (0 - reset) 1'b1, // input chn_en; // [8] 1 - enable sensor channel (0 - reset)
1'b0); // input bits16; // [9] 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms 1'b0); // input bits16; // [9] 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
// test i2c - manual and sequencer (same data as in 353 test fixture // test i2c - manual and sequencer (same data as in 353 test fixture
TEST_TITLE = "GAMMA_CTL";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up
0, // input [1:0] num_sensor; // sensor channel number (0..3) num_sensor, // input [1:0] num_sensor; // sensor channel number (0..3)
2'h3, // input [1:0] bayer; // bayer shift (0..3) 2'h3, // input [1:0] bayer; // bayer shift (0..3)
0, // input table_page; // table page (only used if SENS_GAMMA_BUFFER) 0, // input table_page; // table page (only used if SENS_GAMMA_BUFFER)
1'b1, // input en_input; // enable channel input 1'b1, // input en_input; // enable channel input
1'b1, // input repet_mode; // Normal mode, single trigger - just for debugging 1'b1, // input repet_mode; // Normal mode, single trigger - just for debugging
1'b0); // input trig; // pass next frame 1'b0); // input trig; // pass next frame
// temporarily putting in the very end as it takes about 30 usec to program curves (TODO: see how to make it faster for simulation)
TEST_TITLE = "GAMMA_LOAD";
$display("===================== TEST_%s =========================",TEST_TITLE);
program_curves(
num_sensor, // input [1:0] num_sensor;
0); // input [1:0] sub_channel;
end end
endtask endtask
...@@ -2035,6 +2136,62 @@ task program_status_sensor_io; ...@@ -2035,6 +2136,62 @@ task program_status_sensor_io;
end end
endtask endtask
task program_status_gpio;
input [1:0] mode;
input [5:0] seq_num;
begin
program_status (GPIO_ADDR,
GPIO_SET_STATUS,
mode,
seq_num);
end
endtask
task set_gpio_ports;
input [1:0] port_soft; // <2 - unchanged, 2 - disable, 3 - enable
input [1:0] port_a; // camsync
input [1:0] port_b; // motors on 353
input [1:0] port_c; // logger
reg [31:0] data;
begin
data = 0;
data [GPIO_PORTEN + 0 +:2] = port_soft;
data [GPIO_PORTEN + 2 +:2] = port_a;
data [GPIO_PORTEN + 4 +:2] = port_b;
data [GPIO_PORTEN + 6 +:2] = port_c;
write_contol_register( GPIO_ADDR + GPIO_SET_PINS, data);
end
endtask
task set_gpio_pins;
input [1:0] ext0; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext1; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext2; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext3; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext4; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext5; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext6; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext7; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext8; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
input [1:0] ext9; // 0 - nop, 1 - set "0", 2 - set "1", 3 - set as input
reg [31:0] data;
begin
data = 0;
data [ 0 +:2] = ext0;
data [ 2 +:2] = ext1;
data [ 4 +:2] = ext2;
data [ 6 +:2] = ext3;
data [ 8 +:2] = ext4;
data [10 +:2] = ext5;
data [12 +:2] = ext6;
data [14 +:2] = ext7;
data [16 +:2] = ext8;
data [18 +:2] = ext9;
write_contol_register( GPIO_ADDR + GPIO_SET_PINS, data);
end
endtask
task set_sensor_mode; task set_sensor_mode;
input [1:0] num_sensor; input [1:0] num_sensor;
...@@ -2181,7 +2338,7 @@ task program_curves; ...@@ -2181,7 +2338,7 @@ task program_curves;
// reg [10:0] curv_diff; // reg [10:0] curv_diff;
reg [17:0] data18; reg [17:0] data18;
begin begin
$readmemh("linear1028rgb.dat",curves_data); $readmemh("input_data/linear1028rgb.dat",curves_data);
set_sensor_gamma_table_addr ( set_sensor_gamma_table_addr (
num_sensor, num_sensor,
sub_channel, sub_channel,
...@@ -2369,6 +2526,7 @@ task set_rtc; ...@@ -2369,6 +2526,7 @@ task set_rtc;
end end
endtask endtask
/*
function [STATUS_DEPTH-1:0] func_status_addr_rtc_status; function [STATUS_DEPTH-1:0] func_status_addr_rtc_status;
begin begin
func_status_addr_rtc_status = RTC_STATUS_REG_ADDR; func_status_addr_rtc_status = RTC_STATUS_REG_ADDR;
...@@ -2380,9 +2538,10 @@ function [STATUS_DEPTH-1:0] func_status_addr_rtc_usec; // sec is in the next add ...@@ -2380,9 +2538,10 @@ function [STATUS_DEPTH-1:0] func_status_addr_rtc_usec; // sec is in the next add
func_status_addr_rtc_usec = RTC_SEC_USEC_ADDR; func_status_addr_rtc_usec = RTC_SEC_USEC_ADDR;
end end
endfunction endfunction
*/
// camsync tasks // camsync tasks
task set_camsync_mode; task set_camsync_mode;
input en; // 1 - enable, 0 - reset module
input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode
...@@ -2391,6 +2550,7 @@ task set_camsync_mode; ...@@ -2391,6 +2550,7 @@ task set_camsync_mode;
reg [31:0] data; reg [31:0] data;
begin begin
data = 0; data = 0;
data [CAMSYNC_EN_BIT] = en;
data [CAMSYNC_SNDEN_BIT -: 2] = en_snd; data [CAMSYNC_SNDEN_BIT -: 2] = en_snd;
data [CAMSYNC_EXTERNAL_BIT -: 2] = en_ts_external; data [CAMSYNC_EXTERNAL_BIT -: 2] = en_ts_external;
data [CAMSYNC_TRIGGERED_BIT -: 2] = triggered_mode; data [CAMSYNC_TRIGGERED_BIT -: 2] = triggered_mode;
......
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