debugging, more corrections, tested write levelling/buffer reading

ddrc_test01_testbench.tf

@@ -988,7 +988,9 @@ simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
     .ready(bready)  //output        ready
     );
 
-simul_axi_read simul_axi_read_i(
+simul_axi_read #(
+    .ADDRESS_WIDTH(10)
+ ) simul_axi_read_i(
   .clk(CLK),
   .reset(RST),
   .last(rlast),

includes/x393_simulation_parameters.vh

@@ -22,5 +22,7 @@
     parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
     parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
     parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
-    parameter integer AXI_TASK_HOLD=1.0
+    parameter integer AXI_TASK_HOLD=1.0,
     
+    parameter [1:0] DEFAULT_STATUS_MODE=3,
+    parameter       SIMUL_AXI_READ_WIDTH=16
\ No newline at end of file

includes/x393_tasks01.vh

@@ -207,6 +207,7 @@
             ARBURST_IN_r <= 2'hz;
             AR_SET_CMD_r <= 1'b0;
             LAST_ARID <= id;
+            NUM_WORDS_EXPECTED <= NUM_WORDS_EXPECTED+len+1;
         end
     endtask
 

memctrl/mcntrl_1kx32r.v

@@ -44,7 +44,7 @@ module  mcntrl_1kx32r(
         if      (wpage_set) page_r <= wpage_in;
         else if (page_next) page_r <= page_r+1;
 
-        if      (page_next) waddr <= 0;
+        if      (page_next || wpage_set) waddr <= 0;
         else if (we)                     waddr <= waddr+1;
     end
     ram_512x64w_1kx32r #(

memctrl/mcntrl_1kx32w.v

@@ -46,7 +46,7 @@ module  mcntrl_1kx32w(
         if      (rpage_set) page_r <= rpage_in;
         else if (page_next) page_r <= page_r+1;
 
-        if      (page_next) raddr <= 0;
+        if      (page_next || rpage_set) raddr <= 0;
         else if (rd)                     raddr <= raddr+1;
     end
     ram_1kx32w_512x64r #(

memctrl/mcntrl_ps_pio.v

@@ -161,12 +161,9 @@ module  mcntrl_ps_pio#(
         else              cmd_set_d <= {cmd_set_d[0],cmd_set};
     end
     
-    always @ (posedge rst or negedge mclk) begin
-        if (rst)          page_neg <= 0;
-        else if (cmd_set) page_neg <= page;
-        
-        if (rst)          cmd_set_d_neg <= 0;
-        else              cmd_set_d_neg <= cmd_set_d[1];
+    always @ (negedge mclk) begin
+        page_neg <= page;
+        cmd_set_d_neg <= cmd_set_d[1];
     end 
     
     cmd_deser #(

simulation_modules/simul_axi_read.v

@@ -20,32 +20,30 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 
-module  simul_axi_read(
+module  simul_axi_read #(
+    parameter ADDRESS_WIDTH=10
+    )(
   input                     clk,
   input                     reset,
   input                     last,      // last data word in burst
   input                     data_stb,  // data strobe (RVALID & RREADY) genearted externally
-  input  [ 9:0] raddr,     // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd 
+  input  [ADDRESS_WIDTH-1:0] raddr,     // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd 
   input              [ 3:0] rlen,      // burst length  as written by axi master, valid at rcmd
   input                     rcmd,      // read command (address+length) strobe
-  output [ 9:0] addr_out,  // output address
+  output [ADDRESS_WIDTH-1:0] addr_out,  // output address
   output                    burst,     // burst in progress
   output reg                err_out);  // data last does not match predicted or FIFO over/under run
 
-  wire   [ 9:0] raddr_fifo; // raddr after fifo
+  wire   [ADDRESS_WIDTH-1:0] raddr_fifo; // raddr after fifo
   wire               [ 3:0] rlen_fifo;  // rlen after fifo
   wire                      fifo_valid; // fifo out valid
-//  wire          fifo_re;    // fifo read strobe
   reg                       burst_r=0;
   reg                [ 3:0] left_plus_1;
-//  wire          start_burst=fifo_valid && (!burst_r || (last && data_stb));
-//  wire          start_burst=fifo_valid && data_stb && (!burst_r || last );
   wire                      start_burst=fifo_valid && data_stb && !burst_r;
   wire                      generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
   wire                      fifo_in_rdy;
   wire                      error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
-  reg    [ 9:0] adr_out_r;
-//  reg           was_last;
+  reg    [ADDRESS_WIDTH-1:0] adr_out_r;
 
   assign  burst=burst_r || start_burst;
   assign  addr_out=start_burst?raddr_fifo:adr_out_r;
@@ -70,7 +68,7 @@ module  simul_axi_read(
   end
 simul_fifo
 #(
-  .WIDTH(14),
+  .WIDTH(ADDRESS_WIDTH+4),
   .DEPTH(64)
 )simmul_fifo_i(
      .clk(clk),