Commit bb237119 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

debugging, more corrections, tested write levelling/buffer reading

parent d899569e

ddrc_test01_testbench.tf

+3 −1
Original line number Diff line number Diff line
@@ -988,7 +988,9 @@ simul_axi_slow_ready simul_axi_slow_ready_write_resp_i( 
    .ready(bready)  //output        ready

    );



simul_axi_read simul_axi_read_i(

simul_axi_read #(

    .ADDRESS_WIDTH(10)

 ) simul_axi_read_i(

  .clk(CLK),

  .reset(RST),

  .last(rlast),

includes/x393_simulation_parameters.vh

+4 −2
Original line number Diff line number Diff line
@@ -22,5 +22,7 @@ 
    parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,

    parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,

    parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1

    parameter integer AXI_TASK_HOLD=1.0

    parameter integer AXI_TASK_HOLD=1.0,

    

    parameter [1:0] DEFAULT_STATUS_MODE=3,

    parameter       SIMUL_AXI_READ_WIDTH=16
 
 No newline at end of file

includes/x393_tasks01.vh

+1 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ 
            ARBURST_IN_r <= 2'hz;

            AR_SET_CMD_r <= 1'b0;

            LAST_ARID <= id;

            NUM_WORDS_EXPECTED <= NUM_WORDS_EXPECTED+len+1;

        end

    endtask

memctrl/mcntrl_1kx32r.v

+2 −2
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ module mcntrl_1kx32r( 
        if      (wpage_set) page_r <= wpage_in;

        else if (page_next) page_r <= page_r+1;



        if      (page_next) waddr <= 0;

        if      (page_next || wpage_set) waddr <= 0;

        else if (we)                     waddr <= waddr+1;

    end

    ram_512x64w_1kx32r #(

memctrl/mcntrl_1kx32w.v

+2 −2
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ module mcntrl_1kx32w( 
        if      (rpage_set) page_r <= rpage_in;

        else if (page_next) page_r <= page_r+1;



        if      (page_next) raddr <= 0;

        if      (page_next || rpage_set) raddr <= 0;

        else if (rd)                     raddr <= raddr+1;

    end

    ram_1kx32w_512x64r #(