Commit b298c320 authored by Andrey Filippov's avatar Andrey Filippov

Merge branch 'lwir' of git.elphel.com:Elphel/x393 into lwir

parents 1c50ea54 fbbfd00c
......@@ -2231,7 +2231,32 @@ input mem mtd4 ram1
break
def mt9f002_read_regs(self,num_sensor):
"""
"""
reglist = [
0x3000,0x3002,0x3004,0x3006,0x3008,0x300a,0x300c,0x3010,
0x3012,0x3014,0x3016,0x3018,0x301a,0x301c,0x301d,0x301e,
0x3021,0x3022,0x3023,0x3024,0x3026,0x3028,0x302a,0x302c,
0x302e,0x3030,0x3032,0x3034,0x3036,0x3038,0x303a,0x303b,
0x303c,0x3040,0x3046,0x3048,0x3056,0x3058,0x305a,0x305c,
0x305e,0x306a,0x306e,0x3070,0x3072,0x3074,0x3078,0x307a,
0x30a0,0x30a2,0x30a4,0x30a6,0x30a8,0x30aa,0x30ac,0x30ae,
0x30bc,0x30c0,0x30c2,0x30c4,0x30c6,0x30c8,0x30e8,0x30ea,
0x30ec,0x30ee,0x3138,0x3140,0x3158,0x315a,0x315e,0x3160,
0x3162,0x3164,0x3166,0x3168,0x316a,0x3178,0x31a0,0x31a2,
0x31a2,0x31a4,0x31a6,0x31a8,0x31aa,0x31ac,0x31ae,0x31b0,
0x31b2,0x31b4,0x31b6,0x31b8,0x31ba,0x31bc,0x31c0,0x31c6
]
i=0
for reg in reglist:
val = int(self.print_sensor_i2c(num_sensor,reg,0xff,0x10,0))&0xffff
print("{:04x}".format(reg)+": "+"{:04x}".format(val),end=' ')
i += 1
if i%8==0:
print("")
......
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