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x393
Commit b0a25b6a authored by Andrey Filippov's avatar Andrey Filippov
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0x03930138 - trigger output from LWIR

parent 8f05c2c2
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Showing with 1258 additions and 1155 deletions
cocotb/x393_cocotb_lwir_04.sav
View file @ b0a25b6a
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Fri May 3 15:28:46 2019
[*] Tue May 7 14:26:47 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
[dumpfile_mtime] "Fri May 3 04:06:09 2019"
[dumpfile_size] 19575412
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190506234557532.fst"
[dumpfile_mtime] "Tue May 7 10:20:44 2019"
[dumpfile_size] 1378118334
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
[timestart] 0
[timestart] 902240000
[size] 1804 1171
[pos] -1 -1
*-25.245840 49300000 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-21.528950 908793333 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_lwir160x120_vospi1_i.
[treeopen] x393_dut.x393_i.
......@@ -90,8 +90,8 @@
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[treeopen] x393_dut.x393_i.timing393_i.rtc393_i.
[sst_width] 402
[signals_width] 335
[sst_width] 314
[signals_width] 265
[sst_expanded] 1
[sst_vpaned_height] 459
@820
......@@ -3032,10 +3032,6 @@ x393_dut.sns1_sda
@28
x393_dut.x393_i.timing393_i.rtc393_i.enable_rtc
x393_dut.x393_i.timing393_i.rtc393_i.mclk
x393_dut.x393_i.timing393_i.rtc393_i.khz
@22
x393_dut.x393_i.timing393_i.rtc393_i.khz_cntr[9:0]
@28
(0)x393_dut.x393_i.timing393_i.rtc393_i.inc_usec[1:0]
@1000200
-rtc393
......@@ -3044,25 +3040,6 @@ x393_dut.x393_i.timing393_i.rtc393_i.khz_cntr[9:0]
-reset_seq
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.set_ctrl_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.ms
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_pclk
@800022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@1001200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_on_cntr
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_after_cntr[2:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
@1000200
-reset_seq
@800200
......@@ -3094,11 +3071,144 @@ x393_dut.x393_i.timing393_i.ts_stb_chn0
x393_dut.x393_i.timing393_i.ts_stb_chn1
x393_dut.x393_i.timing393_i.ts_stb_chn2
x393_dut.x393_i.timing393_i.ts_stb_chn3
@201
-
@22
x393_dut.x393_i.sof_out_mclk[3:0]
x393_dut.x393_i.sof_late_mclk[3:0]
x393_dut.x393_i.sof_out_pclk[3:0]
@1000200
-timestamping
@800200
-timing393
@200
-
@1000200
-timing393
@28
x393_dut.x393_i.timing393_i.ts_master_snap
x393_dut.x393_i.timing393_i.ts_master_stb
@800200
-camsync
@28
x393_dut.x393_i.timing393_i.camsync393_i.mrst
x393_dut.x393_i.timing393_i.camsync393_i.triggered_mode
@c00022
x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
@28
(0)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
(1)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
(2)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
(3)x393_dut.x393_i.timing393_i.camsync393_i.frame_sync[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.timing393_i.camsync393_i.en
x393_dut.x393_i.timing393_i.camsync393_i.ts_external_m
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_en
@22
x393_dut.x393_i.timing393_i.camsync393_i.chn_en[3:0]
x393_dut.x393_i.timing393_i.camsync393_i.gpio_active[9:0]
x393_dut.x393_i.timing393_i.camsync393_i.gpio_out_en[9:0]
x393_dut.x393_i.timing393_i.camsync393_i.gpio_out[9:0]
@200
-
@28
x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn0
x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn1
x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn2
x393_dut.x393_i.timing393_i.camsync393_i.ts_snap_mclk_chn3
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn0
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn1
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn2
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_stb_chn3
@22
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_data_chn0[7:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_data_chn1[7:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_data_chn2[7:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_data_chn3[7:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn0[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn1[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn2[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec_chn3[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_usec_chn0[19:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_usec_chn1[19:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_usec_chn2[19:0]
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_usec_chn3[19:0]
@200
-
@28
x393_dut.x393_i.timing393_i.camsync393_i.suppress_immediate
x393_dut.x393_i.timing393_i.camsync393_i.start_pclk[2:0]
x393_dut.x393_i.timing393_i.camsync393_i.start_pclk2_masked
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_en_pclk
x393_dut.x393_i.timing393_i.camsync393_i.ts_master_snap_pclk
x393_dut.x393_i.timing393_i.camsync393_i.ts_master_snap
x393_dut.x393_i.timing393_i.camsync393_i.ts_master_stb
@22
x393_dut.x393_i.timing393_i.camsync393_i.ts_snd_sec[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.sr_snd_first[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.sr_snd_second[31:0]
@28
[color] 3
x393_dut.x393_i.timing393_i.camsync393_i.out_data
x393_dut.x393_i.timing393_i.camsync393_i.outsync
x393_dut.x393_i.timing393_i.camsync393_i.start_en
x393_dut.x393_i.timing393_i.camsync393_i.start_out_pulse
x393_dut.x393_i.timing393_i.camsync393_i.input_use_intern
x393_dut.x393_i.timing393_i.camsync393_i.master_chn[1:0]
@800022
x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
@28
(0)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
(1)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
(2)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
(3)x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_end[3:0]
@1001200
-group_end
@22
x393_dut.x393_i.timing393_i.camsync393_i.repeat_period[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.bit_length[7:0]
x393_dut.x393_i.timing393_i.camsync393_i.input_dly_chn0[31:0]
x393_dut.x393_i.timing393_i.camsync393_i.dly_cntr_chn0[31:0]
@28
x393_dut.x393_i.timing393_i.camsync393_i.set_trig_period_w
x393_dut.x393_i.timing393_i.camsync393_i.set_trig_delay0_w
x393_dut.x393_i.timing393_i.camsync393_i.cmd_we
x393_dut.x393_i.timing393_i.camsync393_i.set_mode_reg_w
x393_dut.x393_i.timing393_i.camsync393_i.set_period
x393_dut.x393_i.timing393_i.camsync393_i.set_trig_dst_w
x393_dut.x393_i.timing393_i.camsync393_i.set_trig_src_w
@22
x393_dut.x393_i.timing393_i.camsync393_i.bit_length[7:0]
@c08022
x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
@28
(0)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(1)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(2)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(3)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(4)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(5)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(6)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
(7)x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_duration[7:0]
@1401200
-group_end
@8022
x393_dut.x393_i.timing393_i.camsync393_i.bit_snd_counter[5:0]
@28
x393_dut.x393_i.timing393_i.camsync393_i.pre_start_out_pulse
x393_dut.x393_i.timing393_i.camsync393_i.start_out_pulse
@200
-
@28
(3)x393_dut.gpio_pins[9:0]
(5)x393_dut.gpio_pins[9:0]
(3)x393_dut.x393_i.gpio_camsync[9:0]
(5)x393_dut.x393_i.gpio_camsync[9:0]
(3)x393_dut.x393_i.gpio_camsync_en[9:0]
(5)x393_dut.x393_i.gpio_camsync_en[9:0]
@1000200
-camsync
@800200
-lepto3_0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.prst
......
cocotb/x393_dut.v
View file @ b0a25b6a
......@@ -2197,7 +2197,7 @@ assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
`define TEST_IMU
`define TEST_EXT_INT
`define ODOMETER_PULSE_6
//`define ODOMETER_PULSE_6 // conflicts with trigger output
assign #10 gpio_pins[7] = gpio_pins[8];
`ifndef TEST_IMU
assign #10 gpio_pins[9] = gpio_pins[6];
......
fpga_version.vh
View file @ b0a25b6a
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
......
py393/x393_camsync.py
View file @ b0a25b6a
......@@ -183,9 +183,11 @@ class X393Camsync(object):
self.set_camsync_period (SYNC_BIT_LENGTH) #set (bit_length -1) (should be 2..255), not the period
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
print ("camsync_delay=",camsync_delay)
for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly)
print ("set_camsync_delay(",i, dly,")")
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
simulation_modules/simul_lwir160x120_vospi.v
View file @ b0a25b6a
......@@ -48,7 +48,7 @@ module simul_lwir160x120_vospi # (
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz
parameter SEGMENTS_SEQ = 8, // 12 With ITAR
parameter SEGMENT_START = 7, // 0,
parameter SEGMENT_START = 0, // 7, // 0,
parameter FRAME_DELAY = 100, // mclk period to start first frame 1
parameter MS_PERIOD = 25 // ahould actually be 25000
......
timing/camsync393.v
View file @ b0a25b6a
......@@ -380,6 +380,15 @@ module camsync393 #(
wire [3:0] frsync_pclk; // time to copy timestamps from master/received to channels (will always be after it is available)
wire [3:0] dly_cntr_start; // start delay counters (added non-triggered mode option)
// in triggered mode uses ts_master_stb, ts_master_data inputs (as was before), in free runnig - timestyamps from the master channel
wire ts_master_stb_with_free; // 1 clk before ts_snd_data is valid
wire [7:0] ts_master_data_with_free; // byte-wide serialized timestamp message
assign {ts_master_stb_with_free, ts_master_data_with_free} = triggered_mode_r?
{ts_master_stb, ts_master_data}:
(master_chn[1]?(master_chn[0]?{ts_snd_stb_chn3, ts_snd_data_chn3}:{ts_snd_stb_chn2, ts_snd_data_chn2}):
(master_chn[0]?{ts_snd_stb_chn1, ts_snd_data_chn1}:{ts_snd_stb_chn0, ts_snd_data_chn0}));
assign dly_cntr_start = triggered_mode_pclk? {4{start_dly}} : frsync_pclk; // each delay counter will be started in free running mode
assign dly_cntr_non_zero = {(dly_cntr_chn3[31:0]!=0)?1'b1:1'b0,
(dly_cntr_chn2[31:0]!=0)?1'b1:1'b0,
......@@ -449,12 +458,21 @@ module camsync393 #(
wire [9:0] gpio_active_w = ((gpio_active ^ pre_gpio_active) & output_mask) ^ gpio_active;
always @(posedge mclk) begin
if (set_mode_reg_w) begin
if (mrst) begin
en <= 0;
triggered_mode_r <= 0;
master_chn <= 0;
ts_snd_en <= 0;
end else if (set_mode_reg_w) begin
if (cmd_data[CAMSYNC_EN_BIT]) en <= cmd_data[CAMSYNC_EN_BIT - 1];
if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1];
if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external_m <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
if (cmd_data[CAMSYNC_TRIGGERED_BIT]) triggered_mode_r <= cmd_data[CAMSYNC_TRIGGERED_BIT - 1];
if (cmd_data[CAMSYNC_MASTER_BIT]) master_chn <= cmd_data[CAMSYNC_MASTER_BIT - 1 -: 2];
if (cmd_data[CAMSYNC_SNDEN_BIT]) ts_snd_en <= cmd_data[CAMSYNC_SNDEN_BIT - 1];
end
if (set_mode_reg_w) begin
if (cmd_data[CAMSYNC_EXTERNAL_BIT]) ts_external_m <= cmd_data[CAMSYNC_EXTERNAL_BIT - 1];
// Making separate enables for each channel, so channel software will not disturb other channels
if (cmd_data[CAMSYNC_CHN_EN_BIT-3]) chn_en_r[0] <= cmd_data[CAMSYNC_CHN_EN_BIT - 7];
if (cmd_data[CAMSYNC_CHN_EN_BIT-2]) chn_en_r[1] <= cmd_data[CAMSYNC_CHN_EN_BIT - 6];
......@@ -549,7 +567,8 @@ module camsync393 #(
ts_master_snap_pclk <= ts_snd_en_pclk? start_pclk2_masked: rcv_done;
ts_snd_en_pclk<=ts_snd_en;
input_use_intern <= pre_input_use_intern;
// input_use_intern <= pre_input_use_intern;
input_use_intern <= pre_input_use_intern || !triggered_mode_pclk;
ts_external_pclk<= ts_external; // && !input_use_intern;
start_pclk[2:0] <= {(restart && rep_en_pclk) ||
......@@ -576,7 +595,8 @@ module camsync393 #(
start_out_pulse <= pre_start_out_pulse;
/// Generating output pulse - 64* bit_length if timestamp is disabled or
/// 64 bits with encoded timestamp, including pre/post magic for error detectrion
outsync <= start_en && (start_out_pulse || (outsync && !((bit_snd_duration[7:0]==0) &&(bit_snd_counter[5:0]==0))));
// outsync <= start_en && (start_out_pulse || (outsync && !((bit_snd_duration[7:0]==0) &&(bit_snd_counter[5:0]==0))));
outsync <= !pre_start_out_pulse && (start_en || (en & !triggered_mode_pclk)) && (start_out_pulse || (outsync && !((bit_snd_duration[7:0]==0) &&(bit_snd_counter[5:0]==0))));
if (!outsync || (bit_snd_duration[7:0]==0)) bit_snd_duration[7:0] <= bit_length[7:0];
else bit_snd_duration[7:0] <= bit_snd_duration[7:0] - 1;
......@@ -834,8 +854,8 @@ module camsync393 #(
timestamp_to_parallel timestamp_to_parallel_master_i (
.clk (mclk), // input
.pre_stb (ts_master_stb), // input
.tdata (ts_master_data), // input[7:0]
.pre_stb (ts_master_stb_with_free), // input
.tdata (ts_master_data_with_free), // input[7:0]
.sec (ts_snd_sec), // output[31:0] reg
.usec (ts_snd_usec), // output[19:0] reg
.done (master_got) // output
......
x393_vospi.bit
View file @ b0a25b6a
No preview for this file type
x393_vospi.timing_summary_impl
View file @ b0a25b6a
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_vospi_utilization.report
View file @ b0a25b6a
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Fri May 3 14:00:41 2019
| Date : Mon May 6 22:52:43 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42462 | 0 | 78600 | 54.02 |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| Slice LUTs | 42162 | 0 | 78600 | 53.64 |
| LUT as Logic | 38807 | 0 | 78600 | 49.37 |
| LUT as Memory | 3355 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 552 | 0 | | |
| Slice Registers | 54238 | 0 | 157200 | 34.50 |
| Register as Flip Flop | 54238 | 0 | 157200 | 34.50 |
| LUT as Shift Register | 553 | 0 | | |
| Slice Registers | 54240 | 0 | 157200 | 34.50 |
| Register as Flip Flop | 54240 | 0 | 157200 | 34.50 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 8 | Yes | - | Set |
| 680 | Yes | - | Reset |
| 1108 | Yes | Set | - |
| 52442 | Yes | Reset | - |
| 1109 | Yes | Set | - |
| 52443 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16910 | 0 | 19650 | 86.06 |
| SLICEL | 11158 | 0 | | |
| SLICEM | 5752 | 0 | | |
| LUT as Logic | 39108 | 0 | 78600 | 49.76 |
| using O5 output only | 6 | | | |
| using O6 output only | 30466 | | | |
| using O5 and O6 | 8636 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| Slice | 16575 | 0 | 19650 | 84.35 |
| SLICEL | 10941 | 0 | | |
| SLICEM | 5634 | 0 | | |
| LUT as Logic | 38807 | 0 | 78600 | 49.37 |
| using O5 output only | 3 | | | |
| using O6 output only | 30134 | | | |
| using O5 and O6 | 8670 | | | |
| LUT as Memory | 3355 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 552 | 0 | | |
| using O5 output only | 272 | | | |
| using O6 output only | 228 | | | |
| using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24526 | 0 | 78600 | 31.20 |
| fully used LUT-FF pairs | 4532 | | | |
| LUT-FF pairs with one unused LUT output | 17794 | | | |
| LUT-FF pairs with one unused Flip Flop | 17697 | | | |
| Unique Control Sets | 4907 | | | |
| LUT as Shift Register | 553 | 0 | | |
| using O5 output only | 275 | | | |
| using O6 output only | 227 | | | |
| using O5 and O6 | 51 | | | |
| LUT Flip Flop Pairs | 24469 | 0 | 78600 | 31.13 |
| fully used LUT-FF pairs | 4529 | | | |
| LUT-FF pairs with one unused LUT output | 17760 | | | |
| LUT-FF pairs with one unused Flip Flop | 17622 | | | |
| Unique Control Sets | 4810 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -196,17 +196,17 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52442 | Flop & Latch |
| LUT3 | 11375 | LUT |
| LUT6 | 10433 | LUT |
| LUT2 | 8421 | LUT |
| LUT4 | 8002 | LUT |
| LUT5 | 7906 | LUT |
| FDRE | 52443 | Flop & Latch |
| LUT3 | 11395 | LUT |
| LUT6 | 10215 | LUT |
| LUT2 | 8461 | LUT |
| LUT4 | 7997 | LUT |
| LUT5 | 7805 | LUT |
| RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2733 | CarryLogic |
| LUT1 | 1607 | LUT |
| LUT1 | 1604 | LUT |
| RAMS32 | 1392 | Distributed Memory |
| FDSE | 1108 | Flop & Latch |
| FDSE | 1109 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 496 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory |
......
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