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Commit aeb5b749 authored by Andrey Filippov's avatar Andrey Filippov
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Simulating/debugging raw mode

parent bf8f63c5
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cocotb/x393_cocotb_03.sav
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compressor_jp/bit_stuffer_raw_metadata.v
View file @ aeb5b749
......@@ -62,6 +62,7 @@ module bit_stuffer_raw_metadata(
input abort, // @ any, extracts 0->1 and flushes (for both modes!)
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
......@@ -123,12 +124,14 @@ module bit_stuffer_raw_metadata(
wire meta_last = (imgsz4[2:0] == 7) && meta_out;
// re-clock enable to this clock
wire ts_rstb= raw_mode ? raw_ts_copy: (last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
// wire ts_rstb= raw_mode ? raw_ts_copy: (last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire ts_rstb= (raw_mode && raw_ts_copy) || ( compressed_mode && last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4); // TODO: never in raw mode?
wire stb_start = raw_mode? raw_start: (!color_first && color_first_r) ;
wire stb = in_stb & !trailer && !force_flush;
wire stb1 = raw_stb & !trailer && !force_flush;
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4) || raw_flush; // TODO: never in raw mode?
// wire stb_start = raw_mode? raw_start: (!color_first && color_first_r) ;
wire stb_start = (raw_mode && raw_start) || (compressed_mode && !color_first && color_first_r) ;
wire stb = compressed_mode && in_stb && !trailer && !force_flush;
wire stb1 = raw_mode && raw_stb && !trailer && !force_flush;
always @ (posedge xclk) begin
if (xrst ||trailer_done) imgsz4 <= 0;
......@@ -148,9 +151,10 @@ module bit_stuffer_raw_metadata(
if ((!ts_in[3] && (ts_in[1:0] == 2)) || write_size) time_ram2[ts_in[3:2]] <= ts_in[3]? (imgsz4[21:14]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 3)) || write_size) time_ram3[ts_in[3:2]] <= ts_in[3]? (8'hff):ts_dout;
if (xrst) trailer <= 0;
else if (force_flush || (raw_mode ? raw_flush : flush)) trailer <= 1;
else if (trailer_done) trailer <= 0;
if (xrst) trailer <= 0;
// else if (force_flush || (raw_mode ? raw_flush : flush)) trailer <= 1;
else if (force_flush || (raw_mode && raw_flush) || (compressed_mode && flush)) trailer <= 1;
else if (trailer_done) trailer <= 0;
if (xrst) meta_out <= 0;
else if (trailer && (imgsz4[2:0] == 4) &&!zeros_out) meta_out <= 1;
......@@ -167,7 +171,9 @@ module bit_stuffer_raw_metadata(
data_out_valid <= stb1 || stb || trailer;
if (xrst || trailer) running <= 0;
/// if (xrst || trailer) running <= 0; // FIXME: Was this for quite a while? Was in intentional?
if (xrst || trailer_done) running <= 0;
else if (stb_start) running <= 1; // for raw need color_first trailing edge
done <= trailer_done;
......
compressor_jp/cmprs_cmd_decode.v
View file @ aeb5b749
......@@ -189,6 +189,7 @@ module cmprs_cmd_decode#(
// outputs sync @ posedge mclk:
output cmprs_en_mclk, // @mclk 0 resets immediately
input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
input compressor_running, // @xclk - reading frame or running stuffer/trailer
output reg cmprs_run_mclk, // @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
output reg cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
......@@ -221,7 +222,8 @@ module cmprs_cmd_decode#(
output reg [CMPRS_CSAT_CR_BITS-1:0] color_sat_cr, // scale for Cr color component (color saturation)
output reg [CMPRS_CORING_BITS-1:0] coring, // scale for Cb color component (color saturation)
output reg uncompressed,
output reg compressed, // late on, early off running compressor chain
output reg uncompressed, // late on, early off running raw chain
output reg be16
);
......@@ -261,9 +263,11 @@ module cmprs_cmd_decode#(
reg [ 2:0] coring_xclk; // color saturation values (only 10 LSB in each 12 are used
wire uncompressed_mclk;
wire uncompressed_xclk;
assign cmprs_en_mclk = cmprs_en_mclk_r;
assign uncompressed_mclk = cmprs_mode_mclk[3:0] == CMPRS_CBIT_CMODE_RAW;
assign uncompressed_xclk = cmprs_mode_xclk[3:0] == CMPRS_CBIT_CMODE_RAW;
always @ (posedge mclk) begin
if (mrst) ctrl_we_r <= 0;
......@@ -478,10 +482,17 @@ module cmprs_cmd_decode#(
converter_type[2:0] <= 'bx;
end
endcase
uncompressed <= cmprs_mode_xclk[3:0] == CMPRS_CBIT_CMODE_RAW;
// uncompressed <= cmprs_mode_xclk[3:0] == CMPRS_CBIT_CMODE_RAW;
end
always @ (posedge xclk) begin
if (!cmprs_en_mclk_r || (!uncompressed_xclk && !compressor_running)) uncompressed <= 0;
else if (frame_start_xclk) uncompressed <= uncompressed_xclk;
if (!cmprs_en_mclk_r || ( uncompressed_xclk && !compressor_running)) compressed <= 0;
else if (frame_start_xclk) compressed <= !uncompressed_xclk;
end
end
//frame_start_xclk
pulse_cross_clock ctrl_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
......
compressor_jp/cmprs_raw_buf_iface.v
View file @ aeb5b749
......@@ -96,7 +96,7 @@ module cmprs_raw_buf_iface #(
reg [14:0] quads_left; // number of quad bytes left in a row (after this)
reg [16:0] rows_left; // number of rows left (after this)
reg [1:0] rows_last;
reg page_run;
reg page_run; // on after page_start, off after quad_r[2], so during last quad_r[3] shold be off
reg [3:0] quad_r;
reg quad_last; // last quad byte in a row should be valid @quad_r[2]
wire page_start;
......@@ -106,6 +106,9 @@ module cmprs_raw_buf_iface #(
wire frame_finish_w;
wire frames_pending;
reg starting; // from frame_start_r to first page start
reg mode_valid;// after parameters are valid, invalid whe mode is reset
reg page_end_r;
reg frame_done;
assign frame_en_w = frame_en && frame_go; // both are inputs
// one extra at the end of frame is needed (sequence will be short) ???
......@@ -116,21 +119,25 @@ module cmprs_raw_buf_iface #(
assign buf_diff = needed_page - next_valid;
assign buf_ready_w = buf_diff[2];
assign page_start = !page_run && buf_ready_w && frame_pre_run && (starting && stuffer_running); // frame_pre_run should deassert in time with frame end
// assign page_start = !page_run && buf_ready_w && ((frame_pre_run && starting && stuffer_running) || !frame_done); // frame_pre_run should deassert in time with frame end
assign page_start = !page_run && buf_ready_w && frame_pre_run && ((starting && stuffer_running) || !frame_done); // frame_pre_run should deassert in time with frame end
reg page_end_r;
// reg page_restart_r;
assign raw_start = frame_pre_start_r; // for JP - leading edge of color_first
assign page_end_w = frame_en && quad_r[2] && (&bufa_r[9:2] || quad_last);
// assign page_end_w = frame_en && quad_r[2] && (&bufa_r[9:2] || quad_last);
assign page_end_w = frame_en && quad_r[1] && (&bufa_r[9:2] || quad_last);
assign release_buf = page_end_w;
// assign release_buf = page_end_w;
assign release_buf = page_end_r;
assign frame_finish_w = frame_finish_r[1] && !frame_finish_r[0];
assign frames_pending = !frame_que_cntr[FRAME_QUEUE_WIDTH] && (|frame_que_cntr[FRAME_QUEUE_WIDTH-1:0]);
assign frame_en_w = frame_en && frame_go;
assign raw_prefb = buf_rd_r[0]; // delay if memory registered more. TODO Add parameter if it already used
// assign raw_prefb = buf_rd_r[0]; // delay if memory registered more. TODO Add parameter if it already used
assign raw_prefb = quad_r[1]; // delay if memory registered more. TODO Add parameter if it already used
assign raw_ts_copy = frame_en_r && rows_last[0] && !rows_last[1];
......@@ -147,6 +154,13 @@ module cmprs_raw_buf_iface #(
if (reset_page_rd) next_valid <= 0;
else if (page_ready) next_valid <= next_valid + 1;
if (!frame_en) mode_valid <= 0;
// else if (frame_start_xclk) mode_valid <= frame_start_xclk;
else if (frame_pre_start_r) mode_valid <= 1; // frame_pre_start_r sets remaining quads, rows
cmprs_run_xclk <= cmprs_run_mclk;
frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start
......@@ -175,7 +189,8 @@ module cmprs_raw_buf_iface #(
// page_run
if (!frame_pre_run) page_run <= 0;
else if (page_start) page_run <= 1;
else if (quad_r[2] && page_end_r) page_run <= 0;
// else if (quad_r[2] && page_end_r) page_run <= 0;
else if (page_end_r) page_run <= 0;
if (!frame_pre_run) quad_r <= 0;
else quad_r <= {quad_r[2:0], page_start | (quad_r[3] & page_run)};
......@@ -189,17 +204,20 @@ module cmprs_raw_buf_iface #(
if (frame_pre_start_r || (quad_r[2] && quad_last)) quads_left <= {n_blocks_in_row_m1, 2'b11};
else if (quad_r[2]) quads_left <= quads_left - 1;
quad_last <= !(|quads_left); // valid from 2 after frame_pre_start_r or after quad_r[3]
quad_last <= mode_valid && !(|quads_left); // valid from 2 after frame_pre_start_r or after quad_r[3]
if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
else if ((quad_r[2] && quad_last)) rows_left <= rows_left - 1;
rows_last <= {rows_last[0], ~(|rows_left)};
rows_last <= {rows_last[0], mode_valid & ~(|rows_left)};
// if (frame_pre_start_r) bufa_r[11:10] <= needed_page[1:0];
if (page_start) bufa_r[11:10] <= needed_page[1:0];
if (frame_pre_start_r) bufa_r[11:10] <= needed_page[1:0];
if (frame_pre_start_r) bufa_r[9:1] <= 0;
else if (quad_r[3]) bufa_r[9:1] <= bufa_r[9:1] + 1;
// if (frame_pre_start_r) bufa_r[9:1] <= 0;
if (page_start) bufa_r[9:1] <= 0;
else if (quad_r[1] | quad_r[3]) bufa_r[9:1] <= bufa_r[9:1] + 1;
if (frame_pre_start_r) bufa_r[0] <= raw_be16;
else if (buf_rd_r[0]) bufa_r[0] <= ~bufa_r[0];
......@@ -207,6 +225,9 @@ module cmprs_raw_buf_iface #(
if (!frame_en || (!frames_pending && frame_finish_w)) frame_pre_run <= 0;
else if (frame_pre_start_w) frame_pre_run <= 1;
if (!frame_en || frame_pre_start_r) frame_done <= 0;
else if (quad_r[2] && quad_last && rows_last) frame_done <= 1; // valid @ quad_r[3], when page_run is already == 0
end
reg nmrst;
......
compressor_jp/huffman_stuffer_raw_meta.v
View file @ aeb5b749
......@@ -70,6 +70,7 @@ module huffman_stuffer_raw_meta(
input color_first, // @fradv_clk only used for timestamp
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
......@@ -180,6 +181,7 @@ module huffman_stuffer_raw_meta(
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.compressed_mode(compressed_mode), // input
.raw_mode (raw_mode), // input
.raw_be16 (raw_be16), // input
.raw_bytes (raw_bytes), // input[7:0]
......
compressor_jp/jp_channel.v
View file @ aeb5b749
......@@ -382,6 +382,7 @@ module jp_channel#(
wire [15:0] quant_dc_tdo;// MSB aligned coefficient for the DC component (used in focus module)
wire [ 2:0] cmprs_qpage;
wire [ 2:0] coring_num;
wire compressed;
wire uncompressed;
wire raw_be16; // raw bytes in little-endian order need to be converted to big endian 16-bit ones
wire raw_start; // input
......@@ -749,6 +750,7 @@ module jp_channel#(
.frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse
.cmprs_en_mclk (cmprs_en_mclk), // output
.cmprs_en_extend (cmprs_en_extend), // input
.compressor_running (reading_frame || stuffer_running), // input
.cmprs_run_mclk (cmprs_run_mclk), // output reg
.cmprs_standalone (cmprs_standalone), // output reg
.sigle_frame_buf (sigle_frame_buf), // output reg
......@@ -772,6 +774,7 @@ module jp_channel#(
.color_sat_cb (m_cb), // output[9:0] reg
.color_sat_cr (m_cr), // output[9:0] reg
.coring (coring_num), // output[2:0] reg
.compressed (compressed), // output reg
.uncompressed (uncompressed), // output reg
.be16 (raw_be16) // output reg
);
......@@ -1238,6 +1241,7 @@ module jp_channel#(
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input valid @xclk - only for sec/usec
.compressed_mode (compressed), // input
.raw_mode (uncompressed), // input
.raw_be16 (1'b0), // raw_be16), // input
.raw_bytes (buf_pxd), // input[7:0]
......@@ -1248,8 +1252,8 @@ module jp_channel#(
.data_out (stuffer_do), // output[31:0]
.data_out_valid (stuffer_dv), // output
.done (stuffer_done), // output
.running (stuffer_running), // output
.done (stuffer_done), // output // after trailer
.running (stuffer_running), // output // DID not include trailer (bug?), now includes (after raw debugging)
.clk_flush (hclk), // input
.flush_clk (flush_hclk) // output
......
memctrl/mcntrl_tiled_linear_rw.v
View file @ aeb5b749
......@@ -528,11 +528,10 @@ module mcntrl_tiled_linear_rw#(
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign keep_open= mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte)
assign linear_mode = mode_reg[MCONTR_LINTILE_BYTE32 ]; // use linear mode instead of the tiled
assign linear_mode = mode_reg[MCONTR_LINTILE_LINEAR]; // NEW
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
// assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE]; // from LINEAR
assign linear_mode = mode_reg[MCONTR_LINTILE_LINEAR]; // NEW
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
assign status_data= {frames_in_sync, suspend, last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
......@@ -637,7 +636,12 @@ module mcntrl_tiled_linear_rw#(
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
always @(posedge mclk) begin
// acceletaring pre_want - copied from LINEAR (faster, equivalent), start matching
pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
// pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
// FIXME: Same in LINEAR module?
pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) &&!xfer_start_r[0];
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
xfer_start_r[0] ||
......
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