more on hispi code

includes/x393_parameters.vh

@@ -530,7 +530,7 @@
     parameter BUF_IPCLK2X_SENS3 =        "BUFG", // "BUFR",  
 
     parameter SENS_DIVCLK_DIVIDE =       1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =       0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =       0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =       0.010,
     parameter SENS_SS_EN         =       "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =       "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

sensor/sens_hispi12l4.v

@@ -37,7 +37,7 @@ module  sens_hispi12l4#(
     parameter BUF_IPCLK2X =               "BUFR",  
 
     parameter SENS_DIVCLK_DIVIDE =         1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =         0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =         0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =         0.010,
     parameter SENS_SS_EN         =        "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =        "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
@@ -55,10 +55,6 @@ module  sens_hispi12l4#(
 )(
     input             pclk,   // global clock input, pixel rate (220MHz for MT9F002)
     input             prst,
-    output            irst,
-    
-    input             trigger_mode, // running in triggered mode (0 - free running mode)
-    input             trig,      // per-sensor trigger input
     // I/O pads
     input [HISPI_NUMLANES-1:0] sns_dp,
     input [HISPI_NUMLANES-1:0] sns_dn,
@@ -77,6 +73,7 @@ module  sens_hispi12l4#(
     input                           ld_idelay,       // mclk synchronous set idealy value
     input                           set_clk_phase,   // mclk synchronous set idealy value
     input                           rst_mmcm,
+    input                           ignore_embedded, // ignore lines with embedded data
 //    input                           wait_all_lanes,  // when 0 allow some lanes missing sync (for easier phase adjustment)
     // MMCP output status
     output       ps_rdy,          // output
@@ -159,6 +156,10 @@ module  sens_hispi12l4#(
     localparam WAIT_ALL_LANES = 8; // number of output pixel cycles to wait after the earliest lane
     localparam FIFO_DEPTH = 4;
 
+    reg       [2:0] irst_r;
+    wire            irst = irst_r[2];
+    
+
     wire [HISPI_NUMLANES * 12-1:0] hispi_aligned;
     wire      [HISPI_NUMLANES-1:0] hispi_dv;
     wire      [HISPI_NUMLANES-1:0] hispi_embed;
@@ -186,13 +187,16 @@ module  sens_hispi12l4#(
     wire  [HISPI_NUMLANES * 12-1:0] fifo_out;
     wire                            hact_on;
     wire                            hact_off;
-
+    reg                             ignore_embedded_ipclk;
     assign hact_out = hact_r;
     
     always @(posedge ipclk) begin
-       if (irst || (|hispi_eof[i])) vact_ipclk <= 0; // extend output if hact active
-       else if (|hispi_sof)         vact_ipclk <= 1;
+        irst_r <= {irst_r[1:0], prst};
+    
+        if (irst || (|hispi_eof[i])) vact_ipclk <= 0; // extend output if hact active
+        else if (|hispi_sof)         vact_ipclk <= 1;
     
+        ignore_embedded_ipclk <= ignore_embedded;
     end
     
     always @(posedge pclk) begin
@@ -285,7 +289,7 @@ module  sens_hispi12l4#(
                 .ipclk    (ipclk),                     // input
                 .irst     (irst),                      // input
                 .we       (hispi_dv[i]),               // input
-                .sol      (hispi_sol[i]),              // input
+                .sol      (hispi_sol[i] && (hispi_embed[i] || !ignore_embedded_ipclk)), // input
                 .eol      (hispi_eol[i]),              // input
                 .din      (hispi_aligned[12*i +: 12]), // input[11:0] 
                 .pclk     (pclk),                      // input
@@ -295,7 +299,6 @@ module  sens_hispi12l4#(
                 .run      (rd_run[i])                  // output
             );
         
-        
         end
     endgenerate        
 

sensor/sens_hispi_clock.v

@@ -34,7 +34,7 @@ module  sens_hispi_clock#(
     parameter BUF_IPCLK2X =               "BUFR",  
 
     parameter SENS_DIVCLK_DIVIDE =         1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =         0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =         0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =         0.010,
     parameter SENS_SS_EN         =        "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =        "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

sensor/sens_hispi_fifo.v

+/*******************************************************************************
+ * Module: sens_hispi_fifo
+ * Date:2015-10-14  
+ * Author: andrey     
+ * Description: cross-clock FIFO with special handling of 'run' output
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * sens_hispi_fifo.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  sens_hispi_fifo.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  sens_hispi_fifo#(
+  parameter COUNT_START = 7, // wait these many samples input before starting output
+  parameter DATA_WIDTH = 12,
+  parameter DATA_DEPTH = 4 // >=3
+) (
+    input                       ipclk,
+    input                       irst,
+    input                       we,
+    input                       sol,     // start of line - 1 cycle before dv
+    input                       eol,     // end of line - last dv 
+    input      [DATA_WIDTH-1:0] din,
+    input                       pclk,
+    input                       prst,
+    input                       re,
+    output reg [DATA_WIDTH-1:0] dout,   // valid next cycle after re
+    output                      run    // has latency 1 after last re
+);
+    reg [DATA_WIDTH-1:0] fifo_ram[0 : (1 << DATA_DEPTH) -1];
+    reg   [DATA_DEPTH:0] wa;
+    reg   [DATA_DEPTH:0] ra;
+    wire                 line_start_pclk;
+    reg                  line_run_ipclk;
+    reg                  line_run_pclk;
+    reg                  run_r;
+    
+    assign run = run_r;
+    
+    
+    always @ (posedge ipclk) begin
+        if      (irst ||sol)           wa <= 0;
+        else if (we && line_run_ipclk) wa <= wa + 1;
+        
+        if (we && line_run_ipclk) fifo_ram[wa] <= din;
+        
+        if (irst || eol) line_run_ipclk <= 0;
+        else if (sol)    line_run_ipclk <= 1;
+    end
+
+    always @(posedge pclk) begin
+        line_run_pclk <= line_run_ipclk && (line_run_pclk || line_start_pclk);
+        
+        if (prst)                              run_r <= 0;
+        else if (line_start_pclk)              run_r <= 1;
+        else if (!line_run_pclk && (ra == wa)) run_r <= 0;
+        
+        if (prst ||line_start_pclk) ra <= 0;
+        else if (re)                ra <= ra + 1;
+        
+        if (re) dout <= fifo_ram[ra];
+        
+    end
+    
+    pulse_cross_clock #(
+        .EXTRA_DLY(0)
+    ) pulse_cross_clock_line_start_i (
+        .rst       (irst),                      // input
+        .src_clk   (ipclk),                     // input
+        .dst_clk   (pclk),                      // input
+        .in_pulse  (we && (wa == COUNT_START)), // input
+        .out_pulse (line_start_pclk),           // output
+        .busy() // output
+    );
+
+
+endmodule
+

sensor/sens_parallel12.v

@@ -71,7 +71,7 @@ module  sens_parallel12 #(
     
 
     parameter SENS_DIVCLK_DIVIDE =     1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =     0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =     0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =     0.010,
     parameter SENS_SS_EN         =     "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =     "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

sensor/sensor_channel.v

@@ -202,7 +202,7 @@ module  sensor_channel#(
     parameter BUF_IPCLK2X =           "BUFR",  
 
     parameter SENS_DIVCLK_DIVIDE =     1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =     0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =     0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =     0.010,
     parameter SENS_SS_EN         =     "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =     "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

sensor/sensors393.v

@@ -231,7 +231,7 @@ module  sensors393 #(
     
 
     parameter SENS_DIVCLK_DIVIDE =       1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter SENS_REF_JITTER1   =       0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter SENS_REF_JITTER1   =       0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter SENS_REF_JITTER2   =       0.010,
     parameter SENS_SS_EN         =       "FALSE",      // Enables Spread Spectrum mode
     parameter SENS_SS_MODE       =       "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

wrap/mmcm_adv.v

@@ -62,7 +62,7 @@ module  mmcm_adv#(
                                                // EXTERNAL - external to the FPGA network is being compensated
                                                // BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT
     parameter DIVCLK_DIVIDE =         1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter REF_JITTER1   =         0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter REF_JITTER1   =         0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter REF_JITTER2   =         0.010,
     parameter SS_EN         =         "FALSE",      // Enables Spread Spectrum mode
     parameter SS_MODE       =         "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

wrap/mmcm_phase_cntr.v

@@ -63,7 +63,7 @@ module  mmcm_phase_cntr#(
                                                // EXTERNAL - external to the FPGA network is being compensated
                                                // BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT
     parameter DIVCLK_DIVIDE =         1,            // Integer 1..106. Divides all outputs with respect to CLKIN
-    parameter REF_JITTER1   =         0.010,        // Expectet jitter on CLKIN1 (0.000..0.999)
+    parameter REF_JITTER1   =         0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
     parameter REF_JITTER2   =         0.010,
     parameter SS_EN         =         "FALSE",      // Enables Spread Spectrum mode
     parameter SS_MODE       =         "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"

wrap/obufds.v

+/*******************************************************************************
+ * Module: obufds
+ * Date:2015-10-15  
+ * Author: andrey     
+ * Description: Wrapper for OBUFDS primitive
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * obufds.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  obufds.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  obufds #(
+    parameter CAPACITANCE = "DONT_CARE",
+    parameter IOSTANDARD =  "DEFAULT",
+    parameter SLEW =        "SLOW"
+)(
+    output o,
+    output ob,
+    input  i
+);
+    OBUFDS #(
+        .CAPACITANCE (CAPACITANCE),
+        .IOSTANDARD  (IOSTANDARD),
+        .SLEW(SLEW)
+    ) OBUFDS_i (
+        .O    (o),  // output 
+        .OB   (ob), // output 
+        .I    (i)  // input 
+    );
+
+
+endmodule
+

x393_testbench02.tf

@@ -300,7 +300,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     assign PX1_MCLK_PRE =  sns1_dp[6]; // from FPGA to sensor
     assign PX1_MRST =      sns1_dp[7]; // from FPGA to sensor
     assign PX1_ARST =      sns1_dn[7]; // same as GP[3]
-    assign PX1_ARO =       sns1_dn[5]; // same as GP[2]
+    assign PX1_ARO =       sns1_dn[5]; // same as GP[1]
     
     assign sns2_dp[3:0] =  PX2_LANE_P;
     assign sns2_dn[3:0] =  PX2_LANE_N;
@@ -313,7 +313,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     assign PX2_MCLK_PRE =  sns2_dp[6]; // from FPGA to sensor
     assign PX2_MRST =      sns2_dp[7]; // from FPGA to sensor
     assign PX2_ARST =      sns2_dn[7]; // same as GP[3]
-    assign PX2_ARO =       sns2_dn[5]; // same as GP[2]
+    assign PX2_ARO =       sns2_dn[5]; // same as GP[1]
     
     assign sns3_dp[3:0] =  PX3_LANE_P;
     assign sns3_dn[3:0] =  PX3_LANE_N;
@@ -326,7 +326,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     assign PX3_MCLK_PRE =  sns3_dp[6]; // from FPGA to sensor
     assign PX3_MRST =      sns3_dp[7]; // from FPGA to sensor
     assign PX3_ARST =      sns3_dn[7]; // same as GP[3]
-    assign PX3_ARO =       sns3_dn[5]; // same as GP[2]
+    assign PX3_ARO =       sns3_dn[5]; // same as GP[1]
     
     assign sns4_dp[3:0] =  PX4_LANE_P;
     assign sns4_dn[3:0] =  PX4_LANE_N;
@@ -339,7 +339,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     assign PX4_MCLK_PRE =  sns4_dp[6]; // from FPGA to sensor
     assign PX4_MRST =      sns4_dp[7]; // from FPGA to sensor
     assign PX4_ARST =      sns4_dn[7]; // same as GP[3]
-    assign PX4_ARO =       sns4_dn[5]; // same as GP[2]
+    assign PX4_ARO =       sns4_dn[5]; // same as GP[1]
 `else
     //connect parallel12 sensor to sensor port 1
     assign sns1_dp[6:1] =  {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
@@ -349,7 +349,7 @@ parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - emb
     assign PX1_ARST =       sns1_dn[7];
     assign sns1_clkn =      PX1_D[0];  // inout CNVSYNC/TDI
     assign sns1_clkp =      PX1_D[1];  // CNVCLK/TDO
-    assign PX1_ARO =       sns1_ctl;  // from FPGA to sensor
+    assign PX1_ARO =        sns1_ctl;  // from FPGA to sensor
 
     assign PX2_MRST =       sns2_dp[7]; // from FPGA to sensor
     assign PX2_MCLK_PRE =   sns2_dp[0]; // from FPGA to sensor