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x393
Commit ae33ff53 authored by Andrey Filippov's avatar Andrey Filippov
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implemented sync reset, fpga version 0x03930136

parent 823ad682
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Showing with 1475 additions and 1294 deletions
cocotb/x393_cocotb_lwir_04.sav
View file @ ae33ff53
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Apr 30 17:21:50 2019
[*] Fri May 3 04:06:38 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190430003141791.fst"
[dumpfile_mtime] "Tue Apr 30 17:20:36 2019"
[dumpfile_size] 1896466138
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
[dumpfile_mtime] "Fri May 3 04:06:09 2019"
[dumpfile_size] 19575412
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
[timestart] 0
[size] 1804 1171
[pos] -1 -1
*-28.897251 1413970273 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-25.245840 49300000 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_lwir160x120_vospi1_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.
......@@ -87,9 +86,11 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 204
[treeopen] x393_dut.x393_i.timing393_i.rtc393_i.
[sst_width] 402
[signals_width] 335
[sst_expanded] 1
[sst_vpaned_height] 459
......@@ -3022,6 +3023,53 @@ x393_dut.sns1_sda
@1401200
-SENSOR3
@800200
-khz
-timing
@1000200
-timing
@800200
-rtc393
@28
x393_dut.x393_i.timing393_i.rtc393_i.enable_rtc
x393_dut.x393_i.timing393_i.rtc393_i.mclk
x393_dut.x393_i.timing393_i.rtc393_i.khz
@22
x393_dut.x393_i.timing393_i.rtc393_i.khz_cntr[9:0]
@28
(0)x393_dut.x393_i.timing393_i.rtc393_i.inc_usec[1:0]
@1000200
-rtc393
-khz
@800200
-reset_seq
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.set_ctrl_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.ms
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_rst_seq_pclk
@800022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_seq[1:0]
@1001200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_on_cntr
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.mrst_after_cntr[2:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
@200
-
@1000200
-reset_seq
@800200
-sens_channel0
-lepto3_0
@28
......@@ -3094,14 +3142,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_set
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.raddr[10:0]
@29
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]
@200
-
@800200
-packet
@28
......
fpga_version.vh
View file @ ae33ff53
......@@ -35,7 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930133; // Testing sof to hact delay
parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
// parameter FPGA_VERSION = 32'h03930135; // Adding multi-cam reset
// parameter FPGA_VERSION = 32'h0393014; // Adding multi-cam reset - buggy
// parameter FPGA_VERSION = 32'h03930133; // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0
// parameter FPGA_VERSION = 32'h03930132; // Sync from serial bumber start, added output (with hact)
// parameter FPGA_VERSION = 32'h03930131; // Sync from serial bumber start
// parameter FPGA_VERSION = 32'h03930130; // Adding output for receive start frame
......
includes/x393_parameters.vh
View file @ ae33ff53
......@@ -548,8 +548,8 @@
//`elsif LWIR
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
......@@ -589,6 +589,16 @@
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif
//`else
//sensor_fifo parameters (for parallel12)
parameter SENSOR_DATA_WIDTH = 12,
......
py393/vrlg.py
View file @ ae33ff53
......@@ -576,7 +576,6 @@ SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
CMPRS_TABLES__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
......@@ -616,6 +615,7 @@ SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
LWIR_TELEMETRY__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
......@@ -737,6 +737,7 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
HISTOGRAM_HEIGHT = int
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
VOSPI_RST_SEQ__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
CLK_STATUS__TYPE = str
VOSPI_OUT_EN_BITS = int
......@@ -762,11 +763,13 @@ SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
VOSPI_SEGM0_OK = int
VOSPI_RST_SEQ = int
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
VOSPI_MRST_BITS__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
NUM_CYCLES_09__RAW = str
VOSPI_SPI_SEQ = int
SENS_SYNC_LBITS__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
SENS_GAMMA_HEIGHT2 = int
......@@ -835,7 +838,6 @@ REFRESH_OFFSET = int
MCNTRL_PS_EN_RST = int
MCONTR_SENS_BASE__RAW = str
SENS_GAMMA_ADDR_MASK__TYPE = str
VOSPI_PWDN__RAW = str
CMPRS_CSAT_CR = int
CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
......@@ -950,7 +952,7 @@ VOSPI_MRST_BITS__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
MULTICLK_DIV_XCLK__TYPE = str
MEMBRIDGE_LEN64 = int
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
......@@ -1051,7 +1053,7 @@ NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
VOSPI_SPI_SEQ__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
MEMBRIDGE_LO_ADDR64__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
......@@ -1201,6 +1203,7 @@ CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
SENSI2C_CMD_USE_EOF__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
VOSPI_MRST_MS = int
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
......@@ -1214,6 +1217,7 @@ MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
VOSPI_VSYNC__RAW = str
CLKFBOUT_PHASE_SENSOR__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
MCONTR_SENS_BASE = int
CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
......@@ -1405,6 +1409,7 @@ NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE = str
CAMSYNC_ADDR = int
FFCLK1_CAPACITANCE__RAW = str
VOSPI_SPI_SEQ__RAW = str
VOSPI_PACKET_LAST__RAW = str
RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
......@@ -1429,7 +1434,6 @@ SENSI2C_TBL_RAH_BITS__TYPE = str
LWIR_WINDOW_WIDTH = int
CMPRS_AFIMUX_WIDTH = int
HISTOGRAM_ADDR_MASK__TYPE = str
VOSPI_PWDN__TYPE = str
HISTOGRAM_RADDR3__TYPE = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSOR_TIMING_START = int
......@@ -1474,6 +1478,7 @@ LAST_BUF_FRAME = int
SENS_REF_JITTER1 = float
SENS_REF_JITTER2 = float
MCNTRL_TILED_FRAME_SIZE__RAW = str
VOSPI_MRST_AFTER_MS = int
MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
......@@ -1777,7 +1782,7 @@ HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS = int
CMPRS_MONO8__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
CMPRS_AFIMUX_REG_ADDR0 = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_BANDWIDTH__TYPE = str
LD_DLY_LANE0_IDELAY__TYPE = str
CLKFBOUT_PHASE__RAW = str
......@@ -1987,6 +1992,7 @@ SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
SENSI2C_TBL_NBWR_BITS = int
VOSPI_RST_SEQ__TYPE = str
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS0 = str
......@@ -2035,6 +2041,7 @@ MCONTR_BUF0_RD_ADDR__TYPE = str
CMPRS_STATUS_REG_INC__TYPE = str
DLY_LANE0_IDELAY__TYPE = str
MCNTRL_PS_ADDR__TYPE = str
VOSPI_SPI_TIMEOUT_MS = int
WINDOW_WIDTH__RAW = str
MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
......@@ -2043,9 +2050,8 @@ SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE = str
IPCLK2X_PHASE__TYPE = str
SENSOR_HIST_BITS_SET = int
VOSPI_DBG_SRC__TYPE = str
CLK_MASK = int
MCNTRL_SCANLINE_CHN1_ADDR = int
VOSPI_PWDN_BITS__TYPE = str
VOSPI_MCLK__TYPE = str
MULT_SAXI_HALF_BRAM_IN = int
CMDFRAMESEQ_ADDR_INC__RAW = str
......@@ -2131,6 +2137,7 @@ CAMSYNC_SNDEN_BIT = int
DQSTRI_FIRST__RAW = str
SENSI2C_CTRL_MASK__TYPE = str
LWIR_TELEMETRY_SREV = int
VOSPI_SPI_TIMEOUT_MS__RAW = str
SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
......@@ -2146,12 +2153,14 @@ MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
VOSPI_MRST_AFTER_MS__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
CLKFBOUT_PHASE_SENSOR__TYPE = str
SENSOR_HIST_NRST_BITS__TYPE = str
GPIO_PORTEN = int
RTC_STATUS_REG_ADDR__TYPE = str
SENS_JTAG_TCK__TYPE = str
VOSPI_SPI_TIMEOUT_MS__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
......@@ -2172,6 +2181,7 @@ MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
VOSPI_MRST_AFTER_MS__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
VOSPI_PACKET_TTT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
......@@ -2185,7 +2195,6 @@ MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str
VOSPI_PWDN_BITS__RAW = str
DQTRI_FIRST = int
CONTROL_RBACK_DEPTH = int
CAMSYNC_TRIG_DELAY0 = int
......@@ -2249,6 +2258,7 @@ HISPI_DQS_BIAS__RAW = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
VOSPI_MRST_MS__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY = long
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
......@@ -2321,7 +2331,7 @@ CMPRS_CBIT_RUN_BITS = int
SENS_LENS_AY_MASK = int
BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MEMBRIDGE_LEN64 = int
MULTICLK_DIV_XCLK__TYPE = str
HISPI_MMCM2__TYPE = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
......@@ -2381,7 +2391,6 @@ CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
VOSPI_PWDN_BITS = int
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
......@@ -2391,6 +2400,7 @@ DFLT_CHN_EN = int
GPIO_STATUS_REG_ADDR__RAW = str
DLY_DQS_ODELAY = long
SENSOR_CHN_EN_BIT__RAW = str
VOSPI_MRST_MS__RAW = str
CMPRS_AFIMUX_RADDR1 = int
CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
......@@ -2403,7 +2413,6 @@ SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str
VOSPI_PWDN = int
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
VOSPI_MRST = int
......@@ -2519,7 +2528,7 @@ VOSPI_HACT_TO_HACT_EOF__TYPE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
CMDFRAMESEQ_IRQ_BIT__TYPE = str
CLK_MASK = int
VOSPI_DBG_SRC__TYPE = str
MCONTR_BUF4_WR_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
......@@ -2598,7 +2607,7 @@ MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
SENS_LENS_FAT0_OUT__TYPE = str
CMPRS_TABLES__TYPE = str
VOSPI_SPI_CLK = int
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
......
py393/x393_export_c.py
View file @ ae33ff53
......@@ -2126,10 +2126,9 @@ class X393ExportC(object):
def _enc_sensio_ctrl_vospi(self):
dw=[]
dw.append(("mrst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("reset", vrlg.VOSPI_MRST, 2, 0, "Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset"))
dw.append(("rst_seq", vrlg.VOSPI_RST_SEQ, 1, 0, "Initiate simultaneous all sensors reset, generate SOF after pause"))
dw.append(("spi_seq", vrlg.VOSPI_SPI_SEQ, 1, 0, "Initiate VOSPI reset, will generate normal SOF if successful"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
......
py393/x393_sens_cmprs.py
View file @ ae33ff53
......@@ -763,8 +763,8 @@ class X393SensCmprs(object):
elif sensorType == x393_sensor.SENSOR_INTERFACE_VOSPI:
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = True,
pwdn = False,
rst = 2, # mrst, no power down
# TODO - use rst_seq instead?
mclk = True, # None,
spi_en = 1, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero = True, #None,
......@@ -776,13 +776,10 @@ class X393SensCmprs(object):
if self.DRY_MODE:
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = False)
rst = 3) # no mrst, no power down
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
spi_en = 2) #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
# self.x393Sensor.set_sensor_io_ctl_lwir (
# num_sensor = num_sensor,
# spi_en = 2) #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
......@@ -791,7 +788,7 @@ class X393SensCmprs(object):
self.sleep_ms(0.2) # 1 ms. TODO: For real camera turn off all channels simultaneously ***
self.x393Sensor.set_sensor_io_ctl_lwir (
num_sensor = num_sensor,
mrst = False,
rst = 3, # no mrst, no power down
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True)
......
py393/x393_sensor.py
View file @ ae33ff53
......@@ -454,8 +454,9 @@ class X393Sensor(object):
return rslt
def func_sensor_io_ctl_lwir (self,
mrst = None,
pwdn = None,
rst = None,
rst_seq = None,
spi_seq = None,
mclk = None,
spi_en = None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero = None,
......@@ -474,8 +475,9 @@ class X393Sensor(object):
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param pwdn - True - activate POWER_DOWN signal (low), False - deactivate POWER_DOWN (high), None - no change
@param rst - Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset
@param rst_seq Initiate simultaneous all sensors reset, generate SOF after pause
@param spi_seq Initiate VOSPI reset, will generate normal SOF if successful
@param mclk - True - enable master clock (25MHz) to sensor, False - disable, None - no change
@param spi_en - True - SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable, None - no change
@param segm_zero = True - allow receiving segment ID==0 (ITAR invalid), False - disallow, None - no change,
......@@ -500,10 +502,12 @@ class X393Sensor(object):
@return VOSPI sensor i/o control word
"""
rslt = 0
if not mrst is None:
rslt |= (3,2)[mrst] << vrlg.VOSPI_MRST
if not pwdn is None:
rslt |= (3,2)[pwdn] << vrlg.VOSPI_PWDN
if not rst is None:
rslt |= (rst & 3) << vrlg.VOSPI_MRST
if rst_seq:
rslt |= 1 << vrlg.VOSPI_RST_SEQ
if spi_seq:
rslt |= 1 << vrlg.VOSPI_SPI_SEQ
if not mclk is None:
rslt |= (2,3)[mclk] << vrlg.VOSPI_MCLK
if not spi_en is None:
......@@ -1068,8 +1072,9 @@ class X393Sensor(object):
def set_sensor_io_ctl_lwir (self,
num_sensor,
mrst = None,
pwdn = None,
rst = None,
rst_seq = None,
spi_seq = None,
mclk = None,
spi_en = None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
segm_zero = None,
......@@ -1085,11 +1090,11 @@ class X393Sensor(object):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param pwdn - True - activate POWER_DOWN signal (low), False - deactivate POWER_DOWN (high), None - no change
@param rst - Sensor reset/power down control (0 - NOP, 1 - power down + reset, 2 - no pwdn, reset, 3 - no pwdn, no reset
@param rst_seq Initiate simultaneous all sensors reset, generate SOF after pause
@param spi_seq Initiate VOSPI reset, will generate normal SOF if successful
@param mclk - True - enable master clock (25MHz) to sensor, False - disable, None - no change
@param spi_en - True - SPI reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable, None - no change
@param segm_zero = True - allow receiving segment ID==0 (ITAR invalid), False - disallow, None - no change,
......@@ -1116,8 +1121,9 @@ class X393Sensor(object):
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_ctl_lwir (num_sensor,
mrst = mrst,
pwdn = pwdn,
rst = rst,
rst_seq = rst_seq,
spi_seq = spi_seq,
mclk = mclk,
spi_en = spi_en,
segm_zero = segm_zero,
......@@ -1137,8 +1143,9 @@ class X393Sensor(object):
except:
pass
data = self.func_sensor_io_ctl_lwir (
mrst = mrst,
pwdn = pwdn,
rst = rst,
rst_seq = rst_seq,
spi_seq = spi_seq,
mclk = mclk,
spi_en = spi_en,
segm_zero = segm_zero,
......
sensor/sens_lepton3.v
View file @ ae33ff53
......@@ -43,72 +43,18 @@ module sens_lepton3 #(
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
/*
parameter SENSIO_JTAG = 'h2,
parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
*/
parameter SENSIO_STATUS_REG = 'h21,
/*
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
parameter SENS_CTRL_MRST= 0, // 1: 0
parameter SENS_CTRL_ARST= 2, // 3: 2
parameter SENS_CTRL_ARO= 4, // 5: 4
parameter SENS_CTRL_RST_MMCM= 6, // 7: 6
parameter SENS_CTRL_EXT_CLK= 8, // 9: 8
parameter SENS_CTRL_LD_DLY= 10, // 10
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
parameter SENS_CTRL_ODD = 6, //
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
parameter LINE_WIDTH_BITS = 16,
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4,
*/
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16) parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
// mode bits
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST = 0, // 0 - NOP, 1 - power down reset, 1 no power down reset, 3 - no power down , no reset
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
......@@ -142,7 +88,10 @@ module sens_lepton3 #(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
)(
// programming interface
input mrst, // @posedge mclk, sync reset
......@@ -186,10 +135,20 @@ module sens_lepton3 #(
// not used PADS, keep for compatibility with PCB
inout dp2, // input reserved - used for hardware debug (output for oscilloscope)
input dn2, // input reserved
input dn6 // input reserved
input dn6 , // input reserved
// reset synchronization
input ext_rst_in,
input ext_rstseq_in,
output ext_rst_out,
output ext_rstseq_out,
input khz // 1 KHz 50% duty @ mclk
);
localparam VOSPI_STATUS_BITS = 15;
localparam VOSPI_STATUS_BITS = 17;
localparam MRST_CNTR_BITS = clogb2(VOSPI_MRST_MS + 1); // 3
localparam MRST_AFTER_CNTR_BITS = clogb2(VOSPI_MRST_AFTER_MS+ 1); // 11
localparam SPI_TIMEOUT_CNTR_BITS = clogb2(VOSPI_SPI_TIMEOUT_MS+ 1); // 8
// Status data (6 bits + 4)
wire [VOSPI_STATUS_BITS-1:0] status;
wire [ 3:0] segment_id;
......@@ -223,7 +182,11 @@ module sens_lepton3 #(
reg out_en_mclk; // single paulse - single frame, level - continuous
wire out_en_single_mclk;
wire err_reset_mclk;
wire start_rst_seq_mclk;
wire start_spi_seq_mclk;
reg lwir_mrst_mclk;
reg ext_rst_in_mclk;
reg lwir_pwdn_mclk;
reg sns_mclk_en_mclk;
reg spi_clk_en_mclk;
......@@ -247,9 +210,11 @@ module sens_lepton3 #(
reg [ 1:0] use_telemetry_pclk;
reg [ 1:0] vsync_pclk;
wire vsync;
reg [ 3:0] khz_pclk;
reg [ 3:0] init_sof_pclk;
wire out_en_single_pclk;
wire err_reset_pclk;
wire sof_w;
// wire fake_out;
......@@ -283,17 +248,39 @@ module sens_lepton3 #(
wire mipi_clkn_int;
wire dbg_tel_sync; // certain 32 bits in the telemetry
wire dbg_tel_sync_out;
wire ms; // 1 millisecond pulses @pclk
wire start_rst_seq_pclk;
wire start_spi_seq_pclk;
reg [MRST_CNTR_BITS-1:0] mrst_on_cntr;
reg [MRST_AFTER_CNTR_BITS-1:0] mrst_after_cntr;
reg [SPI_TIMEOUT_CNTR_BITS-1:0] spi_timeout_cntr;
reg [1:0] mrst_seq;
reg spi_seq;
assign ext_rst_out = mrst_seq[0];
assign ext_rstseq_out = mrst_seq[1];
// temporary?
assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int ^ fake_dp2 ^ fake_dn2 ^ fake_dn6;
assign out_en_single_mclk = set_ctrl_r && data_r[VOSPI_OUT_EN_SINGL] && !mrst;
assign err_reset_mclk = set_ctrl_r && data_r[VOSPI_RESET_ERR] && !mrst;
assign start_rst_seq_mclk = set_ctrl_r && data_r[VOSPI_RST_SEQ] && !mrst;
assign start_spi_seq_mclk = set_ctrl_r && data_r[VOSPI_SPI_SEQ] && !mrst;
assign prsts = prst | !lwir_mrst_pclk[1];
assign vsync = gpio_in[3];
assign ms = khz_pclk[3];
assign sof = init_sof_pclk[3] | sof_w;
assign status = {
fake_in,
ext_rst_in,
ext_rstseq_in,
sync_err_r,
crc_err_r,
out_busy,
......@@ -321,6 +308,9 @@ module sens_lepton3 #(
always @(posedge mclk) begin
if (mrst) ext_rst_in_mclk <= 0;
else ext_rst_in_mclk <= ext_rst_in;
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
......@@ -342,13 +332,18 @@ module sens_lepton3 #(
if (mrst) out_en_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_OUT_EN + VOSPI_OUT_EN_BITS - 1]) out_en_mclk <= data_r[VOSPI_OUT_EN];
if (mrst) lwir_mrst_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_MRST + VOSPI_MRST_BITS - 1]) lwir_mrst_mclk <= data_r[VOSPI_MRST];
if (mrst) lwir_pwdn_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_PWDN + VOSPI_PWDN_BITS - 1]) lwir_pwdn_mclk <= data_r[VOSPI_PWDN];
else if (ext_rst_in_mclk) lwir_pwdn_mclk <= 1; // turn off power down with external reset cycle
else if (set_ctrl_r && |data_r[VOSPI_MRST +: VOSPI_MRST_BITS]) lwir_pwdn_mclk <= data_r[VOSPI_MRST + 1];
if (mrst) lwir_mrst_mclk <= 0;
else if (ext_rst_in_mclk) lwir_mrst_mclk <= 1; // turn off internal sensor reset with external reset cycle
else if (set_ctrl_r && |data_r[VOSPI_MRST +: VOSPI_MRST_BITS]) lwir_mrst_mclk <= &data_r[VOSPI_MRST +: 2];
if (mrst) sns_mclk_en_mclk <= 0;
else if (ext_rst_in_mclk) sns_mclk_en_mclk <= 1; // enable sensor master clock with external reset cycle
else if (set_ctrl_r && data_r[VOSPI_MCLK + VOSPI_MCLK_BITS - 1]) sns_mclk_en_mclk <= data_r[VOSPI_MCLK];
if (mrst) spi_clk_en_mclk <= 0;
......@@ -371,11 +366,11 @@ module sens_lepton3 #(
end
// resync to pclk
always @ (posedge pclk) begin
spi_nrst_pclk[1:0] <= {spi_nrst_pclk[0], spi_nrst_mclk};
spi_en_pclk[1:0] <= {spi_en_pclk[0], spi_en_mclk};
spi_nrst_pclk[1:0] <= {spi_nrst_pclk[0], spi_nrst_mclk & ~spi_seq & ~ext_rstseq_in};
spi_en_pclk[1:0] <= {spi_en_pclk[0], spi_en_mclk & ~spi_seq & ~ext_rstseq_in};
segm0_ok_pclk[1:0] <= {segm0_ok_pclk[0], segm0_ok_mclk};
out_en_pclk[1:0] <= {out_en_pclk[0], out_en_mclk};
lwir_mrst_pclk[1:0] <= {lwir_mrst_pclk[0], lwir_mrst_mclk};
lwir_mrst_pclk[1:0] <= {lwir_mrst_pclk[0], lwir_mrst_mclk & ~ext_rst_in};
lwir_pwdn_pclk[1:0] <= {lwir_pwdn_pclk[0], lwir_pwdn_mclk};
spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk};
vsync_use_pclk[1:0] <= {vsync_use_pclk[0], vsync_use_mclk};
......@@ -392,8 +387,45 @@ module sens_lepton3 #(
if (prst || err_reset_pclk) sync_err_r <= 0;
else if (sync_err_w) sync_err_r <= 1;
// reg [ 3:0] init_sof_pclk;
end
// Reset sequence generation
always @ (posedge pclk) begin
if (prst) khz_pclk <= 0;
else khz_pclk <= {khz_pclk[1] & ~khz_pclk[2], khz_pclk[1:0], khz};
if (prst) init_sof_pclk <= 0;
else init_sof_pclk <= {~init_sof_pclk[1] & init_sof_pclk[2], init_sof_pclk[1:0], ext_rstseq_in};
if (prst) mrst_seq[0] <= 0;
else if (start_rst_seq_pclk) mrst_seq[0] <= 1;
else if (ms && (mrst_on_cntr == 0)) mrst_seq[0] <= 0;
if (prst) mrst_seq[1] <= 0;
else if (start_rst_seq_pclk) mrst_seq[1] <= 1;
else if (ms && !mrst_seq[0] && (mrst_after_cntr == 0)) mrst_seq[1] <= 0;
if (!mrst_seq[0]) mrst_on_cntr <= (VOSPI_MRST_MS -1);
else if (ms) mrst_on_cntr <= mrst_on_cntr -1;
if (!mrst_seq[1] || mrst_seq[0]) mrst_after_cntr <= (VOSPI_MRST_AFTER_MS -1);
else if (ms) mrst_after_cntr <= mrst_after_cntr -1;
// currently reset SPI does not try to sync with the frames being processed - they should be stopped/reenabled
if (!spi_seq) spi_timeout_cntr <= (VOSPI_SPI_TIMEOUT_MS -1);
else if (ms) spi_timeout_cntr <= spi_timeout_cntr -1;
if (prst) spi_seq <= 0;
else if (start_spi_seq_pclk) spi_seq <= 1;
else if (ms && (spi_timeout_cntr == 0)) spi_seq <= 0;
end
always @(posedge mclk) begin
if (mrst) sns_mclk_r <= 0;
else if (sns_mclk_cntr == 0) sns_mclk_r <= sns_mclk_en_mclk && !sns_mclk_r;
......@@ -425,6 +457,26 @@ module sens_lepton3 #(
.busy() // output
);
pulse_cross_clock pulse_cross_clock_start_rst_seq_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (start_rst_seq_mclk), // input
.out_pulse (start_rst_seq_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_start_spi_seq_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (start_spi_seq_mclk), // input
.out_pulse (start_spi_seq_pclk), // output
.busy() // output
);
// implement I/O ports, including fake ones, to be able to assign them I/O pads
// generate clocka to sesnor output, controlled by control word bits
// SPI clock (10..20MHz)
......@@ -548,7 +600,8 @@ module sens_lepton3 #(
) lwir_mrst_i (
.O (), // output - currently not used
.IO (lwir_mrst), // inout I/O pad
.I (lwir_mrst_pclk[0]), // input
// .I (lwir_mrst_pclk[0]), // input
.I (lwir_mrst_pclk[1]), // input
.T (1'b0) // input - always on
);
......@@ -710,7 +763,7 @@ module sens_lepton3 #(
.discard_segment (discard_segment), // output
.dout (pxd), // output[15:0]
.hact (hact), // output
.sof (sof), // output
.sof (sof_w), // output
.eof (eof), // output
.crc_err (crc_err_w), // output
.sync_err (sync_err_w), // output
......@@ -758,7 +811,15 @@ module sens_lepton3 #(
.start (status_start) // input
);
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin // SuppressThisWarning VEditor - VDT bug
value = value >> 1;
end
end
endfunction
endmodule
sensor/sensor_channel.v
View file @ ae33ff53
......@@ -240,8 +240,8 @@ module sensor_channel#(
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
......@@ -275,8 +275,10 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
......@@ -437,6 +439,18 @@ module sensor_channel#(
output [1:0] hist_chn, // output[1:0] histogram (sub) channel, valid with request and transfer
output hist_dvalid, // output data valid - active when sending a burst
output [31:0] hist_data // output[31:0] histogram data
`ifdef LWIR
// reset synchronization
,input ext_rst_in,
input ext_rstseq_in,
output ext_rst_out,
output ext_rstseq_out
`endif
// currently used only for LWIR
,input khz // 1 KHz 50% @mclk
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
......@@ -1004,61 +1018,15 @@ module sensor_channel#(
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
/*
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
*/
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
/*
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
*/
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_RST_SEQ (VOSPI_RST_SEQ), // 2,
.VOSPI_SPI_SEQ (VOSPI_SPI_SEQ), // 3,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
......@@ -1092,7 +1060,10 @@ module sensor_channel#(
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV) // 4
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
) sens_lepton3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1126,7 +1097,13 @@ module sensor_channel#(
// not used PADS, keep for compatibility with PCB
.dp2 (sns_dp40[2]), // inout reserved - used for debug
.dn2 (sns_dn40[2]), // input reserved
.dn6 (sns_dn76[6]) // input reserved
.dn6 (sns_dn76[6]), // input reserved
// reset synchronization
.ext_rst_in (ext_rst_in), // input
.ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out), // output
.ext_rstseq_out (ext_rstseq_out), // output
.khz (khz) // input 1 KHz 50% duty @ mclk
);
// sns_dn76[6] - not used
// sns_dn40[2] - not used
......
sensor/sensors393.v
View file @ ae33ff53
......@@ -236,8 +236,8 @@ module sensors393 #(
parameter VOSPI_SLEW = "FAST", // "SLOW",
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_RST_SEQ = 2, // initiate reset cycle (master drives all sensors), generate frame start when ready
parameter VOSPI_SPI_SEQ = 3, // initilate SPI re-sync (will automatically generate frame syncs when re-synced)
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
......@@ -272,7 +272,9 @@ module sensors393 #(
parameter VOSPI_SOF_TO_HACT = 100, // 10, // clock cycles from SOF to HACT (limited to 8 bits)
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 5, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
......@@ -506,6 +508,7 @@ module sensors393 #(
,output [2 * 4 - 1 : 0] dbg_rpage
,output [2 * 4 - 1 : 0] dbg_wpage
`endif
,input khz // 1 KHz 50% @mclk
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
......@@ -543,8 +546,13 @@ module sensors393 #(
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
wire ext_rst_in;
wire ext_rstseq_in;
wire [3:0] ext_rst_out;
wire [3:0] ext_rstseq_out;
assign ext_rst_in = |ext_rst_out;
assign ext_rstseq_in = |ext_rstseq_out;
always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in;
......@@ -720,8 +728,8 @@ module sensors393 #(
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_RST_SEQ (VOSPI_RST_SEQ), // 2,
.VOSPI_SPI_SEQ (VOSPI_SPI_SEQ), // 3,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
......@@ -755,8 +763,10 @@ module sensors393 #(
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV) // 4
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
......@@ -868,14 +878,14 @@ module sensors393 #(
.status_start (status_start_chn[i]), // input
.trigger_mode (trigger_mode), // input
.trig_in (trig_in[i]), // input
.frame_num_seq(frame_num[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // input[3:0]
.frame_num_seq (frame_num[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // input[3:0]
.dout (px_data[16 * i +: 16]), // output[15:0]
.dout_valid (px_valid[i]), // output
.last_in_line (last_in_line[i]), // output
.sof_out (sof_out_pclk[i]), // output
.eof_out (eof_out_pclk[i]), // output
.sof_out_mclk (sof_out_mclk[i]), // output
.sof_late_mclk(sof_late_mclk[i]), // output
.sof_late_mclk (sof_late_mclk[i]), // output
.hist_request (hist_request[i]), // output
.hist_frame (hist_frame[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // output[3:0]
......@@ -883,6 +893,14 @@ module sensors393 #(
.hist_chn (hist_chn[2 * i +: 2]), // output[1:0]
.hist_dvalid (hist_dvalid[i]), // output
.hist_data (hist_data[i * 32 +: 32])// output[31:0]
`ifdef LWIR
,.ext_rst_in (ext_rst_in), // input
.ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out[i]), // output
.ext_rstseq_out (ext_rstseq_out[i]) // output
`endif
,.khz (khz) // input 1 KHz 50% duty
`ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output
.debug_sl (debug_sl), // input
......
timing/rtc393.v
View file @ ae33ff53
......@@ -68,7 +68,8 @@ module rtc393 #(
input status_start, // Acknowledge of the first status packet byte (address)
output [31:0] live_sec,
output [19:0] live_usec);
output [19:0] live_usec,
output khz);
// output reg snap); // take a snapshot (externally)
wire [31:0] cmd_data;
......@@ -85,6 +86,9 @@ module rtc393 #(
reg [15:0] corr;
reg [RTC_BITC_PREDIV-1:0] pre_cntr = 0;
wire [RTC_BITC_PREDIV-1:0] pre_cntr_m1;
wire [RTC_BITC_PREDIV-1:0] RTC_MHZ_m1;
reg [3:0] halfusec = 0; // 1-hot running pulse with 0.5 usec period
reg [2:0] refclk_mclk;
reg refclk2x_mclk;
......@@ -99,6 +103,8 @@ module rtc393 #(
reg [19:0] usec;
reg [31:0] sec;
reg [9:0] khz_cntr;
reg [19:0] usec_plus1;
reg [31:0] sec_plus1;
......@@ -106,7 +112,7 @@ module rtc393 #(
reg [19:0] pio_usec; // micro seconds snapshot to be read as PIO
reg pio_alt_snap; // FF to invert after each PIO snapshot (used to generate status)
assign khz = khz_cntr[9];
assign set_usec_w = cmd_we && (cmd_a == RTC_SET_USEC);
assign set_sec_w = cmd_we && (cmd_a == RTC_SET_SEC);
assign set_corr_w = cmd_we && (cmd_a == RTC_SET_CORR);
......@@ -115,11 +121,17 @@ module rtc393 #(
assign live_sec = sec;
assign live_usec = usec;
assign pre_cntr_m1 = pre_cntr -1;
assign RTC_MHZ_m1 = RTC_MHZ - 1;
always @ (posedge mclk) begin
if (mrst) pio_alt_snap <= 0;
else if (set_status_w) pio_alt_snap <= ~pio_alt_snap;
end
`ifdef SIMULATION
localparam CONST499 = 4; // 100 times faster, 10 1KHz will be 100 KHz
`else
localparam CONST499 = 499;
`endif
always @ (posedge mclk) begin
if (set_status_w) pio_sec <= live_sec;
......@@ -146,7 +158,7 @@ module rtc393 #(
// else halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
if (!enable_rtc) pre_cntr <= RTC_MHZ-1;
else if (refclk2x_mclk) pre_cntr <= (|pre_cntr) ? (pre_cntr - 1) : (RTC_MHZ-1);
else if (refclk2x_mclk) pre_cntr <= (|pre_cntr) ? pre_cntr_m1 : RTC_MHZ_m1;
if (!enable_rtc) halfusec <= 0;
else halfusec <= {halfusec[2:0], (|pre_cntr || !refclk2x_mclk)?1'b0:1'b1};
......@@ -179,6 +191,16 @@ module rtc393 #(
if (set_cntr) sec[31:0] <= wsec[31:0];
else if (inc_sec[1]) sec[31:0] <= sec_plus1[31:0];
//khz_cntr
if (!enable_rtc) khz_cntr[8:0] <= CONST499;
else if (inc_usec[1]) begin
if (khz_cntr[8:0] == 0) khz_cntr[8:0] <= CONST499;
else khz_cntr[8:0] <= khz_cntr[8:0] - 1;
end
if (!enable_rtc) khz_cntr[9] <= 0;
else if (inc_usec[1] && (khz_cntr[8:0] == 0)) khz_cntr[9] <= ~khz_cntr[9];
end
cmd_deser #(
......
timing/timing393.v
View file @ ae33ff53
......@@ -130,8 +130,8 @@ module timing393 #(
input lrst, // @ posedge lclk - sync reset
input ts_logger_snap, // request from the logger to take a snapshot
output ts_logger_stb, // one clock pulse before sending TS data
output [7:0] ts_logger_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
output [7:0] ts_logger_data, // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
output khz // 1 KHz 50% output
);
wire [3:0] frame_sync;
......@@ -180,7 +180,9 @@ module timing393 #(
.status_rq (status_rq), // output
.status_start (status_start), // input
.live_sec (live_sec), // output[31:0]
.live_usec (live_usec) // output[19:0]
.live_usec (live_usec), // output[19:0]
.khz (khz) // output
);
......
x393.v
View file @ ae33ff53
......@@ -615,6 +615,7 @@ module x393 #(
wire ts_pre_logger_stb; // input logger timestamp sync (@logger_clk)
wire [7:0] ts_logegr_data; // input[7:0] loger timestamp data (@logger_clk)
wire khz; // 1 KHz 50% duty
// Compressor signals for interrupts generation
wire [3:0] eof_written_mclk; // output // SuppressThisWarning VEditor - (yet) unused
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
......@@ -1846,8 +1847,8 @@ assign axi_grst = axi_rst_pre;
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_RST_SEQ (VOSPI_RST_SEQ), // 2,
.VOSPI_SPI_SEQ (VOSPI_SPI_SEQ), // 3,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
......@@ -1882,7 +1883,9 @@ assign axi_grst = axi_rst_pre;
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 100,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 5
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
`else
......@@ -2067,7 +2070,7 @@ assign axi_grst = axi_rst_pre;
,.dbg_rpage (dbg_rpage[7:0]) // output[7:0]
,.dbg_wpage (dbg_wpage[7:0]) // output[7:0]
`endif
,.khz (khz) // input 1 KHz 50% duty
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
......@@ -2428,7 +2431,8 @@ assign axi_grst = axi_rst_pre;
.lrst (lrst), // input
.ts_logger_snap (logger_snap), // input
.ts_logger_stb (ts_pre_logger_stb), // output
.ts_logger_data (ts_logegr_data) // output[7:0]
.ts_logger_data (ts_logegr_data), // output[7:0]
.khz (khz) // output // 1 KHz 50% output
);
event_logger #(
......
x393_vospi.bit
View file @ ae33ff53
No preview for this file type
x393_vospi.timing_summary_impl
View file @ ae33ff53
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_vospi_utilization.report
View file @ ae33ff53
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Tue Apr 30 13:08:01 2019
| Date : Thu May 2 22:27:59 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41899 | 0 | 78600 | 53.31 |
| LUT as Logic | 38547 | 0 | 78600 | 49.04 |
| LUT as Memory | 3352 | 0 | 26600 | 12.60 |
| Slice LUTs | 42274 | 0 | 78600 | 53.78 |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 550 | 0 | | |
| Slice Registers | 54053 | 0 | 157200 | 34.38 |
| Register as Flip Flop | 54053 | 0 | 157200 | 34.38 |
| LUT as Shift Register | 554 | 0 | | |
| Slice Registers | 54220 | 0 | 157200 | 34.49 |
| Register as Flip Flop | 54220 | 0 | 157200 | 34.49 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -57,9 +57,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 8 | Yes | - | Set |
| 672 | Yes | - | Reset |
| 1026 | Yes | Set | - |
| 52347 | Yes | Reset | - |
| 680 | Yes | - | Reset |
| 1084 | Yes | Set | - |
| 52448 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16499 | 0 | 19650 | 83.96 |
| SLICEL | 10887 | 0 | | |
| SLICEM | 5612 | 0 | | |
| LUT as Logic | 38547 | 0 | 78600 | 49.04 |
| using O5 output only | 5 | | | |
| using O6 output only | 29897 | | | |
| using O5 and O6 | 8645 | | | |
| LUT as Memory | 3352 | 0 | 26600 | 12.60 |
| Slice | 16898 | 0 | 19650 | 85.99 |
| SLICEL | 11122 | 0 | | |
| SLICEM | 5776 | 0 | | |
| LUT as Logic | 38918 | 0 | 78600 | 49.51 |
| using O5 output only | 1 | | | |
| using O6 output only | 30285 | | | |
| using O5 and O6 | 8632 | | | |
| LUT as Memory | 3356 | 0 | 26600 | 12.62 |
| LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 550 | 0 | | |
| using O5 output only | 275 | | | |
| using O6 output only | 221 | | | |
| using O5 and O6 | 54 | | | |
| LUT Flip Flop Pairs | 24341 | 0 | 78600 | 30.97 |
| fully used LUT-FF pairs | 4497 | | | |
| LUT-FF pairs with one unused LUT output | 17618 | | | |
| LUT-FF pairs with one unused Flip Flop | 17682 | | | |
| Unique Control Sets | 4761 | | | |
| LUT as Shift Register | 554 | 0 | | |
| using O5 output only | 285 | | | |
| using O6 output only | 219 | | | |
| using O5 and O6 | 50 | | | |
| LUT Flip Flop Pairs | 24502 | 0 | 78600 | 31.17 |
| fully used LUT-FF pairs | 4550 | | | |
| LUT-FF pairs with one unused LUT output | 17779 | | | |
| LUT-FF pairs with one unused Flip Flop | 17787 | | | |
| Unique Control Sets | 4739 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -196,18 +196,18 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52347 | Flop & Latch |
| LUT3 | 11357 | LUT |
| LUT6 | 10054 | LUT |
| LUT2 | 8436 | LUT |
| LUT4 | 7995 | LUT |
| LUT5 | 7765 | LUT |
| FDRE | 52448 | Flop & Latch |
| LUT3 | 11328 | LUT |
| LUT6 | 10336 | LUT |
| LUT2 | 8397 | LUT |
| LUT4 | 7992 | LUT |
| LUT5 | 7901 | LUT |
| RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2733 | CarryLogic |
| LUT1 | 1585 | LUT |
| LUT1 | 1596 | LUT |
| RAMS32 | 1392 | Distributed Memory |
| FDSE | 1026 | Flop & Latch |
| FDCE | 672 | Flop & Latch |
| FDSE | 1084 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 496 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory |
| IBUF | 99 | IO |
......
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