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Commit ac01dea9 authored by Andrey Filippov's avatar Andrey Filippov
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cleaning up

parent c7c4510d
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dct_tests_02.sav
View file @ ac01dea9
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 9 01:30:06 2017
[*] Sat Dec 9 23:22:47 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_02-20171206113130304.fst"
[dumpfile_mtime] "Wed Dec 6 18:31:30 2017"
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_02-20171209161906877.fst"
[dumpfile_mtime] "Sat Dec 9 23:19:07 2017"
[dumpfile_size] 222572
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_02.sav"
[timestart] 1319200
[timestart] 0
[size] 1814 1171
[pos] 0 40
*-15.492632 1451000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-20.492632 3096000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_02.
[treeopen] dct_tests_02.dtt_iv_8x8_i.
[treeopen] dct_tests_02.dtt_iv_8x8r_i.
......@@ -59,6 +59,9 @@ dct_tests_02.dtt_iv_8x8_i.xin[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.pre_last_in
dct_tests_02.dtt_iv_8x8_i.pre_first_out
@29
dct_tests_02.dtt_iv_8x8_i.pre_busy
@28
dct_tests_02.dtt_iv_8x8_i.dv
@420
dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
......@@ -177,12 +180,12 @@ dct_tests_02.dtt_iv_8x8_i.dctv_out_run
dct_tests_02.dtt_iv_8x8_i.dctv_out_start_1
@22
dct_tests_02.dtt_iv_8x8_i.dctv_out_wa[4:0]
@c00029
@c00028
dct_tests_02.dtt_iv_8x8_i.dctv_out_we[1:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.dctv_out_we[1:0]
(1)dct_tests_02.dtt_iv_8x8_i.dctv_out_we[1:0]
@1401201
@1401200
-group_end
@1000200
-debug
......
dct_tests_03.sav
View file @ ac01dea9
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 9 05:38:48 2017
[*] Sat Dec 9 23:05:14 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_03-20171208223621417.fst"
[dumpfile_mtime] "Sat Dec 9 05:36:24 2017"
[dumpfile_size] 225832
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_03-20171209160023169.fst"
[dumpfile_mtime] "Sat Dec 9 23:00:23 2017"
[dumpfile_size] 225733
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_03.sav"
[timestart] 0
[size] 1920 1171
[pos] -1920 40
*-20.492632 1460700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-20.492632 1605000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_03.
[treeopen] dct_tests_03.dtt_iv_8x8_i.
[treeopen] dct_tests_03.dtt_iv_8x8r_i.
[sst_width] 299
[sst_width] 318
[signals_width] 287
[sst_expanded] 1
[sst_vpaned_height] 344
......@@ -34,10 +34,6 @@ dct_tests_03.mode_in[1:0]
dct_tests_03.x_in_2d[23:0]
@8420
dct_tests_03.x_in_2d[23:0]
@420
dct_tests_03.d_out_2d[23:0]
@8420
dct_tests_03.d_out_2d[23:0]
@22
dct_tests_03.mode_out[1:0]
@420
......@@ -58,12 +54,6 @@ dct_tests_03.dtt_iv_8x8_i.xin[23:0]
dct_tests_03.dtt_iv_8x8_i.xin[23:0]
@28
dct_tests_03.dtt_iv_8x8_i.pre_last_in
dct_tests_03.dtt_iv_8x8_i.pre_first_out
dct_tests_03.dtt_iv_8x8_i.dv
@420
dct_tests_03.dtt_iv_8x8_i.d_out[23:0]
@8420
dct_tests_03.dtt_iv_8x8_i.d_out[23:0]
@800200
-debug
@28
......@@ -175,8 +165,6 @@ dct_tests_03.dtt_iv_8x8_i.dctv_out_sel
[color] 2
dct_tests_03.dtt_iv_8x8_i.dctv_out_run
dct_tests_03.dtt_iv_8x8_i.dctv_out_start_1
@22
dct_tests_03.dtt_iv_8x8_i.dctv_out_wa[4:0]
@c00028
dct_tests_03.dtt_iv_8x8_i.dctv_out_we[1:0]
@28
......@@ -231,22 +219,20 @@ dct_tests_03.out_ram_ren
dct_tests_03.out_ram_regen
@22
dct_tests_03.out_ram_ra[5:0]
@8420
dct_tests_03.out_ram_r[23:0]
@23
dct_tests_03.out_ram_r2[23:0]
@29
dct_tests_03.out_pre_first
@28
dct_tests_03.out_ram_dv
@1000200
-debug
@22
dct_tests_03.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_03.dtt_iv_8x8_i.pre_first_out_w
@8420
dct_tests_03.dtt_iv_8x8_i.d_out[23:0]
@28
dct_tests_03.dtt_iv_8x8_i.dv
dct_tests_03.dtt_iv_8x8_i.pre_first_out
dct_tests_03.dtt_iv_8x8_i.pre_busy
dct_tests_03.dtt_iv_8x8_i.pre_first_out
@c00200
-direct_internal
@28
......
dsp/dct_tests_03.tf
View file @ ac01dea9
......@@ -118,7 +118,7 @@ module dct_tests_03 ();
wire pre_first_out_2d; // SuppressThisWarning VEditor - simulation only
wire pre_busy_2d; // SuppressThisWarning VEditor - simulation only
wire dv_2d; // SuppressThisWarning VEditor - simulation only
wire signed [OUT_WIDTH-1:0] d_out_2d;
// wire signed [OUT_WIDTH-1:0] d_out_2d;
wire pre_last_in_2dr; // SuppressThisWarning VEditor - simulation only
wire pre_first_out_2dr; // SuppressThisWarning VEditor - simulation only
......@@ -352,12 +352,16 @@ module dct_tests_03 ();
wire [ODEPTH-1:0] out_ram_wa = {out_ram_wah,out_wa};
reg out_ram_ren;
reg out_ram_regen;
reg out_ram_dv;
wire out_pre_first;
reg [5:0] out_ram_ra;
reg signed [OUT_WIDTH-1:0] out_ram_r;
reg signed [OUT_WIDTH-1:0] out_ram_r2;
always @ (posedge CLK) begin
if (RST) out_ram_cntr <= 0;
else if (inc16) out_ram_cntr <= out_ram_cntr + 1;
......@@ -370,7 +374,7 @@ module dct_tests_03 ();
else if (&out_ram_ra) out_ram_ren <= 1'b0;
out_ram_regen <= out_ram_ren;
out_ram_dv <= out_ram_regen;
if (!out_ram_ren) out_ram_ra <= 0;
else out_ram_ra <= out_ram_ra + 1;
......@@ -379,6 +383,17 @@ module dct_tests_03 ();
end
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_out_pre_first_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (start64), // input[0:0]
.dout (out_pre_first) // output[0:0]
);
dtt_iv_8x8_ad #(
.INPUT_WIDTH (WIDTH),
......@@ -396,9 +411,6 @@ module dct_tests_03 ();
.mode (mode_in), // input[1:0]
.xin (x_in_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2d), // output reg
.pre_first_out (pre_first_out_2d), // output
.dv (dv_2d), // output
.d_out (d_out_2d), // output[24:0] signed
.mode_out (mode_out), // output[1:0] reg
.pre_busy (pre_busy_2d), // output reg
.out_wd (out_wd), // output[24:0] reg
......@@ -411,7 +423,7 @@ module dct_tests_03 ();
dtt_iv_8x8 #(
dtt_iv_8x8_obuf #(
.INPUT_WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
......@@ -423,14 +435,14 @@ module dct_tests_03 ();
) dtt_iv_8x8r_i (
.clk (CLK), // input
.rst (RST), // input
.start (pre_first_out_2d), // input
.start (out_pre_first), // pre_first_out_2d), // input
.mode ({mode_out[0],mode_out[1]}), // input[1:0] // result is transposed
.xin (d_out_2d), // input[24:0] signed
.xin (out_ram_r2), // d_out_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2dr), // output reg
.pre_first_out (pre_first_out_2dr), // output
.dv (dv_2dr), // output
.d_out (d_out_2dr), // output[24:0] signed
.mode_out (), // output[1:0] reg
.mode_out (), // output[1:0] reg
.pre_busy (pre_busy_2dr) // output reg
);
......
dsp/dtt_iv_8x8_ad.v
View file @ ac01dea9
......@@ -48,7 +48,7 @@ module dtt_iv_8x8_ad#(
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter COSINE_SHIFT= 17,
parameter ODEPTH = 5, // output buffer depth (bits). Here 5, put can use more if used as a full block buffer
// parameter ODEPTH = 5, // output buffer depth (bits). Here 5, put can use more if used as a full block buffer
parameter COS_01_32 = 130441, // int(round((1<<17) * cos( 1*pi/32)))
parameter COS_03_32 = 125428, // int(round((1<<17) * cos( 3*pi/32)))
parameter COS_04_32 = 121095, // int(round((1<<17) * cos( 4*pi/32)))
......@@ -68,9 +68,6 @@ module dtt_iv_8x8_ad#(
// Next data should be sent in bursts of 8, pause of 8 - total 128 cycles
input signed [INPUT_WIDTH-1:0] xin, //!< input data
output pre_last_in, //!< output high during input of the pre-last of 64 pixels in a 8x8 block (next can be start
output reg pre_first_out, //!< 1 cycle ahead of the first output in a 64 block
output reg dv, //!< data output valid. WAS: Will go high on the 94-th cycle after the start
output signed [OUT_WIDTH-1:0] d_out, //!< output data
output reg [1:0] mode_out, //!< copy of mode input, valid @ pre_first_out
output reg pre_busy, //!< start should come each 64-th cycle (next after pre_last_in), and not after pre_busy)
output reg [OUT_WIDTH-1:0] out_wd, //!< output data to write to external output buffer memory
......@@ -159,8 +156,8 @@ module dtt_iv_8x8_ad#(
wire signed [OUT_WIDTH-1:0] dctv_dout1;
wire dctv_en_out0;
wire dctv_en_out1;
wire [2:0] dctv_yindex0;
wire [2:0] dctv_yindex1;
///wire [2:0] dctv_yindex0;
///wire [2:0] dctv_yindex1;
wire dctv_phin_start = transpose_out_run && (transpose_rcntr[5:0] == 8);
reg dctv_phin_run;
......@@ -176,27 +173,14 @@ module dtt_iv_8x8_ad#(
reg dctv_start_1_r;
reg pre_last_in_r;
reg [6:0] dctv_out_cntr; // count output data from second (vertical) pass (bit 6 - stopping)
reg dctv_out_run; //
wire dctv_out_start = dctv_phin [6:0] == 'h11;
reg [6:0] out_cntr; // count output data from second (vertical) pass (bit 6 - stopping)
reg out_run; //
wire out_start = dctv_phin [6:0] == 'h12;
reg out_sel; // which of the 2 output channels to select
reg [ODEPTH-1:0] dctv_out_wa;
reg [1:0] dctv_out_we;
reg dctv_out_sel; // select DCTv channel output;
reg signed [OUT_WIDTH-1:0] dctv_out_ram[0: ((1<<ODEPTH)-1)]; // [0:31];
reg [2:0] dctv_out_debug_ram[0:((1<<ODEPTH)-1)]; // [0:31];
reg [6:0] dctv_out_ra;
wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0e; // 'h0b;
reg pre_dv;
reg signed [OUT_WIDTH-1:0] dctv_out_reg;
reg [2:0] dctv_out_debug_reg; // SuppressThisWarning VEditor - simulation only
reg [1:0] mode_h; // registered at start, [1] used for hor (first) pass
......@@ -208,10 +192,9 @@ module dtt_iv_8x8_ad#(
reg pre_dsth; // 1 cycles before horizontal output data is valid, 0 dct, 1 - dst
reg pre_dstv; // 1 cycles before vertical output data is valid, 0 dct, 1 - dst
reg dstv; // when vertical output data is valid, 0 dct, 1 - dst
wire pre_first_out_w = dctv_out_start_1;
wire [OUT_WIDTH-1:0] debug_dctv_dout = dctv_out_sel? dctv_dout1: dctv_dout0; // SuppressThisWarning VEditor - simulation only
assign d_out = dctv_out_reg;
wire start64_w = out_cntr[6:0] == 'h0d;
assign pre_last_in = pre_last_in_r;
......@@ -224,7 +207,9 @@ module dtt_iv_8x8_ad#(
if (start) mode_h <= mode;
if (pre_last_in) mode_h_late <= mode_h;
if (transpose_out_start) mode_v <= mode_h_late;
if (pre_first_out_w) mode_out <= mode_v;
if (start64_w) mode_out <= mode_v;
if (!x_run) x_wa <= 0;
else x_wa <= x_wa + 1;
......@@ -356,56 +341,9 @@ module dtt_iv_8x8_ad#(
dctv_debug_xin0 <= t_debug_ram0[t_ra0[2:0]];
dctv_debug_xin1 <= t_debug_ram1[t_ra1[2:0]];
// Reordering data from a pair of vertical DCTs - 2 steps, 1 is not enough
if (rst) dctv_out_run <= 0;
else if (dctv_out_start) dctv_out_run <= 1;
else if (dctv_out_cntr[6:0] == 'h47) dctv_out_run <= 0;
if (!dctv_out_run || dctv_out_start) dctv_out_cntr <= 0;
else dctv_out_cntr <= dctv_out_cntr + 1;
dctv_out_we <= {dctv_out_we[0], dctv_en_out0 | dctv_en_out1};
dctv_out_sel <= dctv_out_cntr[0];
case (dctv_out_cntr[3:0])
4'h0: dctv_out_wa[3:0] <= 4'h0 ^ {1'b0,{3{pre_dstv}}};
4'h1: dctv_out_wa[3:0] <= 4'h9 ^ {1'b0,{3{pre_dstv}}};
4'h2: dctv_out_wa[3:0] <= 4'h7 ^ {1'b0,{3{pre_dstv}}};
4'h3: dctv_out_wa[3:0] <= 4'he ^ {1'b0,{3{pre_dstv}}};
4'h4: dctv_out_wa[3:0] <= 4'h4 ^ {1'b0,{3{pre_dstv}}};
4'h5: dctv_out_wa[3:0] <= 4'ha ^ {1'b0,{3{pre_dstv}}};
4'h6: dctv_out_wa[3:0] <= 4'h3 ^ {1'b0,{3{pre_dstv}}};
4'h7: dctv_out_wa[3:0] <= 4'hd ^ {1'b0,{3{pre_dstv}}};
4'h8: dctv_out_wa[3:0] <= 4'h1 ^ {1'b0,{3{pre_dstv}}};
4'h9: dctv_out_wa[3:0] <= 4'h8 ^ {1'b0,{3{pre_dstv}}};
4'ha: dctv_out_wa[3:0] <= 4'h6 ^ {1'b0,{3{pre_dstv}}};
4'hb: dctv_out_wa[3:0] <= 4'hf ^ {1'b0,{3{pre_dstv}}};
4'hc: dctv_out_wa[3:0] <= 4'h2 ^ {1'b0,{3{pre_dstv}}};
4'hd: dctv_out_wa[3:0] <= 4'hc ^ {1'b0,{3{pre_dstv}}};
4'he: dctv_out_wa[3:0] <= 4'h5 ^ {1'b0,{3{pre_dstv}}};
4'hf: dctv_out_wa[3:0] <= 4'hb ^ {1'b0,{3{pre_dstv}}};
endcase
// It is possible to fill large output memory buffer, in that case
dctv_out_wa[ODEPTH-1:4] <= dctv_out_cntr[ODEPTH-1:4] - (~dctv_out_cntr[3] & dctv_out_cntr[0]);
// write first stage of output reordering
if (dctv_out_we[1]) dctv_out_ram[dctv_out_wa] <= dctv_out_sel? dctv_dout1: dctv_dout0;
if (dctv_out_we[1]) dctv_out_debug_ram[dctv_out_wa] <= dctv_out_sel? dctv_yindex1: dctv_yindex0;
if (rst) pre_dv <= 0;
else if (dctv_out_start_1) pre_dv <= 1;
else if (&dctv_out_ra[5:0]) pre_dv <= 0;
if (!pre_dv || dctv_out_start_1) dctv_out_ra <= 0;
else dctv_out_ra <= dctv_out_ra + 1;
// reading first stage of output reorder RAM
if (pre_dv) dctv_out_reg <= dctv_out_ram[dctv_out_ra[4:0]];
if (pre_dv) dctv_out_debug_reg <= dctv_out_debug_ram[dctv_out_ra[4:0]];
pre_first_out <= pre_first_out_w;
dv <= pre_dv;
// alternative option
......@@ -442,11 +380,10 @@ module dtt_iv_8x8_ad#(
4'he: out_wa[3:0] <= 4'h5 ^ {1'b0,{3{dstv}}};
4'hf: out_wa[3:0] <= 4'hb ^ {1'b0,{3{dstv}}};
endcase
// sub16 <= ~out_cntr[3] & out_cntr[0];
sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run;
inc16 <= out_cntr[3:0] == 'he;
out_we <= dctv_out_we[1];
start64 <= out_cntr[6:0] == 'h0d;
start64 <= start64_w;
end
always @ (posedge clk) begin
......@@ -628,7 +565,7 @@ module dtt_iv_8x8_ad#(
.pre2_start_out (), // pre2_start_outv[0]), // output reg
.en_out (dctv_en_out0), // output reg
.dst_out (pre2_dstv[0]), // output valid with en_out
.y_index (dctv_yindex0) // output[2:0] reg
.y_index () // dctv_yindex0) // output[2:0] reg
);
......@@ -662,7 +599,7 @@ module dtt_iv_8x8_ad#(
.pre2_start_out (), // pre2_start_outv[1]), // output reg
.en_out (dctv_en_out1), // output reg
.dst_out (pre2_dstv[1]), // output valid with en_out
.y_index (dctv_yindex1) // output[2:0] reg
.y_index () //dctv_yindex1) // output[2:0] reg
);
endmodule
......
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