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Commit a7abc965 authored by Andrey Filippov's avatar Andrey Filippov
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added interrupt status read

parent cd1e1c3d
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Showing with 54 additions and 18 deletions
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ a7abc965
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
VivadoBitstream_@_rawfile=x393_hispi
VivadoBitstream_@_rawfile=x393_parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ a7abc965
VivadoPlace_@_SkipSnapshotPlace=true
VivadoPlace_@_directive_place=Explore
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->VivadoPlace_@_directive_place<-@\#\#@->
eclipse.preferences.version=1
VERSION
View file @ a7abc965
......@@ -4,4 +4,4 @@
# a. 3
# b. 3.2 (preferred)
# c. 3.2.4
1.157
1.160
axi/mult_saxi_wr.v
View file @ a7abc965
......@@ -48,7 +48,8 @@ module mult_saxi_wr #(
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_POINTERS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_STATUS_REG = 'h3c, //status and IRQ requests and masks
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
parameter MULT_SAXI_BSLOG1 = 4,
......@@ -557,9 +558,15 @@ module mult_saxi_wr #(
reg [29:0] status_pntr2;
reg [29:0] status_pntr3;
wire pntr_we_mclk;
wire [128:0] status_data;
// wire [128:0] status_data;
wire [137:0] status_data;
reg status_tgl;
assign status_data = {2'b0, status_pntr3, 2'b0, status_pntr2, 2'b0, status_pntr1, 2'b0, status_pntr0, status_tgl};
assign status_data = {2'b0, status_pntr3,
2'b0, status_pntr2,
2'b0, status_pntr1,
2'b0, status_pntr0,
irq_m[3:0],irq_r[3:0],
1'b0, status_tgl};
always @ (posedge mclk) begin
if (!en_mclk) status_tgl <= 0;
else if (pntr_we_mclk) status_tgl <= ~status_tgl;
......@@ -573,18 +580,18 @@ module mult_saxi_wr #(
pulse_cross_clock status_wr_i (.rst(arst), .src_clk(aclk), .dst_clk(mclk), .in_pulse(pntr_we), .out_pulse(pntr_we_mclk),.busy());
status_generate #(
.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG+4), // not used
.PAYLOAD_BITS (0),
.STATUS_REG_ADDR (MULT_SAXI_STATUS_REG),
.PAYLOAD_BITS (10),
.REGISTER_STATUS (1),
.EXTRA_WORDS (4),
.EXTRA_REG_ADDR (MULT_SAXI_STATUS_REG)
.EXTRA_REG_ADDR (MULT_SAXI_POINTERS_REG)
) status_generate_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_STATUS)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[128:0]
.status (status_data), // input[137:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......
fpga_version.vh
View file @ a7abc965
......@@ -35,7 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
parameter FPGA_VERSION = 32'h039300a0; // parallel, else same as 9f 78.91%, not met by -0.032
// parameter FPGA_VERSION = 32'h0393009f; // hispi, adding IRQ status register (placemnt "explore") 81.36%, all met
// parameter FPGA_VERSION = 32'h0393009e; // hispi, adding IRQ status register 80.90%, timing failed by -0.218
// parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
// parameter FPGA_VERSION = 32'h0393009c; // parallel, adding IRQ from multi_saxi 79.31% , timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009a; // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
......
includes/x393_parameters.vh
View file @ a7abc965
......@@ -834,7 +834,8 @@
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_POINTERS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_STATUS_REG = 'h3c, //status and IRQ requests and masks
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
parameter MULT_SAXI_BSLOG1 = 4,
......
py393/vrlg.py
View file @ a7abc965
......@@ -411,6 +411,7 @@ FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
CMDFRAMESEQ_REL__TYPE = str
HISPI_DELAY_CLK0 = str
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
......@@ -678,6 +679,7 @@ MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_PS_EN_RST__TYPE = str
BUF_CLK1X_PCLK2X__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MULT_SAXI_POINTERS_REG__RAW = str
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LOGGER_MASK__RAW = str
......@@ -1555,7 +1557,7 @@ SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENSI2C_DRIVE = int
NUM_CYCLES_04__RAW = str
SENS_GAMMA_HEIGHT2__RAW = str
HISPI_DELAY_CLK0 = str
MULT_SAXI_POINTERS_REG__TYPE = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK3 = str
......@@ -1961,6 +1963,7 @@ CAMSYNC_EN_BIT__RAW = str
SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
MULT_SAXI_POINTERS_REG = int
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
SENSI2C_TBL_RAH = int
SENSI2C_ADDR_MASK__RAW = str
......
py393/x393_export_c.py
View file @ a7abc965
......@@ -598,6 +598,10 @@ class X393ExportC(object):
data = self._enc_mult_saxi_interrupts(),
name = "x393_mult_saxi_interrupts", typ="wo", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI interrupt status",
data = self._enc_mult_saxi_status(),
name = "x393_mult_saxi_status", typ="ro",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULTICLK reset/power down controls",
data = self._enc_multiclk_ctl(),
......@@ -1106,10 +1110,11 @@ class X393ExportC(object):
(("X393_MULT_SAXI_MODE", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_MODE, 0, None, "x393_mult_saxi_mode", "rw","MULT_SAXI mode register (per-channel enable and run bits)")),
(("X393_MULT_SAXI_STATUS_CTRL", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_STATUS, 0, None, "x393_status_ctrl", "rw","MULT_SAXI status control mode (status provides current DWORD pointers)")),
(("X393_MULT_SAXI_INTERRUPTS", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_IRQ, 0, None, "x393_mult_saxi_interrupts", "wo","MULT_SAXI per-channel interrupts control (each dibit:nop/reset/disable/enable)")),
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_IRQLEN", c, vrlg.MULT_SAXI_IRQLEN_ADDR, 1, z3, "x393_mult_saxi_irqlen", "wo","MULT_SAXI lower DWORD address bit to change to generate interrupt")),
(("X393_MULT_SAXI_STATUS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 1, z3, "x393_mult_saxi_al", "ro","MULT_SAXI current DWORD pointer"))]
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_IRQLEN", c, vrlg.MULT_SAXI_IRQLEN_ADDR, 1, z3, "x393_mult_saxi_irqlen", "wo","MULT_SAXI lower DWORD address bit to change to generate interrupt")),
(("X393_MULT_SAXI_POINTERS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_POINTERS_REG, 1, z3, "x393_mult_saxi_al", "ro","MULT_SAXI current DWORD pointer")),
(("X393_MULT_SAXI_STATUS", "", vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 0, None, "x393_mult_saxi_status", "ro","MULT_SAXI status with interrupt status"))]
#MULTI_CLK global clock generation PLLs
ba = 0
......@@ -2370,6 +2375,21 @@ class X393ExportC(object):
dw.append(("interrupt_cmd2", 4, 2, 0, "Channel 2 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd3", 6, 2, 0, "Channel 3 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
return dw
def _enc_mult_saxi_status(self):
dw=[]
dw.append(("irq_r0", 0, 1, 0, "Channel 0 interrupt request (not masked)"))
dw.append(("irq_r1", 1, 1, 0, "Channel 1 interrupt request (not masked)"))
dw.append(("irq_r2", 2, 1, 0, "Channel 2 interrupt request (not masked)"))
dw.append(("irq_r3", 3, 1, 0, "Channel 3 interrupt request (not masked)"))
dw.append(("irq_m0", 4, 1, 0, "Channel 0 interrupt enable"))
dw.append(("irq_m1", 5, 1, 0, "Channel 1 interrupt enable"))
dw.append(("irq_m2", 6, 1, 0, "Channel 2 interrupt enable"))
dw.append(("irq_m3", 7, 1, 0, "Channel 3 interrupt enable"))
dw.append(("tgl", 24, 1, 0, "toggles at any address change"))
dw.append(("seq_num", 26, 6, 0, "Status sequence number"))
return dw
def _enc_multiclk_ctl(self):
dw=[]
......
system_defines.vh
View file @ a7abc965
......@@ -63,7 +63,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
......
x393.v
View file @ a7abc965
......@@ -2329,6 +2329,7 @@ assign axi_grst = axi_rst_pre;
.MULT_SAXI_CNTRL_MODE (MULT_SAXI_CNTRL_MODE),
.MULT_SAXI_CNTRL_STATUS (MULT_SAXI_CNTRL_STATUS),
.MULT_SAXI_CNTRL_IRQ (MULT_SAXI_CNTRL_IRQ),
.MULT_SAXI_POINTERS_REG (MULT_SAXI_POINTERS_REG),
.MULT_SAXI_STATUS_REG (MULT_SAXI_STATUS_REG),
.MULT_SAXI_HALF_BRAM (MULT_SAXI_HALF_BRAM),
.MULT_SAXI_BSLOG0 (MULT_SAXI_BSLOG0),
......
x393_hispi.bit
View file @ a7abc965
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x393_parallel.bit
View file @ a7abc965
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