Working on a 256-cycle Bayer->FD converter

dsp/mclt16x16_bayer.v

@@ -245,22 +245,6 @@ module  mclt16x16_bayer#(
 
 
 
-    ram18p_var_w_var_r #(
-        .REGISTERS(1),
-        .LOG2WIDTH_WR(5),
-        .LOG2WIDTH_RD(5)
-    ) ram18p_var_w_var_r_dtt_in_i (
-        .rclk     (clk),          // input
-        .raddr    (dtt_r_ra),     // input[8:0] 
-        .ren      (dtt_r_re),     // input
-        .regen    (dtt_r_regen),  // input
-        .data_out (dtt_r_data_w), // output[35:0] 
-        .wclk     (clk),          // input
-        .waddr    (dtt_in_wa),    // input[8:0] 
-        .we       (dtt_we),       // input
-        .web      (4'hf),         // input[3:0] 
-        .data_in  ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] 
-    );
     wire [8:0] dbg_diff_wara_dtt_in = dtt_in_wa-dtt_r_ra; // SuppressThisWarning VEditor : debug only signal
     
     
@@ -367,6 +351,22 @@ module  mclt16x16_bayer#(
         .dtt_in_dv (dtt_we)        // output reg 
     );
     
+    ram18p_var_w_var_r #(
+        .REGISTERS(1),
+        .LOG2WIDTH_WR(5),
+        .LOG2WIDTH_RD(5)
+    ) ram18p_var_w_var_r_dtt_in_i (
+        .rclk     (clk),          // input
+        .raddr    (dtt_r_ra),     // input[8:0] 
+        .ren      (dtt_r_re),     // input
+        .regen    (dtt_r_regen),  // input
+        .data_out (dtt_r_data_w), // output[35:0] 
+        .wclk     (clk),          // input
+        .waddr    (dtt_in_wa),    // input[8:0] 
+        .we       (dtt_we),       // input
+        .web      (4'hf),         // input[3:0] 
+        .data_in  ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] 
+    );
    
     
     

mclt_test_04.sav

 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Wed Dec 27 05:08:10 2017
+[*] Thu Dec 28 00:31:10 2017
 [*]
-[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226172318550.fst"
-[dumpfile_mtime] "Wed Dec 27 00:23:21 2017"
-[dumpfile_size] 842624
+[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226220814551.fst"
+[dumpfile_mtime] "Wed Dec 27 05:08:17 2017"
+[dumpfile_size] 843036
 [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav"
-[timestart] 4875410
-[size] 1920 1171
-[pos] -1920 0
-*-14.216505 4955000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 0
+[size] 1824 1171
+[pos] 0 0
+*-21.266958 10681000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] mclt_test_04.
 [treeopen] mclt_test_04.mclt16x16_bayer_i.
 [treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.