Commit 74bffdd3 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Matched mclt16x16_bayer with more java data

parent 1db76b02

dsp/mclt16x16_bayer.v

+20 −8
Original line number Diff line number Diff line
@@ -99,10 +99,13 @@ module mclt16x16_bayer#( 
    reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt

    reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill

    reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill

    reg [SHIFT_WIDTH-1:0] x_shft_r5; // registered @ dtt_start_first_fill

    reg [SHIFT_WIDTH-1:0] y_shft_r5; // registered @ dtt_start_first_fill

    reg                   inv_checker_r;                

    reg                   inv_checker_r2;                

    reg                   inv_checker_r3;                

    reg                   inv_checker_r4;                

    reg                   inv_checker_r5;                



    wire                     [1:0] signs;        //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input

    wire                     [6:0] phases;        //!< other signals
@@ -157,7 +160,7 @@ module mclt16x16_bayer#( 
        end

        start_r <= {start_r[0], start};

        if (start_r[1]) begin      // same latency as mpix_a_w

            x_shft_r2 <=      x_shft_r; // use for the window 

            x_shft_r2 <=      x_shft_r;

            y_shft_r2 <=      y_shft_r;

            inv_checker_r2 <= inv_checker_r;

        end
@@ -174,6 +177,13 @@ module mclt16x16_bayer#( 
            inv_checker_r4 <= inv_checker_r3;

        end



        if (dtt_start_second_fill) begin 

            x_shft_r5 <= x_shft_r4; 

            y_shft_r5 <= y_shft_r4;

            inv_checker_r5 <= inv_checker_r4;

        end





//         if (!phases[14]) dtt_in_cntr <= 0; 

         if     (!dtt_we) dtt_in_cntr <= 0; 

         else             dtt_in_cntr <= dtt_in_cntr + 1;
@@ -374,7 +384,8 @@ module mclt16x16_bayer#( 
        .rst            (rst),              // input

        .start          (dtt_start),        // input

        .mode           ({dtt_mode, 1'b0}), // input[1:0] for checker-board: only 2 of 4 modes (CC, SC) 

        .xin            (dtt_r_data),       // input[24:0] signed 

//        .xin            (dtt_r_data),       // input[24:0] signed 

        .xin            ({dtt_r_data[DTT_IN_WIDTH-1],dtt_r_data[DTT_IN_WIDTH-1:1]}),       // input[24:0] signed 

        .pre_last_in    (),                 // output reg 

        .mode_out       (), // dtt_mode_out),     // output[1:0] reg 

        .pre_busy       (),                 // output reg
@@ -385,6 +396,7 @@ module mclt16x16_bayer#( 
        .inc16          (dtt_inc16),        // output reg 

        .start_out      (dtt_start_fill)    // output[24:0] signed

    );

    //[DTT_IN_WIDTH-1:0

    // still incorrectly shows difference when filled nto sequentially 

    reg  [8:0] dbg_last_dtt_out_ram_wa; // SuppressThisWarning VEditor : debug only signal

    wire [8:0] dbg_diff_wara_dtt_out0 = dbg_last_dtt_out_ram_wa-dtt_rd_ra0; // SuppressThisWarning VEditor : debug only signal
@@ -444,9 +456,9 @@ module mclt16x16_bayer#( 
        .rst           (rst),           // input

        .start         (dtt_start_out[1]), // input

        // are these shift OK? Will need to be valis only @ dtt_start_out

        .shift_h       (x_shft_r4),     // input[6:0] signed 

        .shift_v       (y_shft_r4),     // input[6:0] signed

        .inv_checker   (inv_checker_r4),// input only used for Bayer mosaic data 

        .shift_h       (x_shft_r5),     // input[6:0] signed 

        .shift_v       (y_shft_r5),     // input[6:0] signed

        .inv_checker   (inv_checker_r5),// input only used for Bayer mosaic data 

        .fd_din        (dtt_rd_data0),  // input[24:0] signed. Expected latency = 3 from start  

        .fd_out        (dout0),         // output[24:0] reg signed 

        .pre_first_out (pre_first_out), // output reg
@@ -466,9 +478,9 @@ module mclt16x16_bayer#( 
        .rst           (rst),           // input

        .start         (dtt_start_out[1]), // input

        // are these shift OK? Will need to be valis only @ dtt_start_out

        .shift_h       (x_shft_r4),     // input[6:0] signed 

        .shift_v       (y_shft_r4),     // input[6:0] signed

        .inv_checker   (inv_checker_r4),// input only used for Bayer mosaic data 

        .shift_h       (x_shft_r5),     // input[6:0] signed 

        .shift_v       (y_shft_r5),     // input[6:0] signed

        .inv_checker   (inv_checker_r5),// input only used for Bayer mosaic data 

        .fd_din        (dtt_rd_data1),  // input[24:0] signed. Expected latency = 3 from start  

        .fd_out        (dout1),         // output[24:0] reg signed 

        .pre_first_out (),              // output reg

dsp/mclt_test_04.tf

+57 −537

File changed.

Preview size limit exceeded, changes collapsed.

dsp/phase_rotator.v

+9 −4
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ module phase_rotator#( 
// 0xxxxxx (>0)       nnn    s     s    xxxxxx            nnn          0         0



    reg                     [5:0] start_d; // delayed versions of start (TODO: adjust length)  

    reg                     [7:0] cntr_h_consec; // input sample counter

    reg            [7-DECIMATE:0] cntr_h_consec; // input sample counter

    wire                    [7:0] cntr_h = DECIMATE ? {cntr_h_consec[6:2], ODD ? 1'b1: 1'b0, cntr_h_consec[1:0]}: cntr_h_consec;

    

    reg                           run_h;
@@ -121,7 +121,8 @@ module phase_rotator#( 
        

        if   (rst)                                               run_h <= 0;

        else if (start)                                          run_h <= 1;

        else if (&cntr_h_consec[6:0] && (cntr_h[7] || DECIMATE)) run_h <= 0;

//        else if (&cntr_h_consec[6:0] && (cntr_h[7] || DECIMATE)) run_h <= 0;

        else if (&cntr_h_consec)                                 run_h <= 0;

        

        if (!run_h) cntr_h_consec <= 0;

        else        cntr_h_consec <= cntr_h_consec + 1;
@@ -224,10 +225,15 @@ module phase_rotator#( 
        sela_1 <= ph[2] | ph[4]; sela_2 <= ph[3] | ph[5];

        selb_1 <= ph[2] | ph[5]; selb_2 <= ph[3] | ph[6];

        // 0 1 0 0

        /*

        negm_1 <= ((ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3])) ^ 

                  (inv_checker_r2 & (ph[4] | ph[6]));  // invert negation when using Bayer patterns

        negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^

                  (inv_checker_r2 & (ph[5] | ph[7]));  // invert negation when using Bayer patterns

        */

        negm_1 <= (ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3]); 

        negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^ inv_checker_r2;

//                  (inv_checker_r2 & (|ph[7:4]));  // invert negation when using Bayer patterns

        

        

        accum_1 <= ph[4] | ph[6]; accum_2 <= ph[5] | ph[7];
@@ -241,7 +247,6 @@ module phase_rotator#( 
//inv_checker_r2

        negm_3 <= (ph[10] & ~sign_cs[2]) | (ph[11] & sign_cs[3]);

        negm_4 <= (ph[11] & ~sign_cs[3]) | (ph[12] & sign_cs[4]);

        ;



        accum_3 <= ph[10] | ph[12]; accum_4 <= ph[11] | ph[13];
@@ -249,7 +254,7 @@ module phase_rotator#( 
        fd_dv <= pre_dv;

        if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH];

        

        pre_first_out <= cntr_h_consec[7:0] == 8'hd;

        pre_first_out <= cntr_h_consec == 8'hd;

        

    end

input_data/mclt_dtt_all_00_x1489_y951.dat

+261 −262

File changed.

Preview size limit exceeded, changes collapsed.

mclt_test_04.sav

+163 −39
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI

[*] Tue Dec 26 08:22:23 2017

[*] Wed Dec 27 05:08:10 2017

[*]

[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226012033452.fst"

[dumpfile_mtime] "Tue Dec 26 08:20:36 2017"

[dumpfile_size] 856099

[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226172318550.fst"

[dumpfile_mtime] "Wed Dec 27 00:23:21 2017"

[dumpfile_size] 842624

[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav"

[timestart] 0

[size] 1824 1171

[pos] 0 0

*-21.178318 3655000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[timestart] 4875410

[size] 1920 1171

[pos] -1920 0

*-14.216505 4955000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] mclt_test_04.

[treeopen] mclt_test_04.mclt16x16_bayer_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.
@@ -19,9 +20,10 @@ 
[treeopen] mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.

[treeopen] mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.

[sst_width] 233

[signals_width] 408

[sst_width] 262

[signals_width] 356

[sst_expanded] 1

[sst_vpaned_height] 343

@800200
@@ -177,10 +179,98 @@ mclt_test_04.diff61 
@8420

mclt_test_04.diff60

mclt_test_04.diff61

@420

mclt_test_04.n7

mclt_test_04.cntr7

@22

mclt_test_04.mclt16x16_bayer_i.dout0[24:0]

mclt_test_04.mclt16x16_bayer_i.dout1[24:0]

mclt_test_04.java_data_dtt_rot0[24:0]

mclt_test_04.java_data_dtt_rot1[24:0]

@8420

mclt_test_04.diff70

mclt_test_04.diff71

@200

-

@28

mclt_test_04.dv

@22

mclt_test_04.dout0[24:0]

mclt_test_04.dout1[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]

@800200

-mclt16x16_bayer

@c00200

-dtt_iv_8x8_ad

@28

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start

@22

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.xin[24:0]

@c00022

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

@28

(0)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

(1)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

(2)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

(3)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

(4)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

(5)mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]

@1401200

-group_end

@28

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0h

@22

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0[2:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1h

@22

[color] 2

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1[2:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin0[24:0]

[color] 2

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin1[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout0[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout1[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_di[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_wa[7:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_we[1:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_start

@22

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_run[2:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_ra[7:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout0[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout1[24:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start_out

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_we

@22

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wa[3:0]

mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]

@200

-

@1401200

-dtt_iv_8x8_ad

@22

mclt_test_04.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra1[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_data0[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_data1[24:0]

[color] 2

mclt_test_04.mclt16x16_bayer_i.dbg_dtt_rd_data0[24:0]

[color] 2

mclt_test_04.mclt16x16_bayer_i.dbg_dtt_rd_data1[24:0]

@200

-

@22

mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_out_we

@22

mclt_test_04.mclt16x16_bayer_i.dtt_out_wd[24:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_start_fill

mclt_test_04.mclt16x16_bayer_i.dtt_first_quad_out
@@ -198,14 +288,11 @@ mclt_test_04.mclt16x16_bayer_i.dtt_start_out[1:0] 
@22

mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]

mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]

@8023

@8022

mclt_test_04.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]

@20000

-

@22

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra1[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_regen_dv[3:0]

@8022

mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@@ -344,19 +431,6 @@ mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0] 
-

@1000200

-mclt16x16_bayer

@c00200

-mclt_test_04.java_sgn_w

@1401200

-group_end

@c00200

-mclt_test_04.cntr4

@1401200

-group_end

@c00200

-mclt_test_04.mclt16x16_i.dtt_rd_cntr

@1401200

-group_end

@1000200

-top

@800200

-mclt_bayer
@@ -382,12 +456,6 @@ mclt_test_04.mclt16x16_bayer_i.dbg_dout0[24:0] 
[color] 7

mclt_test_04.mclt16x16_bayer_i.dbg_dout1[24:0]

@22

mclt_test_04.mclt16x16_bayer_i.dtt_rd_data0[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_data1[24:0]

[color] 2

mclt_test_04.mclt16x16_bayer_i.dbg_dtt_rd_data0[24:0]

[color] 2

mclt_test_04.mclt16x16_bayer_i.dbg_dtt_rd_data1[24:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra1[8:0]

mclt_test_04.mclt16x16_bayer_i.dtt_r_data[24:0]
@@ -414,6 +482,25 @@ mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] 
-top

@200

-

@22

mclt_test_04.mclt16x16_bayer_i.x_shft[6:0]

@28

mclt_test_04.mclt16x16_bayer_i.start

@22

mclt_test_04.mclt16x16_bayer_i.x_shft_r[6:0]

@28

(0)mclt_test_04.mclt16x16_bayer_i.start_r[1:0]

@22

mclt_test_04.mclt16x16_bayer_i.x_shft_r2[6:0]

@28

mclt_test_04.mclt16x16_bayer_i.start_dtt

@22

mclt_test_04.mclt16x16_bayer_i.x_shft_r3[6:0]

@28

mclt_test_04.mclt16x16_bayer_i.dtt_start_first_fill

mclt_test_04.mclt16x16_bayer_i.dtt_start_second_fill

@22

mclt_test_04.mclt16x16_bayer_i.x_shft_r4[6:0]

@800200

-rotator0

@28
@@ -447,12 +534,54 @@ mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0] 
mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.negm_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.negm_2

@22

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cntr_h_consec[6:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cntr_h[7:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cntr_v[7:0]

@28

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.pre_dv

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.pre_first_out

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cea1_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cea1_2

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cea2_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cea2_2

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.sela_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.negm_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.negm_2

(14)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

(13)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

(12)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

(11)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

(10)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

(9)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2

(2)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]

(1)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]

(0)mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]

@22

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]

@28

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ceb1_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.ceb2_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.selb_1

@800200

-dsp1

@28

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA1

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA2

@22

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg1[29:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg2[29:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qad_o_reg1[24:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0]

@23

mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0]

@200

-

@1000200

-dsp1

-rotator0

@800200

-rotator1
@@ -486,6 +615,7 @@ mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.sign_cs[4:0] 
mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.negm_1

mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.negm_2

@22

mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.cntr_h_consec[6:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.cntr_h[7:0]

mclt_test_04.mclt16x16_bayer_i.phase_rotator1_i.cntr_v[7:0]

@28
@@ -808,11 +938,5 @@ mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0] 
-group_end

@1000200

-mclt_bayer

@800200

-mono

@200

-

@1000200

-mono

[pattern_trace] 1

[pattern_trace] 0