Commit a5e4cd6e authored by Andrey Filippov's avatar Andrey Filippov

Working on a 256-cycle Bayer->FD converter

parent 74bffdd3
......@@ -245,22 +245,6 @@ module mclt16x16_bayer#(
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_in_i (
.rclk (clk), // input
.raddr (dtt_r_ra), // input[8:0]
.ren (dtt_r_re), // input
.regen (dtt_r_regen), // input
.data_out (dtt_r_data_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_in_wa), // input[8:0]
.we (dtt_we), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
);
wire [8:0] dbg_diff_wara_dtt_in = dtt_in_wa-dtt_r_ra; // SuppressThisWarning VEditor : debug only signal
......@@ -367,6 +351,22 @@ module mclt16x16_bayer#(
.dtt_in_dv (dtt_we) // output reg
);
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_in_i (
.rclk (clk), // input
.raddr (dtt_r_ra), // input[8:0]
.ren (dtt_r_re), // input
.regen (dtt_r_regen), // input
.data_out (dtt_r_data_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_in_wa), // input[8:0]
.we (dtt_we), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
);
......
/*!
* <b>Module:</b> mclt16x16_bayer3
* @file mclt16x16_bayer3.v
* @date 2017-12-21
* @author eyesis
*
* @brief Generate addresses and windows to fold MCLT Bayer data
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* mclt16x16_bayer3.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt16x16_bayer3.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module mclt16x16_bayer3#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency (may increase to 4 for gamma)
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18, // input pixel width (unsigned)
parameter OUT_WIDTH = 25, // bits in dtt output
parameter DTT_IN_WIDTH = 25, // bits in DTT input
parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< start convertion of the next 256 samples
input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
input [1:0] color_wa, //!< color index to apply parameters to (0 - R, 1 - B, 2 - G)
input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
input [7:0] top_left, //!< index of the 16x16 top left corner
// input [1:0] valid_rows, //!< 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
input valid_odd, //!< For R and B: 0 - even rows (0,2...) valid, 1 - odd rows valid, green - N/A
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X fractional shift (valid @ start)
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y fractional shift (valid @ start)
input set_inv_checker, //!< 0 write inv_checker for the color selected by color_wa
input set_top_left, //!< 0 write top_left for the color selected by color_wa
input set_valid_odd, //!< 0 write top_left for the color selected by color_wa
input set_x_shft, //!< 0 write top_left for the color selected by color_wa
input set_y_shft, //!< 0 write top_left for the color selected by color_wa
output [PIX_ADDR_WIDTH-1:0] pix_addr, //!< external pixel buffer address
output pix_re, //!< pixel read enable (sync with mpixel_a)
output pix_page, //!< copy pixel page (should be externally combined with first color)
input [PIXEL_WIDTH-1:0] pix_d, //!< pixel data, latency = 2 from pixel address
output pre_busy, //!< start should come each 256-th cycle (next after pre_last_in), and not after pre_busy)
output pre_last_in, //!< may increment page
output pre_first_out,//!< next will output first of DCT/DCT coefficients
output pre_last_out, //!< next will be last output of DST/DST coefficients
output [7:0] out_addr, //!< address to save coefficients, 2 MSBs - mode (CC,SC,CS,SS), others - down first
output dv, //!< output data valid
output signed [OUT_WIDTH - 1 : 0] dout_r, //!<frequency domain data output for red color components
output signed [OUT_WIDTH - 1 : 0] dout_b, //!<frequency domain data output for blue color components
output signed [OUT_WIDTH - 1 : 0] dout_g //!<frequency domain data output for green color components
);
// When defined, use 2 DSP multipleierts
// `define DSP_ACCUM_FOLD 1
localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1
reg [7:0] in_cntr; //
reg run_r;
// general timing
always @(posedge clk) begin
if (rst) run_r <= 0;
else if (start) run_r <= 1;
else if (&in_cntr) run_r <= 0;
if (!run_r) in_cntr <= 0;
else in_cntr <= in_cntr + 1;
end
// register files - should be valid for 3 cycles after start (while being copied)
reg inv_checker_rf_ram[0:3]; //
reg [7:0] top_left_rf_ram[0:3]; //
reg valid_odd_rf_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] x_shft_rf_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] y_shft_rf_ram[0:3]; //
reg inv_checker_rf_ram_reg; //
reg [7:0] top_left_rf_ram_reg; //
reg valid_odd_rf_ram_reg; //
reg [SHIFT_WIDTH-1:0] x_shft_rf_ram_reg; //
reg [SHIFT_WIDTH-1:0] y_shft_rf_ram_reg; //
reg [1:0] copy_regs;
// internal per-color registers
reg inv_checker_ram[0:3]; //
reg [7:0] top_left_ram[0:3]; //
reg valid_odd_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] x_shft_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] y_shft_ram[0:3]; //
reg reg_rot_page; // odd/even register sets for long latency (rotator)
reg [1:0] regs_wa;
reg inv_checker_rot_ram[0:7]; //
reg valid_odd_rot_ram[0:7]; //
reg [SHIFT_WIDTH-1:0] x_shft_rot_ram[0:7]; //
reg [SHIFT_WIDTH-1:0] y_shft_rot_ram[0:7]; //
reg [1:0] start_block_r; // 0 - read regs, 1 - start fold
reg inv_checker_ram_reg; //
reg [7:0] top_left_ram_reg; //
reg valid_odd_ram_reg; //
reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; //
reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; //
// todo: add registers to read into rotators
always @(posedge clk) begin
if (set_inv_checker) inv_checker_rf_ram[color_wa] <= inv_checker;
if (set_top_left) top_left_rf_ram [color_wa] <= top_left;
if (set_valid_odd) valid_odd_rf_ram [color_wa] <= valid_odd;
if (set_x_shft) x_shft_rf_ram [color_wa] <= x_shft;
if (set_y_shft) y_shft_rf_ram [color_wa] <= y_shft;
copy_regs <= {copy_regs[0], start | (run_r && (in_cntr[7:1]==0))?1'b1:1'b0};
if (copy_regs[0]) begin
regs_wa <= in_cntr[1:0];
inv_checker_rf_ram_reg <= inv_checker_rf_ram[in_cntr[1:0]];
top_left_rf_ram_reg <= top_left_rf_ram[in_cntr[1:0]];
valid_odd_rf_ram_reg <= valid_odd_rf_ram[in_cntr[1:0]];
x_shft_rf_ram_reg <= x_shft_rf_ram[in_cntr[1:0]];
y_shft_rf_ram_reg <= y_shft_rf_ram[in_cntr[1:0]];
end
if (rst) reg_rot_page <= 1;
else if (start) reg_rot_page <= ~reg_rot_page;
if (copy_regs[1]) begin
inv_checker_ram[regs_wa] <= inv_checker_rf_ram_reg;
top_left_ram[regs_wa] <= top_left_rf_ram_reg;
valid_odd_ram[regs_wa] <= valid_odd_rf_ram_reg;
x_shft_ram[regs_wa] <= x_shft_rf_ram_reg;
y_shft_ram[regs_wa] <= y_shft_rf_ram_reg;
inv_checker_rot_ram[{reg_rot_page,regs_wa}] <= inv_checker_rf_ram_reg;
valid_odd_rot_ram[{reg_rot_page,regs_wa}] <= valid_odd_rf_ram_reg;
x_shft_rot_ram[{reg_rot_page,regs_wa}] <= x_shft_rf_ram_reg;
y_shft_rot_ram[{reg_rot_page,regs_wa}] <= y_shft_rf_ram_reg;
end
start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0};
if (start_block_r[0]) begin
inv_checker_ram_reg <= inv_checker_ram[in_cntr[7:6]];
top_left_ram_reg <= top_left_ram[in_cntr[7:6]];
valid_odd_ram_reg <= valid_odd_ram[in_cntr[7:6]];
x_shft_ram_reg <= x_shft_ram[in_cntr[7:6]];
y_shft_ram_reg <= y_shft_ram[in_cntr[7:6]];
end
end
`ifdef DSP_ACCUM_FOLD
localparam ADDR_DLYL = 4 - EXT_PIX_LATENCY; // 4'h2; // 3 for mpy, 2 - for dsp
`else
localparam ADDR_DLYL = 5 - EXT_PIX_LATENCY; // 4'h3; // 3 for mpy, 2 - for dsp
`endif
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
wire [6:0] phases; //!< other signals
wire signed [WND_WIDTH-1:0] window_w;
wire var_pre2_first; //
wire pre_last_in_w;
wire green_late;
wire signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg dtt_we;
wire dtt_prewe;
reg [7:0] dtt_in_precntr; //
// reg dtt_in_page;
reg [8:0] dtt_in_wa;
// assign pre_last_out = pre_last_out_r;
// assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]);
assign pre_last_in = pre_last_in_w;
mclt_bayer_fold_rgb #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.ADDR_DLY (ADDR_DLYL), // 3 for mpy, 2 - for dsp
.COORD_WIDTH (COORD_WIDTH),
.WND_WIDTH (WND_WIDTH)
) mclt_bayer_fold_rgb_i (
.clk (clk), // input
.rst (rst), // input
.start (start_block_r[1]), // input
.tile_size (tile_size), // input[1:0]
.inv_checker (inv_checker_ram_reg), // input
.top_left (top_left_ram_reg), // input[7:0]
.green (in_cntr[7]), // input
.valid_odd (valid_odd_ram_reg), // input[1:0]
.x_shft (x_shft_ram_reg), // input[6:0]
.y_shft (y_shft_ram_reg), // input[6:0]
.pix_addr (pix_addr), // output[8:0]
.pix_re (pix_re), // output
.pix_page (pix_page), // output
.window (window_w), // output[17:0] signed
.signs (signs), // output[1:0]
.phases (phases), // output[7:0]
// make it always 0 or 1 for R/B, then if use only not-in-series, use D -input for twice value
.var_pre2_first(var_pre2_first), // output
.pre_last_in (pre_last_in_w),// output reg
.green_late (green_late) // output reg
);
mclt_baeyer_fold_accum_rgb #(
.PIXEL_WIDTH(PIXEL_WIDTH),
.WND_WIDTH(WND_WIDTH),
.DTT_IN_WIDTH(DTT_IN_WIDTH),
.DSP_B_WIDTH(DSP_B_WIDTH),
.DSP_A_WIDTH(DSP_A_WIDTH),
.DSP_P_WIDTH(DSP_P_WIDTH)
) mclt_baeyer_fold_accum_rgb_i (
.clk (clk), // input
.rst (rst), // input
.pre_phase (phases[6]), // input
.green (green_late), //input // valid with pix_d
.pix_d (pix_d), // input[15:0] signed
.pix_sgn (signs), // input[1:0]
.window (window_w), // input[17:0] signed
.var_pre2_first (var_pre2_first), // input
.dtt_in (data_dtt_in), // output[24:0] signed
.dtt_in_predv (dtt_prewe), // output reg
.dtt_in_dv () // output reg
);
always @ (posedge clk) begin
if (!dtt_prewe) dtt_in_precntr <= 0;
else dtt_in_precntr <= dtt_in_precntr + 1;
dtt_in_wa <= {1'b0, dtt_in_precntr[7],
dtt_in_precntr[7]?
{dtt_in_precntr[0], dtt_in_precntr[6:1]}:
dtt_in_precntr[6:0]};
dtt_we<=dtt_prewe;
end
// reading/converting DTT
reg start_dtt; // = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256
// reg [6:0] dtt_r_cntr; //
reg [7:0] dtt_r_cntr; //
// reg dtt_r_page;
reg dtt_r_re;
reg dtt_r_regen;
reg dtt_start;
// wire dtt_mode = dtt_r_cntr[6]; // TODO: or reverse?
wire dtt_mode = dtt_r_cntr[7] & dtt_r_cntr[6]; // (second of green only)
// wire [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};
wire [8:0] dtt_r_ra = {1'b0, dtt_r_cntr};
wire signed [35:0] dtt_r_data_w; // high bits are not used
wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0];
wire [8:0] dbg_dtt_in_rawa = dtt_in_wa-dtt_r_ra; // SuppressThisWarning VEditor : debug only signal
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_in_i (
.rclk (clk), // input
.raddr (dtt_r_ra), // input[8:0]
.ren (dtt_r_re), // input
.regen (dtt_r_regen), // input
.data_out (dtt_r_data_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_in_wa), // input[8:0]
.we (dtt_we), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
);
wire signed [OUT_WIDTH-1:0] dtt_out_wd;
wire [3:0] dtt_out_wa16;
wire dtt_out_we;
wire dtt_sub16;
wire dtt_inc16;
reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah;
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill;
reg dtt_start_second_fill;
reg [1:0] dtt_start_out; // start read out to sin/cos rotator
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
wire [8:0] dtt_out_ram_wa_rb = {2'b0,dtt_out_ram_wa[8],dtt_out_ram_wa[5:0]};
wire [8:0] dtt_out_ram_wa_g = {1'b0,dtt_out_ram_wa[8],dtt_out_ram_wa[6:0]};
wire dtt_out_we_r = dtt_out_we & ~dtt_out_ram_wa[7] & ~dtt_out_ram_wa[6];
wire dtt_out_we_b = dtt_out_we & ~dtt_out_ram_wa[7] & dtt_out_ram_wa[6];
wire dtt_out_we_g = dtt_out_we & dtt_out_ram_wa[7];
reg [7:0] dtt_dly_cntr;
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
reg [8:0] dtt_rd_ra0;
reg [8:0] dtt_rd_ra1;
reg [3:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
wire [35:0] dtt_rd_data_r_w; // high bits are not used
wire [35:0] dtt_rd_data_b_w; // high bits are not used
wire [35:0] dtt_rd_data_g_w; // high bits are not used
// data to be input to phase rotator
wire signed [OUT_WIDTH-1:0] dtt_rd_data_r = dtt_rd_data_r_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data_b = dtt_rd_data_b_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data_g = dtt_rd_data_g_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
always @ (posedge clk) begin
// reading memory and running DTT
start_dtt <= dtt_in_precntr == DTT_IN_DELAY;
// if (start_dtt) dtt_r_page <= dtt_in_wa[7];// dtt_in_page;
if (rst) dtt_r_re <= 1'b0;
else if (start_dtt) dtt_r_re <= 1'b1;
else if (&dtt_r_cntr) dtt_r_re <= 1'b0;
dtt_r_regen <= dtt_r_re;
if (!dtt_r_re) dtt_r_cntr <= 0;
else dtt_r_cntr <= dtt_r_cntr + 1;
dtt_start <= (dtt_r_cntr[5:0] == 0) && dtt_r_re;
end
dtt_iv_8x8_ad #(
.INPUT_WIDTH (DTT_IN_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH)
) dtt_iv_8x8_ad_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start), // input
.mode ({dtt_mode, 1'b0}), // input[1:0] for checker-board: only 2 of 4 modes (CC, SC)
// .xin (dtt_r_data), // input[24:0] signed
.xin ({dtt_r_data[DTT_IN_WIDTH-1],dtt_r_data[DTT_IN_WIDTH-1:1]}), // input[24:0] signed
.pre_last_in (), // output reg
.mode_out (), // dtt_mode_out), // output[1:0] reg
.pre_busy (), // output reg
.out_wd (dtt_out_wd), // output[24:0] reg
.out_wa (dtt_out_wa16), // output[3:0] reg
.out_we (dtt_out_we), // output reg
.sub16 (dtt_sub16), // output reg
.inc16 (dtt_inc16), // output reg
.start_out (dtt_start_fill) // output[24:0] signed
);
always @(posedge clk) begin
if (rst) dtt_out_ram_cntr <= 0;
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out;
if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
if (dtt_start_second_fill) dtt_out_ram_wpage2 <= dtt_out_ram_wpage;
if (rst) dtt_dly_cntr <= 0;
else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0};
if (rst) dtt_rd_regen_dv[0] <= 0;
else if (dtt_start_out[0]) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
// if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage2, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
dtt_rd_cntr_pre[0]};
dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
~dtt_rd_cntr_pre[0]};
end
// Three of 2 page buffers after dtt (feeding two phase rotators), address MSB is not needed
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_r_i (
.rclk (clk), // input
.raddr (dtt_rd_ra0), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input
.regen (dtt_rd_regen_dv[2]), // input
.data_out (dtt_rd_data_r_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_out_ram_wa_rb), // input[8:0]
.we (dtt_out_we_r), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, dtt_out_wd}) // input[35:0]
);
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_b_i (
.rclk (clk), // input
.raddr (dtt_rd_ra1), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input
.regen (dtt_rd_regen_dv[2]), // input
.data_out (dtt_rd_data_b_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_out_ram_wa_rb), // input[8:0]
.we (dtt_out_we_b), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, dtt_out_wd}) // input[35:0]
);
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_g_i (
.rclk (clk), // input
.raddr (dtt_rd_ra1), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input
.regen (dtt_rd_regen_dv[2]), // input
.data_out (dtt_rd_data_g_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_out_ram_wa_g), // input[8:0]
.we (dtt_out_we_g), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, dtt_out_wd}) // input[35:0]
);
endmodule
/*!
* <b>Module:</b> mclt_baeyer_fold_accum_rgb
* @file mclt_baeyer_fold_accum_rgb.v
* @date 2017-12-23
* @author eyesis
*
* @brief Alternative implementation of CC and CS folded data accumulators
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* mclt_baeyer_fold_accum_rgb.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt_baeyer_fold_accum_rgb.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`define DSP_ACCUM_FOLD 1
module mclt_baeyer_fold_accum_rgb # (
parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18, // input pixel width (unsigned)
parameter DTT_IN_WIDTH = 25, // bits in DTT input
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM // SuppressThisWarning VEditor - not always used
parameter DSP_A_WIDTH = 25, // SuppressThisWarning VEditor - not always used
parameter DSP_P_WIDTH = 48 // SuppressThisWarning VEditor - not always used
)(
input clk,
input rst,
input pre_phase,
input green, //!<valid with pix_d
input signed [PIXEL_WIDTH-1:0] pix_d, //!< pixel data (should be 1 cycle later for `undef DSP_ACCUM_FOLD
input [1:0] pix_sgn, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
input signed [WND_WIDTH-1:0] window,
input var_pre2_first,
output signed [DTT_IN_WIDTH-1:0] dtt_in,
output dtt_in_predv,
output dtt_in_dv
);
reg var_pre_first;
reg var_first;
reg var_last;
reg [6:0] phases;
reg [4:0] green_r;
always @ (posedge clk) begin
phases <= {phases[5:0], pre_phase};
if (phases[2]) begin
var_pre_first <= var_pre2_first;
end
if (phases[3]) begin
var_first <= var_pre_first;
end
var_last <= (var_first & phases[4]) & green_r[3] ;
green_r <= {green_r[3:0], green};
end
`ifdef DSP_ACCUM_FOLD
reg signed [PIXEL_WIDTH-1:0] pix_d_r;
reg dtt_in_dv_dsp_r;
reg dtt_in_predv_dsp_r;
reg signed [DTT_IN_WIDTH-1:0] dtt_in_dsp;
assign dtt_in = dtt_in_dsp;
assign dtt_in_dv = dtt_in_dv_dsp_r;
assign dtt_in_predv = dtt_in_predv_dsp_r;
always @ (posedge clk) begin
if (rst) dtt_in_dv_dsp_r <= 0;
else dtt_in_dv_dsp_r <= phases[5];
end
always @ (posedge clk) begin
if (rst) dtt_in_predv_dsp_r <= 0;
else dtt_in_predv_dsp_r <= phases[4];
end
reg [1:0] ced2;
wire neg_m1, neg_m2, en_a2;
wire accum1= !var_pre2_first;
wire accum2= !var_pre_first && green_r[2];
wire [DSP_P_WIDTH-1:0] pout1;
wire [DSP_P_WIDTH-1:0] pout2;
wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ?
pout1 [PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH] :
pout2 [PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH])
`ifdef ROUND
+ (var_last ?
pout1 [PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -1] :
pout2 [PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -1)
`endif
;
// wire signed [DTT_IN_WIDTH-2:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 1]
always @ (posedge clk) begin
if (phases[5]) dtt_in_dsp <= dtt_in_dsp_w;
ced2 <= {ced2[0], pre_phase & ~green};
if (ced2[0]) pix_d_r <= pix_d;
end
dsp_ma_preadd #(
.B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH),
.AREG(1),
.BREG(1)
) dsp_fold_cc_i (
.clk (clk), // input
.rst (rst), // input
.bin (window), // input[17:0] signed
.ceb1 (1'b0), // input
.ceb2 (phases[1]), // input
.selb (1'b1), // input
.ain ({{(DSP_A_WIDTH-PIXEL_WIDTH){pix_d[PIXEL_WIDTH-1]}},pix_d}), // input[24:0] signed
.cea1 (1'b0), // input
.cea2 (phases[0]), // input
.din (25'b0), // input[24:0] signed
.ced (1'b0), // input
.cead (phases[1]), // input
.sela (1'b1), // input
.en_a (1'b1), // input
.en_d (1'b0), // input
.sub_a (1'b0), // input
.neg_m (neg_m1), // input
.accum (accum1), // input
.pout (pout1) // output[47:0] signed
);
dsp_ma_preadd #(
.B_WIDTH(DSP_B_WIDTH),
.A_WIDTH(DSP_A_WIDTH),
.P_WIDTH(DSP_P_WIDTH),
.AREG(2), // delayed by 1
.BREG(2)
) dsp_fold_cs_i (
.clk (clk), // input
.rst (rst), // input
.bin (window), // input[17:0] signed
.ceb1 (phases[1]), // input
.ceb2 (phases[2]), // input
.selb (1'b1), // input
.ain ({{(DSP_A_WIDTH-PIXEL_WIDTH){pix_d[PIXEL_WIDTH-1]}},pix_d}), // input[24:0] signed
.cea1 (phases[0]), // input
.cea2 (phases[1]), // input
// twice ain
.din ({{(DSP_A_WIDTH-PIXEL_WIDTH-1){pix_d_r[PIXEL_WIDTH-1]}},pix_d_r,1'b0}), // input[24:0] signed
.ced (ced2[1]), // input
.cead (phases[2]), // input
.sela (1'b1), // input
.en_a (en_a2), // input
.en_d (~en_a2), // input
.sub_a (1'b0), // input
.neg_m (neg_m2), // input
.accum (accum2), // input
.pout (pout2) // output[47:0] signed
);
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_neg_m1_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h0), // input[3:0]
.din (pix_sgn[0]), // input[0:0]
.dout (neg_m1) // output[0:0]
);
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_neg_m2_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h1), // input[3:0]
// .din (pix_sgn[1]), // input[0:0]
.din (green_r[0]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
.dout (neg_m2) // output[0:0]
);
//1'b0
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_en_d2_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h1), // input[3:0]
.din (green), // input[0:0]
.dout (en_a2) // output[0:0]
);
`else
wire [ 1:0] pix_sgn_d;
/// reg [PIXEL_WIDTH-1:0] pix_dr; // only for mpy to match dsp
reg signed [WND_WIDTH-1:0] window_r;
reg signed [PIXEL_WIDTH:0] pix_d_r; // registered pixel data (to be absorbed by MPY)
reg [ 1:0] pix_sgn_r;
reg signed [PIXEL_WIDTH + WND_WIDTH - 0:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
reg signed [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
// rounding
// wire signed [DTT_IN_WIDTH-3:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]
// wire signed [DTT_IN_WIDTH-2:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 1]
wire signed [DTT_IN_WIDTH-1:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH - 0]
`ifdef ROUND
// + pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH]
// + pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -1]
+ pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH -2]
`endif
;
reg signed [DTT_IN_WIDTH-1:0] data_cc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r2; // data_sc_r delayed by 1 cycle
reg mode_mux;
reg dtt_in_dv_r;
reg dtt_in_predv_r;
reg signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
assign dtt_in = data_dtt_in;
assign dtt_in_dv = dtt_in_dv_r;
assign dtt_in_predv = dtt_in_predv_r;
always @ (posedge clk) begin
if (rst) dtt_in_dv_r <= 0;
else dtt_in_dv_r <= phases[5];
if (rst) dtt_in_predv_r <= 0;
else dtt_in_predv_r <= phases[6];
if (phases[1]) begin
pix_d_r <= green_r[0]? {pix_d[PIXEL_WIDTH-1],pix_d}:{pix_d,1'b0};
window_r <= window;
end
if (phases[2]) pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra
if (phases[3]) begin
// pix_wnd_r2 <= green_r[2]?
// {pix_wnd_r2_w[DTT_IN_WIDTH-2],pix_wnd_r2_w}:
// { pix_wnd_r2_w,1'b0};
// pix_wnd_r2 <= {pix_wnd_r2_w[DTT_IN_WIDTH-2],pix_wnd_r2_w};
pix_wnd_r2 <= pix_wnd_r2_w;
pix_sgn_r <= green_r[2]? pix_sgn_d : {pix_sgn_d[0],pix_sgn_d[0]};
end
if (phases[4]) begin
data_cc_r <= ((var_first || !green_r[3]) ?
{DTT_IN_WIDTH{1'b0}} :
data_cc_r) +
(pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r <= ((var_first || !green_r[3]) ? // will be used for R & B
{DTT_IN_WIDTH{1'b0}} :
data_sc_r) +
(pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r2 <= data_sc_r;
end
if (phases[5]) data_sc_r2 <= data_sc_r;
if (!green_r[4]) mode_mux <= 1;
else if (var_last) mode_mux <= 0;
else if (phases[6]) mode_mux <= mode_mux + 1;
if (phases[6]) case (mode_mux)
1'b0: data_dtt_in <= data_cc_r;
1'b1: data_dtt_in <= data_sc_r2;
endcase
end
dly_var #(
.WIDTH(2),
.DLY_WIDTH(4)
) dly_pix_sgn_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h1), // input[3:0]
.din (pix_sgn), // input[0:0]
.dout (pix_sgn_d) // output[0:0]
);
`endif
endmodule
/*!
* <b>Module:</b> mclt_bayer_fold_rgb
* @file mclt_bayer_fold_rgb.v
* @date 2017-12-21
* @author eyesis
*
* @brief Generate addresses and windows to fold MCLT Bayer data
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* mclt_bayer_fold_rgb.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt_bayer_fold_rgb.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module mclt_bayer_fold_rgb#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
parameter ADDR_DLY = 4'h3, // extra delay of pixel address to match window delay
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter WND_WIDTH = 18 // input pixel width (unsigned)
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< start convertion of the next 256 samples
input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
input [7:0] top_left, //!< index of the 16x16 top left corner
input green, //!< 0 - R or B, 1 - G
input valid_odd, //!< 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X fractional shift (valid @ start)
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y fractional shift (valid @ start)
output [PIX_ADDR_WIDTH-1:0] pix_addr, //!< external pixel buffer address
output pix_re, //!< pixel read enable (sync with mpixel_a)
output pix_page, //!< copy pixel page (should be externally combined with first color)
output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive
output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
output [6:0] phases, //!< other signals
output var_pre2_first,//!< two ahead of first of 2 fold variants (4 for monochrome, 2 left for checker)
output pre_last_in, //!< pre last data in
output reg green_late //!< delayed green to be fed to the accummulator
);
reg [6:0] in_cntr; // input phase counter
reg [6:0] run_r; // run phase
// reg stop_r;
reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
reg [7:0] top_left_r0; // index of the 16x16 top left corner
reg [7:0] top_left_r; // index of the 16x16 top left corner
// reg [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels
// wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, (valid_rows_r0==3)?
// in_cntr[0]:
// ~valid_rows_r0[0],
// in_cntr[6:1]};
wire [ 9:0] fold_addr= {tile_size_r,inv_checker_r, in_cntr[0], in_cntr[6:1]};
reg [SHIFT_WIDTH-1:0] x_shft_r0; // tile pixel X fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] y_shft_r0; // tile pixel Y fractional shift (valid @ start)
reg [SHIFT_WIDTH-1:0] x_shft_r; // matching delay
reg [SHIFT_WIDTH-1:0] y_shft_r; // matching delay
wire [17:0] fold_rom_out;
// does not have enough bits for pixel address (9) and window address(8), restoring MSB of pixel address from both MSBc
wire [7:0] wnd_a_w = fold_rom_out[7:0];
wire [PIX_ADDR_WIDTH-1:0] pix_a_w = {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};
reg [PIX_ADDR_WIDTH-1:0] pix_a_r;
wire [ 1:0] sgn_w = fold_rom_out[16 +: 2];
wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out
reg green_r;
reg [1:0] start_r;
reg pre_last_in_r; // @ 7e
reg last_in_r; // @ 7f
wire var_first_d; // adding subtracting first variant of 2 folds
assign phases = run_r;
assign var_pre2_first = var_first_d;
assign pre_last_in = pre_last_in_r;
always @ (posedge clk) begin
start_r <= {start_r[0], start};
if (rst) run_r <= 0;
else run_r <= {run_r[5:0], start | (run_r[0] & ~last_in_r)};
if (start) in_cntr <= ~green & valid_odd;
else if (run_r) in_cntr <= in_cntr + (green_r? 1 : 2);
if (start) begin
tile_size_r <= tile_size;
inv_checker_r<= inv_checker;
top_left_r0 <= top_left;
green_r <= green;
// valid_rows_r0 <= green? 2'h3: {valid_odd, ~valid_odd};
x_shft_r0 <= x_shft;
y_shft_r0 <= y_shft;
end
// if (in_cntr == 1) top_left_r <=top_left_r0;
if ( start_r[1]) top_left_r <=top_left_r0;
// if (in_cntr == 1) begin
if (start_r[1]) begin
x_shft_r <= x_shft_r0;
y_shft_r <= y_shft_r0;
end
if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};
// pre_last_in <= in_cntr[6:0] == 7'h7d;
pre_last_in_r <= run_r[0] && (green_r? (in_cntr[6:0] == 7'h7d):(in_cntr[6:1] == 6'h3d));
last_in_r<= pre_last_in_r;
end
ram18tp_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4)
`ifdef PRELOAD_BRAMS
`include "mclt_bayer_fold_rom.vh"
`endif
) i_mclt_fold_rom (
.clk_a (clk), // input
.addr_a (fold_addr), // input[9:0]
.en_a (run_r[0]), // input
.regen_a (run_r[1]), // input
.we_a (1'b0), // input
.data_out_a(fold_rom_out), // output[17:0]
.data_in_a (18'b0), // input[17:0]
// port B may be used for other mclt16x16
.clk_b (1'b0), // input
.addr_b (10'b0), // input[9:0]
.en_b (1'b0), // input
.regen_b (1'b0), // input
.we_b (1'b0), // input
.data_out_b(), // output[17:0]
.data_in_b (18'b0) // input[17:0]
);
// Matching window latency with pixel data latency
generate
if (ADDR_DLY !=0) begin
wire [3:0] addr_dly = ADDR_DLY - 1; // iverilog problem mitigation
dly_var #(
.WIDTH(11),
.DLY_WIDTH(4)
) dly_pixel_addr_i (
.clk (clk), // input
.rst (rst), // input
.dly (addr_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({pre_page, run_r[3], pix_a_r}), // input[0:0]
.dout ({pix_page, pix_re, pix_addr}) // output[0:0]
);
end else begin
assign pix_page = pre_page;
assign pix_re = run_r[3];
assign pix_addr = pix_a_r;
end
endgenerate
// Latency = 6
mclt_wnd_mul #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.COORD_WIDTH (COORD_WIDTH),
.OUT_WIDTH (WND_WIDTH)
) mclt_wnd_i (
.clk (clk), // input
.en (run_r[2]), // input
.x_in (wnd_a_w[3:0]), // input[3:0]
.y_in (wnd_a_w[7:4]), // input[3:0]
.x_shft (x_shft_r), // input[7:0]
.y_shft (y_shft_r), // input[7:0]
.zero_in (1'b0), // blank_r), // input 2 cycles after inputs!
.wnd_out (window) // output[17:0] valid with in_busy[8]
);
dly_var #(
.WIDTH(2),
.DLY_WIDTH(4)
) dly_signs_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h5), // TODO: put correct value!
.din (sgn_w), // input[0:0]
.dout (signs) // output[0:0]
);
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_var_first_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h8), // input[3:0]
.din (run_r[0] && (in_cntr[0] == 0)), // input[0:0]
// .din (start_r[0]), // input[0:0]
.dout (var_first_d) // output[0:0]
);
wire [3:0] green_dly = ADDR_DLY + 3; // iverilog problem mitigation
wire green_stb;
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_pixel_addr_i (
.clk (clk), // input
.rst (rst), // input
.dly (green_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din (start), // input[0:0]
.dout (green_stb) // output[0:0]
);
always @ (posedge clk) begin
if (green_stb) green_late <= green_r;
end
endmodule
/*!
* <b>Module:</b>mclt_test_01
* @file mclt_test_01.tf
* @date 2016-12-02
* @author Andrey Filippov
*
* @brief testing MCLT 16x16 -> 4*8*8 transform
* Uses 2 DSP blocks
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*mclt_test_01.tf is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mclt_test_01.tf is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh"
// `define INSTANTIATE_DSP48E1
// `define PRELOAD_BRAMS
// `define ROUND
module mclt_test_05 ();
`ifdef IVERILOG
`ifdef NON_VDT_ENVIROMENT
parameter fstname="mclt_test_05.fst";
`else
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else // IVERILOG
`ifdef CVC
`ifdef NON_VDT_ENVIROMENT
parameter fstname = "x393.fst";
`else // NON_VDT_ENVIROMENT
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else
parameter fstname = "mclt_test_05.fst";
`endif // CVC
`endif // IVERILOG
parameter CLK_PERIOD = 10; // ns
// parameter WIDTH = 25; //4; // input data width
parameter SHIFT_WIDTH = 7; // bits in shift (7 bits - fractional)
parameter COORD_WIDTH = 10; // bits in full coordinate 10 for 18K RAM
parameter PIXEL_WIDTH = 16; // input pixel width (unsigned)
parameter WND_WIDTH = 18; // input pixel width (unsigned)
parameter OUT_WIDTH = 25; // bits in dtt output
parameter DTT_IN_WIDTH = 25; // bits in DTT input
parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 2; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass
parameter DSP_B_WIDTH = 18; // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25;
parameter DSP_P_WIDTH = 48;
parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause
reg RST = 1'b1;
reg CLK = 1'b0;
integer i, n;
wire pre_busy;
reg LATE = 0;
wire pre_last_in; // SuppressThisWarning VEditor - output only
wire pre_first_out; // SuppressThisWarning VEditor - output only
wire pre_last_out; // SuppressThisWarning VEditor - output only
wire [7:0] out_addr; // SuppressThisWarning VEditor - output only
wire dv; // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout0; // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout1; // SuppressThisWarning VEditor - output only
// assign #(1) pre_busy = pre_busy_w;
always #(CLK_PERIOD/2) CLK = ~CLK;
localparam PIX_ADDR_WIDTH = 9;
// localparam ADDR_DLY = 2;
localparam EXT_PIX_LATENCY = 2; // external pixel buffer a->d latency (may increase to 4 for gamma)
localparam TILE_SIDE = 22;
localparam TILE_SIZE = TILE_SIDE * TILE_SIDE;
localparam TILE_START= 'hc;
localparam TILE_END = TILE_START + TILE_SIZE;
localparam INTILE_START = TILE_END;
localparam INTILE_SIZE = 'h300;
localparam INTILE_END = INTILE_START + INTILE_SIZE;
localparam SGN_START = INTILE_END;
localparam SGN_SIZE = 'h300;
localparam SGN_END = SGN_START + SGN_SIZE;
localparam WND_START = SGN_END;
localparam WND_SIZE = 'h300;
localparam WND_END = WND_START + WND_SIZE;
localparam DTT_IN_START = WND_END;
localparam DTT_IN_SIZE = 'h300;
localparam DTT_IN_END = DTT_IN_START + DTT_IN_SIZE;
localparam DTT_OUT_START = DTT_IN_END;
localparam DTT_OUT_SIZE = 'h300;
localparam DTT_OUT_END = DTT_OUT_START + DTT_OUT_SIZE;
localparam DTT_ROT_START = DTT_OUT_END;
localparam DTT_ROT_SIZE = 'h300;
localparam DTT_ROT_END = DTT_ROT_START + DTT_ROT_SIZE; // SuppressThisWarning VEditor
integer java_all[0:5103]; //'h126f]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [1:0] TILE_SIZE2 = (TILE_SIDE - 16) >> 1; // 3; // 22;
wire PIX_RE; // SuppressThisWarning VEditor : debug only
wire [8:0] PIX_ADDR9;
wire PIX_COPY_PAGE; // copy page address // SuppressThisWarning VEditor - not yet used
wire [PIXEL_WIDTH-1 : 0] PIX_D;
reg [PIXEL_WIDTH-1 : 0] bayer_tiles[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [PIXEL_WIDTH-1 : 0] jav_pix_in [0:INTILE_SIZE*2-1];
reg [3 : 0] jav_signs [0:SGN_SIZE*2-1]; // SuppressThisWarning VEditor not yet used
reg [WND_WIDTH-1 : 0] jav_wnd [0:WND_SIZE*2-1]; // SuppressThisWarning VEditor not yet used
reg [DTT_IN_WIDTH - 1:0] jav_dtt_in [0:DTT_IN_SIZE*2-1];
reg [OUT_WIDTH - 1:0] jav_dtt_out[0:DTT_OUT_SIZE*2-1];
reg [OUT_WIDTH - 1:0] jav_dtt_rot[0:DTT_ROT_SIZE*2-1];
reg [SHIFT_WIDTH-1:0] jav_shifts_x [0:3*2-1];
reg [SHIFT_WIDTH-1:0] jav_shifts_y [0:3*2-1];
reg jav_inv_check[0:3*2-1];
reg [7:0] jav_top_left[0:3*2-1];
reg [1:0] jav_vld_rows[0:3*2-1];
integer offs_x, offs_y, top_left;
reg [1:0] byr_index; // [0:2]; // bayer index of top-left 16x16 tile
initial begin
$readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
$display("000c: %h", java_all['h000c]);
$display("01f0: %h", java_all['h01f0]);
$display("02f0: %h", java_all['h02f0]);
$display("03f0: %h", java_all['h03f0]);
$display("04f0: %h", java_all['h04f0]);
$display("05f0: %h", java_all['h05f0]);
$display("06f0: %h", java_all['h06f0]);
$display("07f0: %h", java_all['h07f0]);
$display("08f0: %h", java_all['h08f0]);
$display("09f0: %h", java_all['h09f0]);
$display("0af0: %h", java_all['h0af0]);
$display("0bf0: %h", java_all['h0bf0]);
$display("0cf0: %h", java_all['h0cf0]);
$display("0df0: %h", java_all['h0df0]);
$display("0ef0: %h", java_all['h0ef0]);
$display("0ff0: %h", java_all['h0ff0]);
$display("10f0: %h", java_all['h10f0]);
$display("11f0: %h", java_all['h11f0]);
$display("12f0: %h", java_all['h12f0]);
for (i=0; i<3; i=i+1) begin
jav_shifts_x[0 + i] = java_all[0 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_x[3 + i] = java_all[0 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[0 + i] = java_all[1 + 4 * i][SHIFT_WIDTH-1:0];
jav_shifts_y[3 + i] = java_all[1 + 4 * i][SHIFT_WIDTH-1:0];
end
for (i=0; i < 3; i=i+1) begin // two sets
byr_index = (java_all[2 + 4 * i] & 1) + ((java_all[3 + 4 * i] & 1) << 1); // bayer index of top left 16x16 tile
offs_x= java_all[2 + 4 * i] - java_all[2 + 4 * 2] + TILE_SIZE2;
offs_y= java_all[3 + 4 * i] - java_all[3 + 4 * 2] + TILE_SIZE2;
top_left = offs_x + TILE_SIDE * offs_y;
jav_top_left[0 + i] = top_left[7:0];
jav_top_left[3 + i] = top_left[7:0];
jav_inv_check[0 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_inv_check[3 + i] = ((i == 2)? 1'b0 : 1'b1) ^ byr_index[0] ^ byr_index[1];
jav_vld_rows[0 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
jav_vld_rows[3 + i] = (i == 2)? 2'h3 : ((i == 1)?{~byr_index[1],byr_index[1]}:{byr_index[1],~byr_index[1]});
end
for (i=0; i < 2; i=i+1) begin // two sets
end
for (i=0; i<TILE_SIZE; i=i+1) begin
bayer_tiles['h000 + i] = java_all[TILE_START+i][PIXEL_WIDTH-1 : 0];
bayer_tiles['h200 + i] = java_all[TILE_START+i][PIXEL_WIDTH-1 : 0];
end
for (i=0; i<INTILE_SIZE; i=i+1) begin
jav_pix_in[0 + i] = java_all[INTILE_START+i][PIXEL_WIDTH-1 : 0];
jav_pix_in[INTILE_SIZE + i] = java_all[INTILE_START+i][PIXEL_WIDTH-1 : 0];
end
for (i=0; i<SGN_SIZE; i=i+1) begin
jav_signs[ + i] = java_all[SGN_START+i][3 : 0];
jav_signs[SGN_SIZE + i] = java_all[SGN_START+i][3 : 0];
end
for (i=0; i<WND_SIZE; i=i+1) begin
jav_wnd[ + i] = java_all[WND_START+i][WND_WIDTH-1 : 0];
jav_wnd[WND_SIZE + i] = java_all[WND_START+i][WND_WIDTH-1 : 0];
end
for (i=0; i<DTT_IN_SIZE; i=i+1) begin
jav_dtt_in[ + i] = java_all[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0];
jav_dtt_in[DTT_IN_SIZE + i] = java_all[DTT_IN_START+i][DTT_IN_WIDTH-1 : 0];
end
for (i=0; i<DTT_OUT_SIZE; i=i+1) begin
jav_dtt_out[ + i] = java_all[DTT_OUT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_out[DTT_OUT_SIZE + i] = java_all[DTT_OUT_START+i][OUT_WIDTH-1 : 0];
end
for (i=0; i<DTT_ROT_SIZE; i=i+1) begin
jav_dtt_rot[ + i] = java_all[DTT_ROT_START+i][OUT_WIDTH-1 : 0];
jav_dtt_rot[DTT_ROT_SIZE + i] = java_all[DTT_ROT_START+i][OUT_WIDTH-1 : 0];
end
end
reg START;
reg [8:0] in_cntr;
reg in_run;
wire pre_last_count = (in_cntr == 'h17e);
reg last_count_r;
wire pre_last_128 = (in_cntr[6:0] == 'h7e);
reg last_128_r;
wire start = START | (last_128_r && ! in_cntr[8]);
reg PAGE; // full page, 192 clocks
reg [2:0] SUB_PAGE; // single color page
reg PIX_PAGE;
wire [9:0] PIX_ADDR10 = {PIX_PAGE,PIX_ADDR9}; // SuppressThisWarning VEditor debug output
always @ (posedge CLK) begin
last_count_r <= pre_last_count;
last_128_r <= pre_last_128;
if (RST) in_run <= 0;
else if (START) in_run <= 1;
else if (last_count_r) in_run <= 0;
if (!in_run) in_cntr <= 0;
else in_cntr <= in_cntr + 1;
if (RST) PAGE <= 0;
else if (pre_last_count) PAGE <= PAGE + 1;
if (RST) SUB_PAGE <= 0;
else if (pre_last_128) SUB_PAGE <= SUB_PAGE + 1;
if (PIX_COPY_PAGE) PIX_PAGE <= PAGE;
end
initial begin
$dumpfile(fstname);
$dumpvars(0,mclt_test_05); // SuppressThisWarning VEditor
#100;
START = 0;
LATE = 0;
RST = 0;
#100;
repeat (10) @(posedge CLK);
#1 START = 1;
@(posedge CLK)
#1 START = 0;
for (n = 0; n < 1; n = n+1) begin
if (n >= 0) LATE = 1;
while (!in_cntr[8]) begin
@(posedge CLK);
#1;
end
while (pre_busy || LATE) begin
if (!pre_busy) LATE = 0;
@(posedge CLK);
#1;
end
#1 START = 1;
@(posedge CLK)
#1 START = 0;
end
repeat (1024) @(posedge CLK);
$finish;
end
integer n1, cntr1, diff1;// SuppressThisWarning VEditor : assigned in $readmem() system task
wire [7:0] wnd_a_w = mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w;
wire [10:0] jav_pix_in_now_a = {n1[2:0], wnd_a_w};
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now = cntr1[7]?{PIXEL_WIDTH{1'bz}}:jav_pix_in[jav_pix_in_now_a];
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now_d;
dly_var #(
.WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4)
) dly_jav_pix_in_now_d_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h4), // input[3:0]
.din (jav_pix_in_now), // input[0:0]
.dout (jav_pix_in_now_d) // output[0:0]
);
initial begin
while (RST) @(negedge CLK);
for (n1 = 0; n1 < 6; n1 = n1+1) begin
while (mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr != 2) begin
@(negedge CLK);
end
for (cntr1 = 0; cntr1 < 128; cntr1 = cntr1 + 1) begin
diff1 = PIX_D - jav_pix_in_now_d; // java_fold_index[cntr1];
@(negedge CLK);
end
end
end
//Compare DTT inputs
integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_bayer_i.data_dtt_in;
// wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[{n4[2:0], cntr4[1:0],cntr4[7:2]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[{n4[2:0], 1'b0, cntr4[0],cntr4[6:1]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]
initial begin
while (RST) @(negedge CLK);
for (n4 = 0; n4 < 6; n4 = n4+1) begin
while ((mclt16x16_bayer_i.dtt_in_cntr != 0) ||!mclt16x16_bayer_i.dtt_we) begin
@(negedge CLK);
end
for (cntr4 = 0; cntr4 < 128; cntr4 = cntr4 + 1) begin
#1;
diff4 = data_dtt_in - java_data_dtt_in;
if (n4 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_bayer_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = jav_dtt_in[{n5[2:0], 1'b0, cntr5[6:0]}]; // java_dtt_in0[cntr5[7:0]];
wire dtt_r_regen = mclt16x16_bayer_i.dtt_r_regen;
reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation
always @ (posedge CLK) begin
if (RST) dtt_r_dv <= 0;
else dtt_r_dv <= dtt_r_regen;
end
initial begin
while (RST) @(negedge CLK);
for (n5 = 0; n5 < 6; n5 = n5+1) begin
while ((!dtt_r_dv) || (mclt16x16_bayer_i.dtt_r_cntr[6:0] != 2)) begin
@(negedge CLK);
end
for (cntr5 = 0; cntr5 < 128; cntr5 = cntr5 + 1) begin
#1;
diff5 = dtt_r_data - java_dtt_r_data;
if (n5 < 1) diff5a = dtt_r_data - java_dtt_r_data; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
integer n6, cntr6, diff60, diff61; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_out0 = mclt16x16_bayer_i.dtt_rd_data0;
wire [DTT_IN_WIDTH-1:0] data_dtt_out1 = mclt16x16_bayer_i.dtt_rd_data1;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out0 = jav_dtt_out[{
n6[2:0],
1'b0,
cntr6[0] ^ cntr6[1],
cntr6[0]? (~cntr6[6:2]) : cntr6[6:2],
cntr6[0]}];
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out1 = jav_dtt_out[{
n6[2:0],
1'b0,
cntr6[0] ^ cntr6[1],
cntr6[0]? (~cntr6[6:2]) : cntr6[6:2],
~cntr6[0]}];
initial begin
while (RST) @(negedge CLK);
for (n6 = 0; n6 < 6; n6 = n6+1) begin
while ((!mclt16x16_bayer_i.dtt_rd_regen_dv[2]) || (mclt16x16_bayer_i.dtt_rd_cntr_pre[6:0] != 3)) begin
@(negedge CLK);
end
for (cntr6 = 0; cntr6 < 128; cntr6 = cntr6 + 1) begin
#1;
diff60 = data_dtt_out0 - java_data_dtt_out0;
diff61 = data_dtt_out1 - java_data_dtt_out1;
@(negedge CLK);
end
end
end
reg FIRST_OUT;
always @(posedge CLK) FIRST_OUT <= mclt16x16_bayer_i.pre_first_out;
integer n7, cntr7, diff70, diff71; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [OUT_WIDTH-1:0] java_data_dtt_rot0 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b0}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
wire [OUT_WIDTH-1:0] java_data_dtt_rot1 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b1}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
initial begin
while (RST) @(negedge CLK);
for (n7 = 0; n7 < 6; n7 = n7+1) begin
while (!FIRST_OUT) begin
@(negedge CLK);
end
for (cntr7 = 0; cntr7 < 128; cntr7 = cntr7 + 1) begin
#1;
diff70 = dout0 - java_data_dtt_rot0;
diff71 = dout1 - java_data_dtt_rot1;
@(negedge CLK);
end
end
end
mclt16x16_bayer #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.EXT_PIX_LATENCY (EXT_PIX_LATENCY), // 2), // external pixel buffer a->d latency (may increase to 4 for gamma)
.COORD_WIDTH (COORD_WIDTH),
.PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
) mclt16x16_bayer_i (
.clk (CLK), // input
.rst (RST), // input
.start (start), // input
.tile_size (TILE_SIZE2), // input[1:0]
.inv_checker (jav_inv_check[SUB_PAGE]), // INV_CHECKER), // input
.top_left (jav_top_left[SUB_PAGE]), // TOP_LEFT), // input[7:0]
.valid_rows (jav_vld_rows[SUB_PAGE]), // VALID_ROWS), // input[1:0]
.x_shft (jav_shifts_x[SUB_PAGE]), //CLT_SHIFT_X), // input[6:0]
.y_shft (jav_shifts_y[SUB_PAGE]), //CLT_SHIFT_Y), // input[6:0]
.pix_addr (PIX_ADDR9), // output[8:0]
.pix_re (PIX_RE), // output
.pix_page (PIX_COPY_PAGE), // output
.pix_d (PIX_D), // input[15:0]
.pre_busy (pre_busy), // output
.pre_last_in (pre_last_in), // output
.pre_first_out (pre_first_out), // output
.pre_last_out (pre_last_out), // output
.out_addr (out_addr), // output[7:0]
.dv (dv), // output
.dout0 (dout0), // output[24:0] signed
.dout1 (dout1) // output[24:0] signed
);
dly_var #(
.WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4)
) dly_pix_dly_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (PIX_RE?bayer_tiles[PIX_ADDR10]:{PIXEL_WIDTH{1'bz}}), // input[0:0]
.dout (PIX_D) // output[0:0]
);
wire PIX_RE3; // SuppressThisWarning VEditor : debug only
wire [8:0] PIX_ADDR93;
reg PIX_PAGE3;
wire [9:0] PIX_ADDR103 = {PIX_PAGE3,PIX_ADDR93}; // SuppressThisWarning VEditor debug output
wire PIX_COPY_PAGE3; // copy page address // SuppressThisWarning VEditor - not yet used
wire [PIXEL_WIDTH-1 : 0] PIX_D3;
reg start3;
reg page3; // 1/2-nd bayer tile
reg pre_run;
reg [1:0] pre_run_cntr;
wire [2:0] color_page = pre_run_cntr + 3 * page3;
always @ (posedge CLK) begin
if (START) page3 <= (SUB_PAGE > 2);
if (RST) pre_run <= 0;
else if (START) pre_run <= 1;
else if (pre_run_cntr == 2) pre_run <= 0;
if (!pre_run) pre_run_cntr <= 0;
else pre_run_cntr <= pre_run_cntr + 1;
if (PIX_COPY_PAGE3) PIX_PAGE3 <= page3;
start3 <= (pre_run_cntr == 2);
end
mclt16x16_bayer3 #(
.SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.EXT_PIX_LATENCY (EXT_PIX_LATENCY), // 2), // external pixel buffer a->d latency (may increase to 4 for gamma)
.COORD_WIDTH (COORD_WIDTH),
.PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
) mclt16x16_bayer3_i (
.clk (CLK), // input
.rst (RST), // input
.start (start3), // input
.tile_size (TILE_SIZE2), // input[1:0]
.color_wa (pre_run_cntr), // input[1:0]
.inv_checker (jav_inv_check[color_page]), // input
.top_left (jav_top_left[color_page]), // TOP_LEFT), // input[7:0]
.valid_odd (jav_vld_rows[color_page][1]),// VALID_ROWS), // input[1:0]
.x_shft (jav_shifts_x[color_page]), //CLT_SHIFT_X), // input[6:0]
.y_shft (jav_shifts_y[color_page]), //CLT_SHIFT_Y), // input[6:0]
.set_inv_checker(pre_run), // input
.set_top_left (pre_run), // input
.set_valid_odd (pre_run), // input
.set_x_shft (pre_run), // input
.set_y_shft (pre_run), // input
.pix_addr (PIX_ADDR93), // output[8:0]
.pix_re (PIX_RE3), // output
.pix_page (PIX_COPY_PAGE3), // output
.pix_d (PIX_D3), // input[15:0]
.pre_busy(), // output
.pre_last_in(), // output
.pre_first_out(), // output
.pre_last_out(), // output
.out_addr(), // output[7:0]
.dv(), // output
.dout_r(), // output[24:0] signed
.dout_b(), // output[24:0] signed
.dout_g() // output[24:0] signed
);
dly_var #(
.WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4)
) dly_pix_dly3_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (PIX_RE3?bayer_tiles[PIX_ADDR103]:{PIXEL_WIDTH{1'bz}}), // input[0:0]
.dout (PIX_D3) // output[0:0]
);
endmodule
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Wed Dec 27 05:08:10 2017
[*] Thu Dec 28 00:31:10 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226172318550.fst"
[dumpfile_mtime] "Wed Dec 27 00:23:21 2017"
[dumpfile_size] 842624
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226220814551.fst"
[dumpfile_mtime] "Wed Dec 27 05:08:17 2017"
[dumpfile_size] 843036
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav"
[timestart] 4875410
[size] 1920 1171
[pos] -1920 0
*-14.216505 4955000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1824 1171
[pos] 0 0
*-21.266958 10681000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_04.
[treeopen] mclt_test_04.mclt16x16_bayer_i.
[treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.
......
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Dec 28 08:27:56 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_05-20171228004859468.fst"
[dumpfile_mtime] "Thu Dec 28 07:49:04 2017"
[dumpfile_size] 1234767
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_05.sav"
[timestart] 0
[size] 1920 1171
[pos] -1920 0
*-21.077135 3685000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_05.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.
[sst_width] 204
[signals_width] 348
[sst_expanded] 1
[sst_vpaned_height] 343
@800200
-top_3
@28
mclt_test_05.CLK
mclt_test_05.START
mclt_test_05.start3
mclt_test_05.page3
@22
mclt_test_05.color_page[2:0]
@28
mclt_test_05.start
@22
mclt_test_05.PIX_ADDR10[9:0]
@28
mclt_test_05.PIX_RE
@22
mclt_test_05.PIX_D[15:0]
mclt_test_05.PIX_ADDR103[9:0]
@28
mclt_test_05.PIX_RE3
@22
mclt_test_05.PIX_D3[15:0]
@1000200
-top_3
@800200
-mclt_bayer3
@28
mclt_test_05.mclt16x16_bayer3_i.start
@c00022
mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(1)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(2)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(3)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(4)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(5)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(6)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(7)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
@1401200
-group_end
@28
(1)mclt_test_05.mclt16x16_bayer3_i.start_block_r[1:0]
(0)mclt_test_05.mclt16x16_bayer3_i.start_block_r[1:0]
mclt_test_05.mclt16x16_bayer3_i.inv_checker_ram_reg
@22
mclt_test_05.mclt16x16_bayer3_i.top_left_ram_reg[7:0]
@28
mclt_test_05.mclt16x16_bayer3_i.valid_odd_ram_reg
@22
mclt_test_05.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_05.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
@28
mclt_test_05.mclt16x16_bayer3_i.green_late
mclt_test_05.mclt16x16_bayer3_i.dtt_we
@c00022
mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer3_i.data_dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_r_re
@22
mclt_test_05.mclt16x16_bayer3_i.dtt_r_ra[8:0]
@1000200
-mclt_bayer3
@800200
-comp_addresses_1
@200
-
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_we
@c08022
mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@1401200
-group_end
@20000
-
-
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_r_re
@8022
mclt_test_05.mclt16x16_bayer3_i.dtt_r_ra[8:0]
@20000
-
-
@200
-
@8023
mclt_test_05.mclt16x16_bayer3_i.dbg_dtt_in_rawa[8:0]
@20000
-
-
@1000200
-comp_addresses_1
@800200
-fold
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.start
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.pre_last_in_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.last_in_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.green
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.green_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.valid_odd
@c00022
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
@c00022
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
@1401200
-group_end
-group_end
@1000200
-fold
@c00200
-fold_accum
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.green
@800022
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
@1001200
-group_end
@800028
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
@1001200
-group_end
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pre_phase
@22
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.window[17:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_d[15:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_d_r[15:0]
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_pre2_first
@22
[color] 2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dtt_in[24:0]
@28
[color] 2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dtt_in_dv
@c00028
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.en_a2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.accum1
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.accum2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pout1[47:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pout2[47:0]
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_first
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_last
@1401200
-fold_accum
@800200
-old_fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.run_r[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.var_pre2_first
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.var_first_d
@200
-
@1000200
-old_fold
@800200
- old_accum
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_last
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_pre2_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout1[47:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout2[47:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
[color] 3
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dv
@200
-
@1000200
- old_accum
@c00200
-top
@28
mclt_test_05.RST
mclt_test_05.CLK
mclt_test_05.START
mclt_test_05.SUB_PAGE[2:0]
mclt_test_05.pre_last_128
mclt_test_05.last_128_r
mclt_test_05.pre_last_count
mclt_test_05.last_count_r
mclt_test_05.in_run
@c00022
mclt_test_05.in_cntr[8:0]
@28
(0)mclt_test_05.in_cntr[8:0]
(1)mclt_test_05.in_cntr[8:0]
(2)mclt_test_05.in_cntr[8:0]
(3)mclt_test_05.in_cntr[8:0]
(4)mclt_test_05.in_cntr[8:0]
(5)mclt_test_05.in_cntr[8:0]
(6)mclt_test_05.in_cntr[8:0]
(7)mclt_test_05.in_cntr[8:0]
(8)mclt_test_05.in_cntr[8:0]
@1401200
-group_end
@28
mclt_test_05.start
mclt_test_05.PAGE
@c00022
mclt_test_05.PIX_ADDR9[8:0]
@28
(0)mclt_test_05.PIX_ADDR9[8:0]
(1)mclt_test_05.PIX_ADDR9[8:0]
(2)mclt_test_05.PIX_ADDR9[8:0]
(3)mclt_test_05.PIX_ADDR9[8:0]
(4)mclt_test_05.PIX_ADDR9[8:0]
(5)mclt_test_05.PIX_ADDR9[8:0]
(6)mclt_test_05.PIX_ADDR9[8:0]
(7)mclt_test_05.PIX_ADDR9[8:0]
(8)mclt_test_05.PIX_ADDR9[8:0]
@1401200
-group_end
@c00022
mclt_test_05.PIX_ADDR10[9:0]
@28
(0)mclt_test_05.PIX_ADDR10[9:0]
(1)mclt_test_05.PIX_ADDR10[9:0]
(2)mclt_test_05.PIX_ADDR10[9:0]
(3)mclt_test_05.PIX_ADDR10[9:0]
(4)mclt_test_05.PIX_ADDR10[9:0]
(5)mclt_test_05.PIX_ADDR10[9:0]
(6)mclt_test_05.PIX_ADDR10[9:0]
(7)mclt_test_05.PIX_ADDR10[9:0]
(8)mclt_test_05.PIX_ADDR10[9:0]
(9)mclt_test_05.PIX_ADDR10[9:0]
@1401200
-group_end
@22
[color] 2
mclt_test_05.PIX_D[15:0]
@28
mclt_test_05.PIX_RE
mclt_test_05.pre_busy
@22
mclt_test_05.SUB_PAGE[2:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.valid_rows[1:0]
mclt_test_05.mclt16x16_bayer_i.top_left[7:0]
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft[6:0]
@c00420
mclt_test_05.cntr1
@28
(0)mclt_test_05.cntr1
(1)mclt_test_05.cntr1
(2)mclt_test_05.cntr1
(3)mclt_test_05.cntr1
(4)mclt_test_05.cntr1
(5)mclt_test_05.cntr1
(6)mclt_test_05.cntr1
(7)mclt_test_05.cntr1
(8)mclt_test_05.cntr1
(9)mclt_test_05.cntr1
(10)mclt_test_05.cntr1
(11)mclt_test_05.cntr1
(12)mclt_test_05.cntr1
(13)mclt_test_05.cntr1
(14)mclt_test_05.cntr1
(15)mclt_test_05.cntr1
(16)mclt_test_05.cntr1
(17)mclt_test_05.cntr1
(18)mclt_test_05.cntr1
(19)mclt_test_05.cntr1
(20)mclt_test_05.cntr1
(21)mclt_test_05.cntr1
(22)mclt_test_05.cntr1
(23)mclt_test_05.cntr1
(24)mclt_test_05.cntr1
(25)mclt_test_05.cntr1
(26)mclt_test_05.cntr1
(27)mclt_test_05.cntr1
(28)mclt_test_05.cntr1
(29)mclt_test_05.cntr1
(30)mclt_test_05.cntr1
(31)mclt_test_05.cntr1
@1401200
-group_end
@420
mclt_test_05.n1
@22
mclt_test_05.wnd_a_w[7:0]
mclt_test_05.jav_pix_in_now_a[10:0]
mclt_test_05.jav_pix_in_now[15:0]
[color] 3
mclt_test_05.jav_pix_in_now_d[15:0]
@420
mclt_test_05.diff1
mclt_test_05.n4
@22
mclt_test_05.cntr4
mclt_test_05.data_dtt_in[24:0]
mclt_test_05.java_data_dtt_in[24:0]
@420
mclt_test_05.diff4
@8420
mclt_test_05.diff4
@420
mclt_test_05.n5
mclt_test_05.cntr5
@22
[color] 3
mclt_test_05.dtt_r_data[24:0]
mclt_test_05.java_dtt_r_data[24:0]
@420
mclt_test_05.diff5
@8420
mclt_test_05.diff5
@420
mclt_test_05.n6
mclt_test_05.cntr6
@22
mclt_test_05.data_dtt_out0[24:0]
mclt_test_05.data_dtt_out1[24:0]
mclt_test_05.java_data_dtt_out0[24:0]
mclt_test_05.java_data_dtt_out1[24:0]
@420
mclt_test_05.diff60
mclt_test_05.diff61
@8420
mclt_test_05.diff60
mclt_test_05.diff61
@420
mclt_test_05.n7
mclt_test_05.cntr7
@22
mclt_test_05.mclt16x16_bayer_i.dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dout1[24:0]
mclt_test_05.java_data_dtt_rot0[24:0]
mclt_test_05.java_data_dtt_rot1[24:0]
@8420
mclt_test_05.diff70
mclt_test_05.diff71
@200
-
@28
mclt_test_05.dv
@22
mclt_test_05.dout0[24:0]
mclt_test_05.dout1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]
@800200
-mclt16x16_bayer
@c00200
-dtt_iv_8x8_ad
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.xin[24:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0h
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0[2:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1h
@22
[color] 2
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1[2:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin0[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_di[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_wa[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_we[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_start
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_run[2:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_ra[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout1[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start_out
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_we
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wa[3:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]
@200
-
@1401200
-dtt_iv_8x8_ad
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_data0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_data1[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_rd_data0[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_rd_data1[24:0]
@200
-
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_out_we
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start_fill
mclt_test_05.mclt16x16_bayer_i.dtt_first_quad_out
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wpage[1:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wpage2[1:0]
@800028
mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
@1001200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@20000
-
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_regen_dv[3:0]
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@20000
-
-
@22
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@20000
-
-
@200
-
@22
mclt_test_05.mclt16x16_bayer_i.valid_rows[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.top_left[7:0]
mclt_test_05.mclt16x16_bayer_i.data_dtt_in[24:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
@1401200
-group_end
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.dtt_we
@22
mclt_test_05.mclt16x16_bayer_i.window_w[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.start
@800200
-fold
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.inv_checker_r
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_addr[9:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(7)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(8)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(9)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(10)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(11)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(12)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(13)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(14)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(15)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(16)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(17)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
@1401200
-group_end
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(7)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0]
@1000200
-fold
@200
-
@1000200
-mclt16x16_bayer
@1401200
-top
@c00200
-mclt_bayer
-top
@28
mclt_test_05.mclt16x16_bayer_i.clk
mclt_test_05.mclt16x16_bayer_i.start
mclt_test_05.mclt16x16_bayer_i.pre_last_in
mclt_test_05.mclt16x16_bayer_i.pre_last_in_w
mclt_test_05.mclt16x16_bayer_i.pre_busy
mclt_test_05.mclt16x16_bayer_i.pre_first_out
mclt_test_05.mclt16x16_bayer_i.dv
@22
mclt_test_05.mclt16x16_bayer_i.dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dout1[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout1[24:0]
@8420
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout1[24:0]
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_r_data[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_out_wd[24:0]
@c00200
-fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pre_last_in
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1401200
-fold
-top
@200
-
@22
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.start
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.start_r[1:0]
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r2[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.start_dtt
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r3[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill
mclt_test_05.mclt16x16_bayer_i.dtt_start_second_fill
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r4[6:0]
@c00200
-rotator0
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.fd_din[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.rom_a[9:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.fd_out[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_h[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_v[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_vr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_hv[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.hv_sin
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
@28
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_h_consec[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_v[7:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.pre_dv
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.pre_first_out
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea1_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea1_2
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea2_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea2_2
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sela_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_2
(14)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(13)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(11)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(10)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(9)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2
(2)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
(0)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ceb1_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ceb2_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.selb_1
@800200
-dsp1
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0]
@200
-
@1000200
-dsp1
@1401200
-rotator0
@c00200
-rotator1
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.fd_din[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_h[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_v[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_hr[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_v0[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_vr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_hv[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.hv_sin
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.sign_cs[4:0]
@28
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.ph[16:0]
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.negm_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.negm_2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_h_consec[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_h[7:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_v[7:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.pre_dv
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.pre_first_out
@200
-
@1401200
-rotator1
@c00200
-mclt_bayer_fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.rst
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.y_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_re
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.window[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
@c00200
-mclt_wnd_mul
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200
-mclt_wnd_mul
-mclt_bayer_fold
@22
mclt_test_05.mclt16x16_bayer_i.pix_d[15:0]
mclt_test_05.mclt16x16_bayer_i.window_w[17:0]
mclt_test_05.mclt16x16_bayer_i.data_dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_we
@22
mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_in_page
mclt_test_05.mclt16x16_bayer_i.start_dtt
@c00200
-mclt_baeyer_fold_accum
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pre_phase
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_d[15:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.window[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_pre_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_last
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dv
(0)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@200
-
@22
mclt_test_05.mclt16x16_bayer_i.signs[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m1
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout1[47:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout2[47:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dsp[24:0]
@800200
-dsp1
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.cead
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qp_o_reg1[47:0]
@1000200
-dsp1
@800200
-dsp2
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.cead
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qp_o_reg1[47:0]
@200
-
@1000200
-dsp2
@1401200
-mclt_baeyer_fold_accum
@c00200
-membuf
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0]
@20000
-
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.raddr[8:0]
@20000
-
@8022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0]
@20000
-
-
@200
-
@28
mclt_test_05.mclt16x16_bayer_i.dtt_out_we
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_last_dtt_out_ram_wa[8:0]
@20000
-
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@20000
-
-
@1401200
-membuf
@22
mclt_test_05.mclt16x16_bayer_i.dtt_r_ra[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
@8420
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start
mclt_test_05.mclt16x16_bayer_i.dtt_start_fill
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_out_we
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.dtt_dly_cntr[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wah[4:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_wa16[3:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.we
@c00022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.ren
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.regen
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r2[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r3[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r4[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r2[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r3[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r4[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
mclt_test_05.mclt16x16_bayer_i.inv_checker_r
mclt_test_05.mclt16x16_bayer_i.inv_checker_r2
mclt_test_05.mclt16x16_bayer_i.inv_checker_r3
mclt_test_05.mclt16x16_bayer_i.inv_checker_r4
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@1401200
-group_end
-mclt_bayer
[pattern_trace] 1
[pattern_trace] 0
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