Commit a26a7c72 authored by Andrey Filippov's avatar Andrey Filippov

merged with origin/framepars, includes updated SATA, bitsteram version 0x039300d3 (sata 0x0b)

parents 16bc2093 88f2b52d
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......@@ -39,7 +39,7 @@
*/
`timescale 1ns/1ps
//`define INSTANTIATE_DSP48E1
`undef INSTANTIATE_DSP48E1
//`undef INSTANTIATE_DSP48E1
module dsp_ma_preadd_c #(
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
......
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300d2; //parallel - fixing false trigger on input condition change -0.018/21, 80.28 %
parameter FPGA_VERSION = 32'h039300d3; //parallel - Updated SATA (v.0xb)
// parameter FPGA_VERSION = 32'h039300d2; //parallel - fixing false trigger on input condition change -0.018/21, 80.28 %
// parameter FPGA_VERSION = 32'h039300d1; //parallel - removed extra debug -0.042/9 80.34%
// parameter FPGA_VERSION = 32'h039300d1; //parallel - changing line_numbers_sync condition -0.011/3, 80.78 %
// parameter FPGA_VERSION = 32'h039300d0; //parallel - more status data
......
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000B001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h2;
localparam PCI_Header__RID__RID__DFLT = 'hb;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
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......@@ -498,7 +498,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
end
// HBA_PORT__PxCMD register - different behaviors of differtnt fields
// HBA_PORT__PxCMD register - different behaviors of different fields
// use PxCMD_MASK to prevent generation of unneeded register bits
always @(posedge mclk) begin
......
......@@ -394,7 +394,9 @@ module ahci_fsm
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0;
//// if (hba_rst || pre_jump_w) fsm_transitions <= 0;
/// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code
if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
......
......@@ -332,7 +332,8 @@ module axi_ahci_regs#(
end
always @ (hba_clk) begin
//// always @ (hba_clk) begin
always @ (posedge aclk) begin
was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]};
was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]};
end
......
/*!
* <b>Module:</b>action_decoder
* @file action_decoder.v
* @date 2016-03-12
* @author auto-generated file, see ahci_fsm_sequence_old.py
*
* @brief Decode sequencer code to 1-hot actions
* @file action_decoder.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
......
/*!
* <b>Module:</b>condition_mux
* @file condition_mux.v
* @date 2016-03-12
* @author auto-generated file, see ahci_fsm_sequence_old.py
*
* @brief Select condition
* @file condition_mux.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Select condition
*/
`timescale 1ns/1ps
......
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