Commit 9ff78344 authored by Andrey Filippov's avatar Andrey Filippov

added simuilation modules for frequency multiplication/division, fractional...

added simuilation modules for frequency multiplication/division, fractional period delays, started parallel12 -> HiSPi packetized SP converter
parent 0a729a6a
/*******************************************************************************
* Module: par12_hispi_psp4l
* Date:2015-10-11
* Author: andrey
* Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes
*
* Copyright (c) 2015 Elphel, Inc .
* par12_hispi_psp4l.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* par12_hispi_psp4l.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module par12_hispi_psp4l#(
parameter CLOCK_MPY = 10,
parameter CLOCK_DIV = 3,
parameter LANE0_DLY = 1.3,
parameter LANE1_DLY = 2.7,
parameter LANE2_DLY = 0.2,
parameter LANE3_DLY = 3.3,
parameter BLANK_LINES = 2,
parameter MAX_LINE = 8192
)(
input pclk,
input rst,
input [11:0] pxd,
input vact,
input hact,
output [3:0] lane_p,
output [3:0] lane_n,
output clk_p,
output clk_n
);
endmodule
/*******************************************************************************
* Module: sim_clk_div
* Date:2015-10-11
* Author: andrey
* Description: Divide clock frequency by integer number
*
* Copyright (c) 2015 Elphel, Inc .
* sim_clk_div.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sim_clk_div.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sim_clk_div#(
parameter DIVISOR = 5
) (
input clk_in,
input en,
output clk_out
);
integer cntr = 0;
reg clk_out_r = 0;
assign clk_out = clk_out_r;
always @(clk_in) if (en) begin
if (cntr == 0) begin
cntr = DIVISOR - 1;
clk_out_r = !clk_out_r;
end else begin
cntr = cntr - 1;
end
end
endmodule
/*******************************************************************************
* Module: sim_frac_clk_delay
* Date:2015-10-11
* Author: andrey
* Description: Delay clock-synchronous signal by fractional number of periods
*
* Copyright (c) 2015 Elphel, Inc .
* sim_frac_clk_delay.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sim_frac_clk_delay.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sim_frac_clk_delay #(
parameter FRAC_DELAY = 2.3, // periods of clock > 0.5
parameter SKIP_FIRST = 5 // skip first clock pulses
) (
input clk,
input din,
output dout
);
localparam integer INT_DELAY = $rtoi (FRAC_DELAY);
// localparam [0:0] HALF_DELAY = $rtoi(2.0 *(FRAC_DELAY - INT_DELAY));
localparam [0:0] HALF_DELAY = (FRAC_DELAY - INT_DELAY) >= 0.5;
localparam RDELAY = (FRAC_DELAY - INT_DELAY) - 0.5 * HALF_DELAY;
integer num_period = 0;
reg en = 0;
real phase;
real prev_phase = 0.0;
real frac_period = 0.0;
// measure period
always @ (posedge clk) begin
phase = $realtime;
if (num_period >= SKIP_FIRST) begin
frac_period = RDELAY* (phase - prev_phase);
en = 1;
end
prev_phase = phase;
if (!en) num_period = num_period + 1;
end
reg [INT_DELAY:0] sr = 0;
reg [INT_DELAY:0] sr_fract = 0;
wire [INT_DELAY+1:0] taps = {sr,din};
wire [INT_DELAY+1:0] taps_fract = {sr_fract,din};
reg dly_half;
// reg dly_int;
always @(posedge clk) if (en) begin
sr <= taps[INT_DELAY:0];
// #frac_period sr_fract <= taps[INT_DELAY:0];
#frac_period sr_fract <= sr;
end
always @(negedge clk) if (en) begin
#frac_period dly_half = taps[INT_DELAY];
end
// assign dout = dly_half;
// assign dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
// assign #frac_period dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
assign dout = HALF_DELAY ? dly_half : taps_fract[INT_DELAY];
// assign #(RDELAY*period) dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
endmodule
/*******************************************************************************
* Module: simul_clk_mult
* Date:2015-10-10
* Author: andrey
* Description: Clock multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_mult.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_mult.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_mult#(
parameter MULTIPLIER = 3,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
real phase;
real prev_phase = 0.0;
real out_half_period = 0.0;
integer num_period = 0;
reg en1 = 0;
reg clk_out_r = 0;
assign clk_out = clk_out_r;
always @ (posedge clk_in) begin
phase = $realtime;
if (num_period >= SKIP_FIRST) begin
out_half_period = (phase - prev_phase) / (2 * MULTIPLIER);
en1 = 1;
end
prev_phase = phase;
num_period = num_period + 1;
end
always @ (posedge clk_in) if (en && en1) begin
clk_out_r = 1;
repeat (MULTIPLIER - 1) begin
#out_half_period clk_out_r = 0;
#out_half_period clk_out_r = 1;
end
#out_half_period clk_out_r = 0;
end
endmodule
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Oct 10 04:26:57 2015 [*] Sun Oct 11 07:47:05 2015
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151009220220129.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151011014314914.fst"
[dumpfile_mtime] "Sat Oct 10 04:26:01 2015" [dumpfile_mtime] "Sun Oct 11 07:46:34 2015"
[dumpfile_size] 96721857 [dumpfile_size] 4050664
[savefile] "/home/andrey/git/x393/x393_testbench02.sav" [savefile] "/home/andrey/git/x393/x393_testbench02.sav"
[timestart] 65911000 [timestart] 16180200
[size] 1823 1180 [size] 1823 1180
[pos] 1922 0 [pos] 1922 0
*-17.835970 66537388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-15.742174 16339089 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench02. [treeopen] x393_testbench02.
[treeopen] x393_testbench02.compressor_control. [treeopen] x393_testbench02.compressor_control.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i. [treeopen] x393_testbench02.simul_axi_hp1_wr_i.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i.waddr_i. [treeopen] x393_testbench02.simul_axi_hp1_wr_i.waddr_i.
[treeopen] x393_testbench02.simul_saxi_gp0_wr_i. [treeopen] x393_testbench02.simul_clk_mult_i.
[treeopen] x393_testbench02.simul_saxi_gp0_wr_i.waddr_i. [treeopen] x393_testbench02.simul_saxi_gp0_wr_i.waddr_i.
[treeopen] x393_testbench02.simul_sensor12bits_i. [treeopen] x393_testbench02.simul_sensor12bits_i.
[treeopen] x393_testbench02.x393_i. [treeopen] x393_testbench02.x393_i.
...@@ -98,7 +98,7 @@ ...@@ -98,7 +98,7 @@
[treeopen] x393_testbench02.x393_i.timing393_i. [treeopen] x393_testbench02.x393_i.timing393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i. [treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i. [treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
[sst_width] 312 [sst_width] 232
[signals_width] 388 [signals_width] 388
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 611 [sst_vpaned_height] 611
...@@ -542,8 +542,134 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -542,8 +542,134 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-group_end -group_end
@1401200 @1401200
-sensor_channel -sensor_channel
@800200
-sim_clk_tests
@200 @200
- -
@800200
-simul_clk_mult
@28
x393_testbench02.PX1_MRST
@22
x393_testbench02.simul_clk_mult_i.prev_phase
x393_testbench02.simul_clk_mult_i.phase
x393_testbench02.simul_clk_mult_i.out_half_period
@28
x393_testbench02.simul_clk_mult_i.clk_in
x393_testbench02.simul_clk_mult_i.clk_out
x393_testbench02.simul_clk_mult_i.en
@1000200
-simul_clk_mult
@200
-
@28
x393_testbench02.PX1_MCLK_MULT_DIV
@c00022
x393_testbench02.PX1_DIV_CNTR[7:0]
@28
(0)x393_testbench02.PX1_DIV_CNTR[7:0]
(1)x393_testbench02.PX1_DIV_CNTR[7:0]
(2)x393_testbench02.PX1_DIV_CNTR[7:0]
(3)x393_testbench02.PX1_DIV_CNTR[7:0]
(4)x393_testbench02.PX1_DIV_CNTR[7:0]
(5)x393_testbench02.PX1_DIV_CNTR[7:0]
(6)x393_testbench02.PX1_DIV_CNTR[7:0]
(7)x393_testbench02.PX1_DIV_CNTR[7:0]
@1401200
-group_end
@800028
x393_testbench02.TEST_DLY[1:0]
@28
(1)x393_testbench02.TEST_DLY[1:0]
(0)x393_testbench02.TEST_DLY[1:0]
@1001200
-group_end
@800200
-sim_frac_clk_delay1
@28
x393_testbench02.sim_frac_clk_delay1_i.clk
x393_testbench02.sim_frac_clk_delay1_i.din
x393_testbench02.sim_frac_clk_delay1_i.dly_half
x393_testbench02.sim_frac_clk_delay1_i.dout
x393_testbench02.sim_frac_clk_delay1_i.en
@22
x393_testbench02.sim_frac_clk_delay1_i.frac_period
x393_testbench02.sim_frac_clk_delay1_i.num_period
x393_testbench02.sim_frac_clk_delay1_i.phase
x393_testbench02.sim_frac_clk_delay1_i.prev_phase
@800028
x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
@1001200
-group_end
@800028
x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
@1001200
-group_end
@c00022
x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(3)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
@1401200
-group_end
@c00022
x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(3)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
@1401200
-group_end
@1000200
-sim_frac_clk_delay1
@800200
-sim_frac_clk_delay2
@28
x393_testbench02.sim_frac_clk_delay2_i.clk
x393_testbench02.sim_frac_clk_delay2_i.din
x393_testbench02.sim_frac_clk_delay2_i.dly_half
x393_testbench02.sim_frac_clk_delay2_i.dout
x393_testbench02.sim_frac_clk_delay2_i.en
@22
x393_testbench02.sim_frac_clk_delay2_i.frac_period
x393_testbench02.sim_frac_clk_delay2_i.num_period
x393_testbench02.sim_frac_clk_delay2_i.phase
x393_testbench02.sim_frac_clk_delay2_i.prev_phase
@c00028
x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
(1)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
(2)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
@1401200
-group_end
@28
x393_testbench02.sim_frac_clk_delay2_i.sr_fract[2:0]
@c00022
x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(1)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(2)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(3)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
@1401200
-group_end
@22
x393_testbench02.sim_frac_clk_delay2_i.taps_fract[3:0]
@1000200
-sim_frac_clk_delay2
-sim_clk_tests
@c00200 @c00200
-sensor_channel_2 -sensor_channel_2
@28 @28
...@@ -4258,14 +4384,14 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -4258,14 +4384,14 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_r x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_r
@22 @22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
@800023 @800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@29 @28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0] (0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0] (1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0] (2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0] (3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@1001201 @1001200
-group_end -group_end
@28 @28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc
......
...@@ -1976,6 +1976,46 @@ simul_axi_hp_wr #( ...@@ -1976,6 +1976,46 @@ simul_axi_hp_wr #(
.ffclk1 ({ffclk1n, ffclk1p}) // output[1:0] .ffclk1 ({ffclk1n, ffclk1p}) // output[1:0]
); );
wire PX1_MCLK_MULT;
wire PX1_MCLK_MULT_DIV;
reg [7:0] PX1_DIV_CNTR = 0;
wire [1:0] TEST_DLY;
simul_clk_mult #(
.MULTIPLIER(3)
) simul_clk_mult_i (
.clk_in (PX1_MCLK), // input
.en (1'b1), // input
.clk_out (PX1_MCLK_MULT) // output reg
);
sim_clk_div #(
.DIVISOR (5)
) sim_clk_div_i (
.clk_in (PX1_MCLK_MULT), // input
.en (1'b1), // input
.clk_out (PX1_MCLK_MULT_DIV) // output
);
always @ (posedge PX1_MCLK_MULT_DIV) PX1_DIV_CNTR <= PX1_DIV_CNTR + 1;
sim_frac_clk_delay #(
.FRAC_DELAY(2.1),
.SKIP_FIRST(5)
) sim_frac_clk_delay1_i (
.clk(PX1_MCLK_MULT_DIV), // input
.din(PX1_DIV_CNTR[3]), // input
.dout(TEST_DLY[0]) // output
);
sim_frac_clk_delay #(
.FRAC_DELAY(2.9),
.SKIP_FIRST(5)
) sim_frac_clk_delay2_i (
.clk(PX1_MCLK_MULT_DIV), // input
.din(PX1_DIV_CNTR[3]), // input
.dout(TEST_DLY[1]) // output
);
simul_sensor12bits #( simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE), .lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......
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