tested register writes, status generation, routing and reading

.gitignore

@@ -8,3 +8,4 @@ IVERILOG_INCLUDE.v
 x393.prj
 *DEBUG_VDT*
 *.kate-swp
+*.old

address_map.txt

@@ -56,7 +56,23 @@
     parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1,    // 8-bit refresh period
     parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2,    // 10 bits refresh address in the sequencer (PL) memory
     parameter MCONTR_TOP_16BIT_STATUS_CNTRL=    'h3,    // 8 bits - write to status control (and debug?)
+0x1080..10ff
+  0x1080..10ff - DLY_LD   // 8 bits :
+  0x1080..109f - set delay for SDD0-SDD7
+  0x10a0..10bf - set delay for SDD8-SDD15
+  0x10c0..10df - set delay for SD_CMDA
+  0x10e0       - set delay for MMCM
 
+  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
+  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
+  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
+  localparam LD_DLY_LANE1_IDELAY = DLY_LD+'h30; // 0x10b0
+  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0
+  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0
+  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
+  
+  
+  
 ----
     parameter MCNTRL_TEST01_ADDR=       'h0f0,
     parameter MCNTRL_TEST01_MASK=       'h3f0

axi/axibram_read.v

@@ -18,6 +18,8 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
+ // Check that this fix did not break anything:
+`define USE_SHORT_REN_REGEN 
 module  axibram_read #(
     parameter ADDRESS_BITS = 10 // number of memory address bits
 )(
@@ -129,13 +131,24 @@ module  axibram_read #(
 // External memory interface
    assign  bram_rclk =  aclk;  // clock for read port
    assign  bram_raddr = read_in_progress?read_address[ADDRESS_BITS-1:0]:{ADDRESS_BITS{1'b1}};  // read address
+   
+`ifdef USE_SHORT_REN_REGEN   
+   reg bram_regen_r;
+   assign  bram_ren =   bram_reg_re_w && !pre_last_in_burst_r ;     // read port enable
+   assign  bram_regen = bram_regen_r;     // output register enable
+`else
    assign  bram_ren =   bram_reg_re_w;     // read port enable
    assign  bram_regen = bram_reg_re_w;     // output register enable
+`endif   
    
    assign  rdata[31:0] = bram_rdata;    // data out
 
     always @ (posedge  aclk or posedge  rst) begin
-    
+`ifdef USE_SHORT_REN_REGEN   
+      if   (rst)  bram_regen_r <= 0;
+      else        bram_regen_r <=  bram_ren;
+`endif    
+   
       if   (rst)                   pre_last_in_burst_r <= 0;
 //      else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
       else if (bram_reg_re_w)      pre_last_in_burst_r <= (read_left==4'b0);
@@ -227,6 +240,7 @@ fifo_same_clock   #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
     raddr_i (
         .rst(rst),
         .clk(aclk),
+        .sync_rst(1'b0), // input
         .we(arvalid && arready),
         .re(start_read_burst_w),
         .data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),

includes/x393_localparams.vh

-// SuppressWarnings VEditor
-/*
-    localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000  << 2
-// SuppressWarnings VEditor
-    localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
-///    localparam BASEADDR_CMD0 =     CMD0_ADDR << 2;     // 'h0800 << 2 = 'h2000
-//    localparam BASEADDR_CTRL =     CONTROL_ADDR << 2;
-///    localparam BASEADDR_CTRL =     (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
-    localparam BASEADDR_STATUS =   STATUS_ADDR << 2;   // 'h0800 << 2 = 'h2000
-///    localparam BASEADDR_DLY_LD =  BASEADDR_CTRL | (DLY_LD_REL <<2);  // 'h080, address to generate delay load
-    localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2);  // 'h070, address to generate delay set
-    localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2);  // 'h000, address to set sequnecer channel and  run (4 LSB-s - channel)
+// S uppressWarnings VEditor
+  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
+  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
+  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
+  localparam LD_DLY_LANE1_IDELAY = DLY_LD+'h30; // 0x10b0
+  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0
+  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0
+  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
 
-    localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
-    localparam BASEADDR_PATTERNS_TRI =BASEADDR_CTRL | (PATTERNS_TRI_REL<<2); // 'h021, address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
-    localparam BASEADDR_WBUF_DELAY =BASEADDR_CTRL | (WBUF_DELAY_REL<<2); // 'h022, extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
-// SuppressWarnings VEditor
-    localparam BASEADDR_PAGES =   BASEADDR_CTRL | (PAGES_REL<<2);    // 'h023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
-    localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2);  // 'h024, address to enable('h825)/disable('h824) command/address outputs  
-    localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // 'h026 address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory     
-///    localparam BASEADDR_CKE_EN =  BASEADDR_CTRL | (CKE_EN_REL<<2);   // 'h028
-    
-// SuppressWarnings VEditor
-    localparam BASEADDR_DCI_RST =  BASEADDR_CTRL | (DCI_RST_REL<<2);   // 'h02a (+1 - enable)
-// SuppressWarnings VEditor
-    localparam BASEADDR_DLY_RST =  BASEADDR_CTRL | (DLY_RST_REL<<2);   // 'h02c (+1 - enable)
-      
-// SuppressWarnings VEditor
-    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h02e, address to set extra parameters (currently just inv_clk_div)
-    
-    localparam BASEADDR_REFRESH_EN =   BASEADDR_CTRL | (REFRESH_EN_REL<<2);    // address to enable('h31) and disable ('h30) DDR refresh
-    localparam BASEADDR_REFRESH_PER =   BASEADDR_CTRL | (REFRESH_PER_REL<<2);    // address ('h32) to set refresh period in 32 x tCK
-    localparam BASEADDR_REFRESH_ADDR =   BASEADDR_CTRL | (REFRESH_ADDR_REL<<2);    // address ('h33)to set sequencer start address for DDR refresh
-    
-    
-    localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;  
-    localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);  
-    localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);  
-    localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);  
-
-    localparam BASEADDRESS_CMDA  = BASEADDR_DLY_LD+('h40<<2);
-    localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
-    localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
-// SuppressWarnings VEditor - not yet used
-    localparam STATUS_LOCKED_MASK = 'h200;
-    localparam STATUS_SEQ_BUSY_MASK = 'h400;
-*/
 `ifdef use200Mhz
     localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
     localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

includes/x393_tasks01.vh

@@ -16,6 +16,13 @@
         end
     endtask
 
+    task read_and_wait_w;
+    input [29:0] address;
+        begin
+            read_and_wait ({address,2'b0});
+        end
+    endtask
+
     task read_and_wait;
     input [31:0] address;
     begin
@@ -32,6 +39,14 @@
     end
     endtask
     
+    task axi_write_single_w; // address in bytes, not words
+        input [29:0] address;
+        input [31:0] data;
+        begin
+            axi_write_single ({address,2'b0},data);
+        end
+    endtask
+
     task axi_write_single; // address in bytes, not words
         input [31:0] address;
         input [31:0] data;

memctrl/mcntrl393.v

@@ -251,6 +251,7 @@ module  mcntrl393 #(
     input                        axird_regen, //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
 //   wire  [31:0]   axird_bram_rdata;  //      .data_out(rdata[31:0]),       // data out
     output              [31:0]   axird_rdata,  // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
+    output                       axird_selected, // axird_rdata contains cvalid data from this module 
 //   wire  [31:0]   port0_rdata;  //
 //   wire  [31:0]   status_rdata;  //
 
@@ -415,7 +416,14 @@ module  mcntrl393 #(
     wire                        status_tiled_chn4_rq;    // PS tiled channel4 (memory read) channels status request  
     wire                        status_tiled_chn4_start; // PS tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
 
-
+// combinatorial early signals
+    wire                         select_cmd0_w;
+    wire                         select_buf0_w;
+    wire                         select_buf1_w;
+    wire                         select_buf2_w;
+    wire                         select_buf3_w;
+    wire                         select_buf4_w;
+// registered selects
     reg                         select_cmd0;
     reg                         select_buf0;
     reg                         select_buf1;
@@ -427,7 +435,7 @@ module  mcntrl393 #(
     reg                         select_buf2_d;
     reg                         select_buf4_d;
 
-    
+    reg                         axird_selected_r; // this module provides output
     
 // Buffers R/W from AXI
     reg   [BUFFER_DEPTH32-1:0]  buf_waddr;
@@ -513,7 +521,7 @@ module  mcntrl393 #(
 
     
     
-// Ror now - combinatorial, maybe add registers (modify axibram_read)
+// For now - combinatorial, maybe add registers (modify axibram_read)
     assign buf_raddr=axird_raddr;    
     assign axird_rdata = (select_buf0 ? buf0_data : 32'b0) | (select_buf2 ? buf2_data : 32'b0) | (select_buf4 ? buf4_data : 32'b0); 
     
@@ -527,25 +535,37 @@ module  mcntrl393 #(
     assign page_ready_chn2=seq_done2;
     assign page_ready_chn3=seq_done3;
     assign page_ready_chn4=rpage_nxt_chn4;
+    
+    
+    assign axird_selected=axird_selected_r;
+    assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf0_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
+    assign select_buf1_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf2_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
+    assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
 
     always @ (axi_rst or axi_clk) begin
         if      (axi_rst)           select_cmd0 <= 0;
-        else if (axiwr_start_burst) select_cmd0 <= ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
         
         if      (axi_rst)           select_buf0 <= 0;
-        else if (axird_start_burst) select_buf0 <= ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf0 <= select_buf0_w;
         
         if      (axi_rst)           select_buf1 <= 0;
-        else if (axiwr_start_burst) select_buf1 <= ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_buf1 <= select_buf1_w;
         
         if      (axi_rst)           select_buf2 <= 0;
-        else if (axird_start_burst) select_buf2 <= ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf2 <= select_buf2_w;
         
         if      (axi_rst)           select_buf3 <= 0;
-        else if (axiwr_start_burst) select_buf3 <= ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_buf3 <= select_buf3_w;
         
         if      (axi_rst)           select_buf4 <= 0;
-        else if (axird_start_burst) select_buf4 <= ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf4 <= select_buf4_w;
+
+        if      (axi_rst)           axird_selected_r <= 0;
+        else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w;
     end
     always @ (axi_clk) begin
         if (axiwr_wen) buf_wdata  <= axiwr_data;

status_read.v

@@ -36,10 +36,18 @@ module  status_read#(
 )(
     input rst,
     input clk,
-    input [AXI_RD_ADDR_BITS-1:0] axi_pre_addr,     // status read address, 1 cycle ahead of read data
-    input                        pre_stb,          // read data request, with axi_pre_addr
-    output reg            [31:0] axi_status_rdata, // read data, 1 cycle latency from the address/stb
-    output reg                   data_valid,       // read data valid, 1 cycle latency from pre_stb, decoded address
+    input                        axi_clk,   // common for read and write channels
+    input [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr,     // status read address, 1 cycle ahead of read data
+//    input                        pre_stb,          // read data request, with axi_pre_addr
+//    output reg            [31:0] axi_status_rdata, // read data, 1 cycle latency from the address/stb
+//    output reg                   data_valid,       // read data valid, 1 cycle latency from pre_stb, decoded address
+    input                        axird_start_burst, // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
+    input     [STATUS_DEPTH-1:0] axird_raddr, //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
+    input                        axird_ren,   //      .ren(bram_reg_re_w) ,      // read port enable
+    input                        axird_regen, //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
+    output              [31:0]   axird_rdata,  // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
+    output                       axird_selected, // axird_rdata contains cvalid data from this module, vcalid next after axird_start_burst
+                                                 // so with ren/regen it may be delayed 1 more cycle
     input                  [7:0] ad,               // byte-serial status data from the sources
     input                        rq,               // request from sources to transfer status data
     output                       start             // acknowledge receiving of first byte (address), currently always ready
@@ -47,20 +55,61 @@ module  status_read#(
     localparam integer DATA_2DEPTH=(1<<STATUS_DEPTH)-1;
     reg  [31:0] ram [0:DATA_2DEPTH];
     reg         [STATUS_DEPTH-1:0] waddr;
-    wire        [STATUS_DEPTH-1:0] raddr;
+//    wire        [STATUS_DEPTH-1:0] raddr;
     reg                          we;
-    wire                         re;
+//    wire                         re;
     reg                  [31: 0] wdata;
     reg                          rq_r;
     reg                   [3:0]  dstb;
     
-    assign re= pre_stb && (((axi_pre_addr ^ STATUS_ADDR) & STATUS_ADDR_MASK) == 0);
-    assign raddr=axi_pre_addr[STATUS_DEPTH-1:0];
+    wire                         select_w;
+    reg                          select_r;
+    reg                          select_d;
+    
+    wire                         rd;
+    wire                         regen;
+    reg                 [31:0]   axi_status_rdata; 
+    reg                 [31:0]   axi_status_rdata_r;
+    
+// registering to match BRAM timing (so it is possible to instantioate it instead)    
+//    reg       [STATUS_DEPTH-1:0] raddr_r; //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
+//    reg                          rd_r;   //      .ren(bram_reg_re_w) ,      // read port enable
+//    reg                          regen_r; //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
+   
+    
+    
+    assign select_w = ((axird_pre_araddr ^ STATUS_ADDR) & STATUS_ADDR_MASK)==0;
+    assign rd =        axird_ren   && select_r;
+    assign regen =     axird_regen && select_d;
+    
+    
+    
+    
+//    assign re= pre_stb && (((axi_pre_addr ^ STATUS_ADDR) & STATUS_ADDR_MASK) == 0);
+//    assign raddr=axi_pre_addr[STATUS_DEPTH-1:0];
     assign start=rq && !rq_r;
+    assign axird_rdata=axi_status_rdata_r;
+    assign axird_selected = select_r; 
+    always @ (posedge rst or posedge axi_clk) begin
+        if      (rst)               select_r <= 0;
+        else if (axird_start_burst) select_r <= select_w;
+    end
+    always @ (posedge axi_clk) begin
+//        if (rd_r)     axi_status_rdata <= ram[raddr_r];
+//        if (regen_r)  axi_status_rdata_r <= axi_status_rdata;
+        if (rd)       axi_status_rdata <= ram[axird_raddr];
+        if (regen)    axi_status_rdata_r <= axi_status_rdata;
+        
+        select_d <=   select_r;
+//        raddr_r <=   axird_raddr;
+//        rd_r <=      rd;
+//        regen_r <=   regen;
+    end
     
     always @ (posedge rst or posedge clk) begin
-        if (rst) data_valid <= 0;
-        else     data_valid <= re;
+    
+//        if (rst) data_valid <= 0;
+//        else     data_valid <= re;
         
         if (rst) rq_r <= 0;
         else     rq_r <= rq;
@@ -99,8 +148,7 @@ module  status_read#(
     end
     
     always @ (posedge clk) begin
-        if (we)  ram[waddr]  <= wdata; // shifted data here
-        if (re)  axi_status_rdata<= ram[raddr];
+        if (we)     ram[waddr]  <= wdata; // shifted data here
     end
                              
 

util_modules/status_router2.v

@@ -70,7 +70,8 @@ module  status_router2 (
 ///    assign snd_pre_start=|fifo_nempty && !snd_rest_r && !start_out; // no channel change after 
 //    assign rq_out=(snd_rest_r && !snd_last_byte) || |fifo_nempty;
     assign rq_out=(snd_rest_r || |fifo_nempty) && !snd_last_byte ;
-    assign early_chn= (snd_rest_r & ~snd_last_byte)?current_chn_r:chn_sel_w;
+//    assign early_chn= (snd_rest_r & ~snd_last_byte)?current_chn_r:chn_sel_w;
+    assign early_chn= snd_rest_r? current_chn_r: chn_sel_w;
     assign db_out=early_chn?fifo1_out:fifo0_out;
     assign fifo_nempty=fifo_nempty_pre & ~fifo_last_byte;
     

x393.v

@@ -349,21 +349,25 @@ module  x393 #(
    wire  [31:0]   axird_rdata;  //      .data_out(rdata[31:0]),       // data out
 //   wire  [31:0]   port0_rdata;  //
    wire  [31:0]   status_rdata;  //
-   wire           status_valid; /// SuppressThisWarning VEditor ****** never used - supposed to be always valid?
+   wire           status_selected;
+   wire  [31:0]   mcntrl_axird_rdata; // read data from the memory controller 
+   wire           mcntrl_axird_selected; // memory controoler has valid data output on mcntrl_axird_rdata 
 
    wire        mclk;
 
    wire [11:0] tmp_debug; 
    
 //   reg    select_port0; // May be used later!
-   reg  select_status;
    wire axiwr_dev_busy;
    wire axird_dev_busy;
    
    assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
    assign axird_dev_busy = 1'b0; // always for now
-//   assign axird_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
-   assign axird_rdata= select_status?status_rdata[31:0]:32'bx;
+// Use this later    
+//   assign axird_rdata= ({32{status_selected}} & status_rdata[31:0]) | ({32{mcntrl_axird_selected}} & mcntrl_axird_rdata[31:0]);
+//Debug with this (to show 'x)   
+   assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
+   
    assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
 
 // Clock and reset from PS
@@ -378,17 +382,6 @@ module  x393 #(
 BUFG bufg_axi_rst_i   (.O(axi_rst),.I(axi_rst_pre));
 BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
    
-//always @ (posedge axi_aclk) begin
-//   port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
-//end
-
-always @ (posedge axi_rst or posedge axi_aclk) begin
- //   if (axi_rst) select_port0 <= 1'b0;
- //   else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
-    if (axi_rst) select_status <= 1'b0;
-    else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
-    
-end
 
 `ifdef DEBUG_FIFO
         wire    waddr_under, wdata_under, wresp_under; 
@@ -593,15 +586,18 @@ end
     ) status_read_i (
         .rst              (axi_rst), // input
         .clk              (mclk), // input
-        .axi_pre_addr     (axird_pre_araddr), // input[12:0] 
-        .pre_stb          (axird_start_burst), // input
-        .axi_status_rdata (status_rdata[31:0]), // output[31:0] reg 
-        .data_valid       (status_valid), // output reg 
+        .axi_clk          (axird_bram_rclk), // input == axi_aclk
+        .axird_pre_araddr (axird_pre_araddr), // input[7:0] 
+        .axird_start_burst(axird_start_burst), // input
+        .axird_raddr      (axird_raddr[STATUS_DEPTH-1:0]), // input[7:0] 
+        .axird_ren        (axird_ren), // input
+        .axird_regen      (axird_regen), // input
+        .axird_rdata      (status_rdata), // output[31:0] 
+        .axird_selected   (status_selected), // output
         .ad               (status_root_ad), // input[7:0] 
         .rq               (status_root_rq), // input
         .start            (status_root_start) // output
     );
-    
 
 // mux status info from the memory controller and other modules    
     status_router2 status_router2_top_i (
@@ -748,7 +744,7 @@ end
         .status_rq            (status_mcontr_rq),   // input request to send status downstream
         .status_start         (status_mcontr_start), // Acknowledge of the first status packet byte (address)
         
-        .axi_clk              (axi_aclk), // input - same?
+        .axi_clk              (axird_bram_rclk), // axi_aclk), // input - same?
         .axiwr_pre_awaddr     (axiwr_pre_awaddr), // input[12:0] 
         .axiwr_start_burst    (axiwr_start_burst), // input
         .axiwr_waddr          (axiwr_waddr[BUFFER_DEPTH32-1:0]), // input[9:0] 
@@ -760,8 +756,8 @@ end
         .axird_raddr          (axird_raddr[BUFFER_DEPTH32-1:0]), // input[9:0] 
         .axird_ren            (axird_ren), // input
         .axird_regen          (axird_regen), // input
-        .axird_rdata          (axird_rdata), // output[31:0]
- 
+        .axird_rdata          (mcntrl_axird_rdata), // output[31:0]
+        .axird_selected       (mcntrl_axird_selected), // output 
  //TODO:        
         .frame_start_chn2     (frame_start_chn2), // input
         .next_page_chn2       (next_page_chn2), // input
@@ -959,7 +955,7 @@ frst[3]?{
         .pre_araddr  (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0] 
         .start_burst (axird_start_burst), // output
         .dev_ready   (axird_dev_ready), // input
-        .bram_rclk   (axird_bram_rclk), // output //SuppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
+        .bram_rclk   (axird_bram_rclk), // output //S uppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
         .bram_raddr  (axird_raddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0] 
         .bram_ren    (axird_ren), // output
         .bram_regen  (axird_regen), // output

x393_testbench01.sav

 [*]
 [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
-[*] Mon Feb  9 18:37:25 2015
+[*] Tue Feb 10 02:20:51 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150209110942833.lxt"
-[dumpfile_mtime] "Mon Feb  9 18:17:39 2015"
-[dumpfile_size] 144866360
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150209170430851.lxt"
+[dumpfile_mtime] "Tue Feb 10 00:05:13 2015"
+[dumpfile_size] 11536611
 [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
-[timestart] 99878000
-[size] 1823 1180
+[timestart] 100326000
+[size] 1823 1173
 [pos] 1922 0
-*-18.878319 101716250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-19.878319 102981300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench01.
 [treeopen] x393_testbench01.x393_i.
-[treeopen] x393_testbench01.x393_i.mcntrl393_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
-[treeopen] x393_testbench01.x393_i.status_router2_top_i.
 [sst_width] 282
-[signals_width] 342
+[signals_width] 395
 [sst_expanded] 1
 [sst_vpaned_height] 371
+@800200
+-top_simulation
+@22
+x393_testbench01.registered_rdata[31:0]
+x393_testbench01.read_and_wait_status.address[7:0]
+x393_testbench01.x393_i.status_rdata[31:0]
+x393_testbench01.x393_i.axird_rdata[31:0]
+@1000200
+-top_simulation
+@200
+-
 @c00200
 -axi
 @28
@@ -169,49 +178,62 @@ x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0]
 x393_testbench01.x393_i.cmd_mux_i.wr_en[0]
 @1401200
 -cmd_mux
-@c00200
+@800200
 -status_read
 @22
 x393_testbench01.x393_i.status_read_i.ad[7:0]
-x393_testbench01.x393_i.status_read_i.axi_pre_addr[12:0]
-x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0]
 @28
+x393_testbench01.x393_i.status_read_i.axi_clk[0]
+@22
+x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0]
+x393_testbench01.x393_i.status_read_i.axi_status_rdata_r[31:0]
+x393_testbench01.x393_i.status_read_i.axird_pre_araddr[12:0]
+x393_testbench01.x393_i.status_read_i.axird_raddr[7:0]
+x393_testbench01.x393_i.status_read_i.axird_rdata[31:0]
+@28
+x393_testbench01.x393_i.status_read_i.axird_regen[0]
+x393_testbench01.x393_i.status_read_i.axird_ren[0]
+x393_testbench01.x393_i.status_read_i.axird_selected[0]
+x393_testbench01.x393_i.status_read_i.axird_start_burst[0]
 x393_testbench01.x393_i.status_read_i.clk[0]
-x393_testbench01.x393_i.status_read_i.data_valid[0]
 @22
 x393_testbench01.x393_i.status_read_i.dstb[3:0]
 @28
-x393_testbench01.x393_i.status_read_i.pre_stb[0]
-@22
-x393_testbench01.x393_i.status_read_i.raddr[7:0]
-@28
-x393_testbench01.x393_i.status_read_i.re[0]
+x393_testbench01.x393_i.status_read_i.rd[0]
+x393_testbench01.x393_i.status_read_i.regen[0]
 x393_testbench01.x393_i.status_read_i.rq[0]
 x393_testbench01.x393_i.status_read_i.rq_r[0]
 x393_testbench01.x393_i.status_read_i.rst[0]
+x393_testbench01.x393_i.status_read_i.select_d[0]
+x393_testbench01.x393_i.status_read_i.select_r[0]
+x393_testbench01.x393_i.status_read_i.select_w[0]
 x393_testbench01.x393_i.status_read_i.start[0]
 @22
 x393_testbench01.x393_i.status_read_i.waddr[7:0]
 x393_testbench01.x393_i.status_read_i.wdata[31:0]
 @28
 x393_testbench01.x393_i.status_read_i.we[0]
-@1401200
+@1000200
 -status_read
-@800200
+@c00200
 -status_router_top
 @28
 x393_testbench01.x393_i.status_router2_top_i.chn_sel_w[0]
+x393_testbench01.x393_i.status_router2_top_i.current_chn_r[0]
 x393_testbench01.x393_i.status_router2_top_i.clk[0]
 x393_testbench01.x393_i.status_router2_top_i.rq_in0[0]
 x393_testbench01.x393_i.status_router2_top_i.start_in0[0]
+@22
+x393_testbench01.x393_i.status_router2_top_i.db_in0[7:0]
+@28
 x393_testbench01.x393_i.status_router2_top_i.rq_in1[0]
 x393_testbench01.x393_i.status_router2_top_i.start_in1[0]
+@22
+x393_testbench01.x393_i.status_router2_top_i.db_in1[7:0]
+@28
 x393_testbench01.x393_i.status_router2_top_i.rq_out[0]
 x393_testbench01.x393_i.status_router2_top_i.start_out[0]
-x393_testbench01.x393_i.status_router2_top_i.current_chn_r[0]
 @22
-x393_testbench01.x393_i.status_router2_top_i.db_in0[7:0]
-x393_testbench01.x393_i.status_router2_top_i.db_in1[7:0]
 x393_testbench01.x393_i.status_router2_top_i.db_out[7:0]
 @28
 x393_testbench01.x393_i.status_router2_top_i.early_chn[0]
@@ -256,7 +278,7 @@ x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0]
 (1)x393_testbench01.x393_i.status_router2_top_i.start_rcv[1:0]
 @1001200
 -group_end
-@1000200
+@1401200
 -status_router_top
 @c00200
 -status_router16_mctrl_top
@@ -324,23 +346,28 @@ x393_testbench01.x393_i.mcntrl393_i.status_router16_mctrl_top_i.start_out[0]
 -memcntrl16_status_router2_top
 @28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.chn_sel_w[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.current_chn_r[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.early_chn[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.clk[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in0[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in0[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in0[7:0]
+@28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in1[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_in1[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in1[7:0]
+@28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_out[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_out[0]
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.current_chn_r[0]
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_last_byte[0]
-(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
-(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
 @22
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in0[7:0]
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_in1[7:0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.db_out[7:0]
 @28
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.early_chn[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_last_byte[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_rest_r[0]
+(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
+(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo_nempty_pre[1:0]
 @22
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo0_out[7:0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.fifo1_out[7:0]
@@ -371,7 +398,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rcv_rest_r[
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rq_in[1:0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.rst[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_pre_start[0]
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.snd_rest_r[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.start_rcv[1:0]
 @1401200
 -memcntrl16_status_router2_top
@@ -385,9 +411,8 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked_pll[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.locked[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_rdy[0]
-@23
-x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_out[7:0]
 @22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ps_out[7:0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.ad[7:0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.status_generate_i.aligned_status[17:0]
 @28
@@ -608,7 +633,83 @@ x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.status_router2_01_i.
 -group_end
 @1401200
 -test01_status_router2_01
-@200
--
+@800200
+-axibram_read
+@28
+x393_testbench01.x393_i.axibram_read_i.aclk[0]
+x393_testbench01.x393_i.axibram_read_i.ar_half_full[0]
+x393_testbench01.x393_i.axibram_read_i.ar_nempty[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.araddr[31:0]
+x393_testbench01.x393_i.axibram_read_i.araddr_out[12:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.arburst[1:0]
+x393_testbench01.x393_i.axibram_read_i.arburst_out[1:0]
+@22
+x393_testbench01.x393_i.axibram_read_i.arid[11:0]
+x393_testbench01.x393_i.axibram_read_i.arid_out[11:0]
+x393_testbench01.x393_i.axibram_read_i.arlen[3:0]
+x393_testbench01.x393_i.axibram_read_i.arlen_out[3:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.arready[0]
+x393_testbench01.x393_i.axibram_read_i.arsize[1:0]
+x393_testbench01.x393_i.axibram_read_i.arsize_out[1:0]
+x393_testbench01.x393_i.axibram_read_i.arvalid[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.bram_raddr[12:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.bram_rclk[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.bram_rdata[31:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.bram_reg_re_0[0]
+x393_testbench01.x393_i.axibram_read_i.bram_reg_re_w[0]
+x393_testbench01.x393_i.axibram_read_i.bram_regen[0]
+x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
+x393_testbench01.x393_i.axibram_read_i.dev_ready[0]
+x393_testbench01.x393_i.axibram_read_i.last_in_burst_0[0]
+x393_testbench01.x393_i.axibram_read_i.last_in_burst_1[0]
+x393_testbench01.x393_i.axibram_read_i.last_in_burst_d_w[0]
+@29
+x393_testbench01.x393_i.axibram_read_i.last_in_burst_w[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.next_rd_address_w[12:0]
+x393_testbench01.x393_i.axibram_read_i.pre_araddr[12:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.pre_last_in_burst_r[0]
+x393_testbench01.x393_i.axibram_read_i.pre_left_zero_w[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.pre_rid0[11:0]
+x393_testbench01.x393_i.axibram_read_i.pre_rid[11:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.pre_rvalid_w[0]
+x393_testbench01.x393_i.axibram_read_i.rburst[1:0]
+@22
+x393_testbench01.x393_i.axibram_read_i.rdata[31:0]
+x393_testbench01.x393_i.axibram_read_i.read_address[12:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.read_in_progress[0]
+x393_testbench01.x393_i.axibram_read_i.read_in_progress_d[0]
+x393_testbench01.x393_i.axibram_read_i.read_in_progress_d_w[0]
+x393_testbench01.x393_i.axibram_read_i.read_in_progress_or[0]
+x393_testbench01.x393_i.axibram_read_i.read_in_progress_w[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.read_left[3:0]
+x393_testbench01.x393_i.axibram_read_i.rid[11:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.rlast[0]
+@22
+x393_testbench01.x393_i.axibram_read_i.rlen[3:0]
+@28
+x393_testbench01.x393_i.axibram_read_i.rready[0]
+x393_testbench01.x393_i.axibram_read_i.rresp[1:0]
+x393_testbench01.x393_i.axibram_read_i.rst[0]
+x393_testbench01.x393_i.axibram_read_i.rvalid[0]
+x393_testbench01.x393_i.axibram_read_i.start_burst[0]
+x393_testbench01.x393_i.axibram_read_i.start_read_burst_0[0]
+x393_testbench01.x393_i.axibram_read_i.start_read_burst_1[0]
+x393_testbench01.x393_i.axibram_read_i.start_read_burst_w[0]
+@1000200
+-axibram_read
 [pattern_trace] 1
 [pattern_trace] 0

x393_testbench01.tf

@@ -87,7 +87,7 @@ module  x393_testbench01 #(
   // SuppressWarnings VEditor
   reg         SIMUL_AXI_FULL; // some data available
 
-  reg  [31:0] registered_rdata;
+  reg  [31:0] registered_rdata; // here read data from tasks goes
 
   reg        CLK;
   reg        RST;
@@ -201,9 +201,15 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 //set simulation-only parameters   
     axi_set_b_lag(0); //(1);
     axi_set_rd_lag(0);
-    program_status_all(3); // mode auto with sequence number increment 
+    program_status_all(3,'h2a); // mode auto with sequence number increment 
 //...    
+    set_up;
     
+    read_all_status;    
+    repeat (20) @(posedge CLK) ;
+    read_all_status;    
+  #2000;
+  $finish;
 end
 // protect from never end
   initial begin
@@ -765,18 +771,212 @@ simul_axi_read simul_axi_read_i(
   reg DEBUG1, DEBUG2, DEBUG3;
   reg [11:0] GLOBAL_WRITE_ID=0;
   reg [11:0] GLOBAL_READ_ID=0;
+  reg [7:0] target_phase=0; // to compare/wait for phase shifter ready
+  
+   task set_up;
+        begin
+// set dq /dqs tristate on/off patterns
+            axi_set_tristate_patterns;
+// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
+            axi_set_dqs_dqm_patterns;
+// prepare all sequences
+/*           set_all_sequences; */
+// prepare write buffer    
+/*            write_block_buf; // fill block memory */
+// set all delays
+//#axi_set_delays - from tables, per-pin
+            axi_set_same_delays(DLY_DQ_IDELAY,DLY_DQ_ODELAY,DLY_DQS_IDELAY,DLY_DQS_ODELAY,DLY_DM_ODELAY,DLY_CMDA_ODELAY);    
+// set clock phase relative to DDR clk
+            axi_set_phase(DLY_PHASE);
+        end
+    endtask
+
+/*
+task set_all_sequences;
+        begin
+            $display("SET MRS @ %t",$time);    
+            set_mrs(1);
+            $display("SET REFRESH @ %t",$time);    
+            set_refresh(
+                50, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
+                16); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
+            $display("SET WRITE LEVELING @ %t",$time);    
+            set_write_lev(16); // write leveling, 16 times   (full buffer - 128) 
+            $display("SET READ PATTERN @ %t",$time);    
+            set_read_pattern(8); // 8x2*64 bits, 32x32 bits to read
+
+            $display("SET WRITE BLOCK @ %t",$time);    
+            set_write_block(
+                3'h5,     // bank
+                15'h1234, // row address
+                10'h100   // column address
+            );
+           
+            $display("SET READ BLOCK @ %t",$time);    
+            set_read_block(
+                3'h5,     // bank
+                15'h1234, // row address
+                10'h100   // column address
+            );
+        end
+endtask
+*/ 
+ 
+     task axi_set_same_delays;
+        input [7:0] dq_idelay;
+        input [7:0] dq_odelay;
+        input [7:0] dqs_idelay;
+        input [7:0] dqs_odelay;
+        input [7:0] dm_odelay;
+        input [7:0] cmda_odelay;
+        begin
+           $display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
+           dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
+            axi_set_dq_idelay(dq_idelay);
+            axi_set_dq_odelay(dq_odelay);
+            axi_set_dqs_idelay(dqs_idelay);
+            axi_set_dqs_odelay(dqs_odelay);
+            axi_set_dm_odelay(dm_odelay);
+            axi_set_cmda_odelay(cmda_odelay);
+        end
+    endtask
+
+    task axi_set_dq_idelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQ IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_IDELAY, 8, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_IDELAY, 8, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dq_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQ ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY, 8, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY, 8, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dqs_idelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQS IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_IDELAY + 8, 0, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_IDELAY + 8, 0, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dqs_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQS ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 8, 0, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 8, 0, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_dm_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET DQM IDELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 9, 0, delay);
+           axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 9, 0, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+    task axi_set_cmda_odelay;
+        input [7:0] delay;
+        begin
+           $display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
+           axi_set_multiple_delays(LD_DLY_CMDA, 32, delay);
+           write_contol_register(DLY_SET,0); // set all delays
+        end
+    endtask
+
+
+    task axi_set_multiple_delays;
+        input [29:0] reg_addr;
+        input integer number;
+        input [7:0]  delay;
+        integer i;
+        begin
+           for (i=0;i<number;i=i+1) begin
+                write_contol_register(reg_addr + i, {24'b0,delay}); // control regiter address
+           end
+        end
+    endtask
+
+    task axi_set_phase;
+        input [PHASE_WIDTH-1:0] phase;
+        begin
+            $display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
+            write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
+            write_contol_register(DLY_SET,0);
+            target_phase <= phase;
+        end
+    endtask
+ 
+ 
+// set dq /dqs tristate on/off patterns
+    task axi_set_tristate_patterns;
+        begin
+            $display("SET TRISTATE PATTERNS @ %t",$time);    
+            write_contol_register(MCONTR_PHY_16BIT_ADDR +MCONTR_PHY_16BIT_PATTERNS_TRI,
+                {16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
+        end
+    endtask
+
+ task axi_set_dqs_dqm_patterns;
+        begin
+            $display("SET DQS+DQM PATTERNS @ %t",$time);    
+ // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)        
+            write_contol_register(MCONTR_PHY_16BIT_ADDR + MCONTR_PHY_16BIT_PATTERNS,
+                32'h0055);
+        end
+ endtask
+ 
+ task read_all_status;
+    begin
+        read_and_wait_status (MCONTR_PHY_STATUS_REG_ADDR);
+        read_and_wait_status (MCONTR_TOP_STATUS_REG_ADDR);
+        read_and_wait_status (MCNTRL_PS_STATUS_REG_ADDR);
+        read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR);
+        read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
+        read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
+        read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
+        read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
+        read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
+    end
+ endtask 
+  
+ task read_and_wait_status;
+    input [STATUS_DEPTH-1:0] address;
+    begin
+        read_and_wait_w(STATUS_ADDR + address ); // Will set:       registered_rdata <= rdata;
+    end
+ endtask
+  
+  
  task program_status_all;
     input [1:0] mode;
+    input [5:0] seq_num;
     begin
-        program_status (MCONTR_PHY_16BIT_ADDR,     MCONTR_PHY_STATUS_CNTRL,        mode,0); //MCONTR_PHY_STATUS_REG_ADDR=          'h0,
-        program_status (MCONTR_TOP_16BIT_ADDR,     MCONTR_TOP_16BIT_STATUS_CNTRL,  mode,0); //MCONTR_TOP_STATUS_REG_ADDR=          'h1,
-        program_status (MCNTRL_PS_ADDR,            MCNTRL_PS_STATUS_CNTRL,         mode,0); //MCNTRL_PS_STATUS_REG_ADDR=           'h2,
-        program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,0); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
-        program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,0); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
-        program_status (MCNTRL_TILED_CHN4_ADDR,    MCNTRL_TILED_STATUS_CNTRL,      mode,0); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
-        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
-        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,
-        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
+        program_status (MCONTR_PHY_16BIT_ADDR,     MCONTR_PHY_STATUS_CNTRL,        mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR=          'h0,
+        program_status (MCONTR_TOP_16BIT_ADDR,     MCONTR_TOP_16BIT_STATUS_CNTRL,  mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR=          'h1,
+        program_status (MCNTRL_PS_ADDR,            MCNTRL_PS_STATUS_CNTRL,         mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR=           'h2,
+        program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
+        program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL,   mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
+        program_status (MCNTRL_TILED_CHN4_ADDR,    MCNTRL_TILED_STATUS_CNTRL,      mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR=   'h6,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,
+        program_status (MCNTRL_TEST01_ADDR,        MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
     end
  endtask
   
@@ -791,10 +991,21 @@ simul_axi_read simul_axi_read_i(
  // 3 - auto, inc sequence number 
     input  [5:0] seq_number;
     begin
-        axi_write_single(((CONTROL_ADDR+{2'b0,base_addr}+reg_addr)<<2), {24'b0,mode,seq_number});
+//        axi_write_single_w(CONTROL_ADDR+base_addr+reg_addr, {24'b0,mode,seq_number});
+        write_contol_register(base_addr + reg_addr, {24'b0,mode,seq_number});
     end
  endtask   
     
+ task   write_contol_register;
+    input [29:0] reg_addr;
+//    input [29:0] base_addr;
+//    input  [7:0] reg_addr;
+    input [31:0] data;
+    begin
+//        axi_write_single_w(CONTROL_ADDR+base_addr+reg_addr, data);
+        axi_write_single_w(CONTROL_ADDR+reg_addr, data);
+    end
+ endtask   
   
 `include "includes/x393_tasks01.vh"