Debugging vospi mode, fpga: 0x03930133

cocotb/x393_cocotb_lwir_04.sav

 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Thu Apr 25 23:42:15 2019
+[*] Tue Apr 30 17:21:50 2019
 [*]
-[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190425172733675.fst"
-[dumpfile_mtime] "Thu Apr 25 23:38:14 2019"
-[dumpfile_size] 13065486
+[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190430003141791.fst"
+[dumpfile_mtime] "Tue Apr 30 17:20:36 2019"
+[dumpfile_size] 1896466138
 [savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
-[timestart] 34144200
+[timestart] 0
 [size] 1804 1171
 [pos] -1 -1
-*-14.717531 34226035 1019686803 237352388 855469045 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-28.897251 1413970273 1022561895 855534694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_dut.
 [treeopen] x393_dut.simul_lwir160x120_vospi1_i.
 [treeopen] x393_dut.x393_i.
@@ -2771,7 +2771,9 @@ x393_dut.simul_lwir160x120_vospi1_i.start_segm_rd
 x393_dut.simul_lwir160x120_vospi1_i.readout_word_indx[6:0]
 @28
 x393_dut.simul_lwir160x120_vospi1_i.readout_pre_last_bit
+@22
 x393_dut.simul_lwir160x120_vospi1_i.readout_segment[1:0]
+@28
 x393_dut.simul_lwir160x120_vospi1_i.spi_cs
 x393_dut.simul_lwir160x120_vospi1_i.packet_sent
 x393_dut.simul_lwir160x120_vospi1_i.readout_last_packet
@@ -2808,6 +2810,7 @@ x393_dut.simul_lwir160x120_vospi1_i.readout_sr_good[15:0]
 @1401200
 -group_end
 @22
+[color] 2
 x393_dut.simul_lwir160x120_vospi1_i.readout_sr_good_dbg[15:0]
 @28
 x393_dut.simul_lwir160x120_vospi1_i.readout_good
@@ -3071,13 +3074,47 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
 @800200
 -vospi_segment61_0
 @28
+[color] 3
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.start_d
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.we
 @22
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.waddr[10:0]
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dout[15:0]
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_running
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dv
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_segment_r
+@22
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_start_waddr[10:0]
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_start_packet[7:0]
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.full_packet[7:0]
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_running
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_segment_r
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good_w
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.discard_set
 @200
 -
 @28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w
+@22
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.raddr[10:0]
+@29
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]
+@800200
+-packet
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.dv_r
+@22
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.dout[15:0]
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.set_d_r
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_invalid
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.will_sync
+@1000200
+-packet
+@28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.start_out_frame_w
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.sof_w
 @22
@@ -3157,6 +3194,10 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
 -group_end
 @28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_done
+@22
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dout[15:0]
+@28
+x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.packet_dv
 @800200
 -vospi_packet80_0
 @28
@@ -3302,9 +3343,7 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
 @28
 (0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
-@29
 (1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
-@28
 (2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
 (3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
 (4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]

fpga_version.vh

@@ -35,7 +35,12 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h0393012e;      // re-arranged control bits, added telemetry on/off
+        parameter FPGA_VERSION =          32'h03930133;      // Testing sof to hact delay
+//        parameter FPGA_VERSION =          32'h03930132;      // Sync from serial bumber start, added output (with hact)
+//        parameter FPGA_VERSION =          32'h03930131;      // Sync from serial bumber start
+//        parameter FPGA_VERSION =          32'h03930130;      // Adding output for receive start frame
+//        parameter FPGA_VERSION =          32'h0393012f;      // debugging resync on othjer sesnor
+//        parameter FPGA_VERSION =          32'h0393012e;      // re-arranged control bits, added telemetry on/off
 //        parameter FPGA_VERSION =          32'h0393012d;      // debugging - working sync
 //        parameter FPGA_VERSION =          32'h0393012c;      // debugging - working sync
 //      parameter FPGA_VERSION =          32'h0393012b;      // debugging

includes/x393_parameters.vh

@@ -582,10 +582,10 @@
     parameter VOSPI_PACKET_LAST =       60,
     parameter VOSPI_PACKET_TTT =        20,  // line number where segment number is provided
 `ifdef SIMULATION
-    parameter VOSPI_SOF_TO_HACT =        1000,  // clock cycles from SOF to HACT
-    parameter VOSPI_HACT_TO_HACT_EOF =   1000,  // pixel clock is 480 MHz, need to slow down for memory
+    parameter VOSPI_SOF_TO_HACT =     1000,  // clock cycles from SOF to HACT
+    parameter VOSPI_HACT_TO_HACT_EOF =1000,  // pixel clock is 480 MHz, need to slow down for memory
 `else
-    parameter VOSPI_SOF_TO_HACT =        10,  // clock cycles from SOF to HACT
+    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
     parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF
 `endif    
     parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 

py393/x393_sensor.py

@@ -1104,7 +1104,7 @@ class X393Sensor(object):
         @param vsync_use =  Wait for VSYNC (should be enabled over i2c) before reading each segment
         @param noresync =   Disable resynchronization by discard packets
         @param dbg_src =    source of the hardware debug output: 0 - dbg_running
-                                                                 1 - vsync_rdy[0]
+                                                                 1 - will_sync
                                                                  2 - vsync_rdy[1]
                                                                  3 - discard_segment
                                                                  4 - in_busy

sensor/sens_lepton3.v

@@ -140,7 +140,7 @@ module  sens_lepton3 #(
     parameter VOSPI_PACKET_FIRST =     0,
     parameter VOSPI_PACKET_LAST =     60,
     parameter VOSPI_PACKET_TTT =      20,  // line number where segment number is provided
-    parameter VOSPI_SOF_TO_HACT =      2,  // clock cycles from SOF to HACT
+    parameter VOSPI_SOF_TO_HACT =    100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
     parameter VOSPI_HACT_TO_HACT_EOF = 2,  // minimal clock cycles from HACT to HACT or to EOF
     parameter VOSPI_MCLK_HALFDIV =     4   // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
 )(
@@ -202,6 +202,7 @@ module  sens_lepton3 #(
     wire                         dbg_segment_stb;
     wire                         dbg_will_sync;
     wire                  [4:0]  dbg_state;
+    wire                         dbg_frame_start;   // output //from receiving first packet to SOF
     wire                         crc_err_w;  // single-cycle CRC error
     reg                          crc_err_r;  // at least one CRC error happened since reset
     wire                         sync_err_w;  // single-cycle synchronzation error
@@ -280,8 +281,8 @@ module  sens_lepton3 #(
     wire        mipi_dn_int;
     wire        mipi_clkp_int;
     wire        mipi_clkn_int;
-    
-    
+    wire        dbg_tel_sync; // certain 32 bits in the telemetry
+    wire        dbg_tel_sync_out;
 // temporary?
     assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int ^ fake_dp2 ^ fake_dn2 ^ fake_dn6;
 
@@ -308,13 +309,13 @@ module  sens_lepton3 #(
                              (dbg_sel[1]?( dbg_sel[0]? dbg_sources[3]:dbg_sources[2]):( dbg_sel[0]? dbg_sources[1]: dbg_sources[0]));
                              
     assign dbg_sources[0] =   dbg_running;
-    assign dbg_sources[1] =   dbg_will_sync; //
-    assign dbg_sources[2] =   dbg_vsync_rdy[1]; //
+    assign dbg_sources[1] =   dbg_will_sync;    //
+    assign dbg_sources[2] =   dbg_state[3];     // dbg_vsync_rdy[1]; //
     assign dbg_sources[3] =   discard_segment;  // dbg_state[0]; //
-    assign dbg_sources[4] =   in_busy;          // dbg_state[1]; //
-    assign dbg_sources[5] =   out_busy;         // dbg_state[2]; //  
+    assign dbg_sources[4] =   dbg_tel_sync_out; // in_busy;          // dbg_state[2];     // in_busy;          // dbg_state[1]; //
+    assign dbg_sources[5] =   dbg_frame_start;  // out_busy;         // dbg_state[2]; //  
     assign dbg_sources[6] =   hact;             // dbg_state[3]; //  
-    assign dbg_sources[7] =   sof;              // dbg_state[4]; //  
+    assign dbg_sources[7] =   dbg_tel_sync;     // sof;              // dbg_state[4]; //  
 
 //dbg_will_sync dbg_state
                              
@@ -687,7 +688,7 @@ module  sens_lepton3 #(
         .VOSPI_PACKET_FIRST     (VOSPI_PACKET_FIRST),     //  0
         .VOSPI_PACKET_LAST      (VOSPI_PACKET_LAST),      // 60
         .VOSPI_PACKET_TTT       (VOSPI_PACKET_TTT),       // 20
-        .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT),      //  2
+        .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT),      //100
         .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF)  //  2
     ) vospi_segment_61_i (
         .rst             (!spi_nrst_pclk[1]),   // input
@@ -717,8 +718,12 @@ module  sens_lepton3 #(
         .dbg_running     (dbg_running),      // output debug output for oscilloscope
         .dbg_vsync_rdy   (dbg_vsync_rdy),    // output[1:0]'
         .dbg_segment_stb (dbg_segment_stb),  // output 
-        .dbg_will_sync   (dbg_will_sync),     // output
-        .dbg_state       (dbg_state) // output[4:0]         
+        .dbg_will_sync   (dbg_will_sync),    // output
+        .dbg_state       (dbg_state),        // output[4:0]
+        .dbg_frame_start (dbg_frame_start),  // output //from receiving first packet to SOF
+        .dbg_tel_sync    (dbg_tel_sync),      // output[4:0] certain 32 bits in telemetry data
+        .dbg_tel_sync_out(dbg_tel_sync_out)      // output[4:0] certain 32 bits in telemetry data
+                 
         
     );
     cmd_deser #(

sensor/sensor_channel.v

@@ -273,7 +273,7 @@ module  sensor_channel#(
     parameter VOSPI_PACKET_FIRST =       0,
     parameter VOSPI_PACKET_LAST =       60,
     parameter VOSPI_PACKET_TTT =        20,  // line number where segment number is provided
-    parameter VOSPI_SOF_TO_HACT =        2,  // clock cycles from SOF to HACT
+    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
     parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF
     parameter VOSPI_MCLK_HALFDIV =       4  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 
     
@@ -1090,7 +1090,7 @@ module  sensor_channel#(
             .VOSPI_PACKET_FIRST     (VOSPI_PACKET_FIRST), //       0,
             .VOSPI_PACKET_LAST      (VOSPI_PACKET_LAST), //       60,
             .VOSPI_PACKET_TTT       (VOSPI_PACKET_TTT), //        20,
-            .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT), //        2,
+            .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT), //      100,
             .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), //   2,
             .VOSPI_MCLK_HALFDIV     (VOSPI_MCLK_HALFDIV) //        4
     ) sens_lepton3_i (

sensor/sensors393.v

@@ -269,7 +269,7 @@ module  sensors393 #(
     parameter VOSPI_PACKET_FIRST =       0,
     parameter VOSPI_PACKET_LAST =       60,
     parameter VOSPI_PACKET_TTT =        20,  // line number where segment number is provided
-    parameter VOSPI_SOF_TO_HACT =        2,  // clock cycles from SOF to HACT
+    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
     parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF
     parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 
     
@@ -753,9 +753,9 @@ module  sensors393 #(
                 .VOSPI_PACKET_FIRST            (VOSPI_PACKET_FIRST), //       0,
                 .VOSPI_PACKET_LAST             (VOSPI_PACKET_LAST), //       60,
                 .VOSPI_PACKET_TTT              (VOSPI_PACKET_TTT), //        20,
-                .VOSPI_SOF_TO_HACT             (VOSPI_SOF_TO_HACT), //        2,
+                .VOSPI_SOF_TO_HACT             (VOSPI_SOF_TO_HACT), //      100,
                 .VOSPI_HACT_TO_HACT_EOF        (VOSPI_HACT_TO_HACT_EOF), //   2,
-                .VOSPI_MCLK_HALFDIV            (VOSPI_MCLK_HALFDIV) //       4
+                .VOSPI_MCLK_HALFDIV            (VOSPI_MCLK_HALFDIV) //        4
                 
 `else
                 .SENSOR_DATA_WIDTH             (SENSOR_DATA_WIDTH),

sensor/vospi_segment_61.v

@@ -47,7 +47,7 @@ module  vospi_segment_61#(
     parameter VOSPI_PACKET_FIRST =     0,
     parameter VOSPI_PACKET_LAST =     60,  // with telemetry
     parameter VOSPI_PACKET_TTT =      20,  // line number where segment number is provided
-    parameter VOSPI_SOF_TO_HACT =      2,  // clock cycles from SOF to HACT
+    parameter VOSPI_SOF_TO_HACT =    100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
     parameter VOSPI_HACT_TO_HACT_EOF = 2  // minimal clock cycles from HACT to HACT or to EOF
     
 //    parameter VOSPI_HACT_TO_EOF =      2   // clock cycles from HACT to EOF
@@ -83,8 +83,12 @@ module  vospi_segment_61#(
     output  [1:0] dbg_vsync_rdy,
     output        dbg_segment_stb,
     output        dbg_will_sync,
-    output [ 4:0] dbg_state
+    output [ 4:0] dbg_state,
+    output        dbg_frame_start,  // from receiving first packet to SOF
+    output        dbg_tel_sync,    // 2 words from Software revision
+    output        dbg_tel_sync_out    // 2 words from Software revision
 );
+
     localparam VOSPI_PACKET_LAST_NOTEL = VOSPI_PACKET_LAST -1;
 
 
@@ -137,7 +141,9 @@ module  vospi_segment_61#(
     reg    [3:0] segment_id_r;
     wire         frame_in_done;
     
-    reg    [1:0] vsync_rdy;  
+    reg    [1:0] vsync_rdy;
+    reg          dbg_frame_start_r; // set when starting the first packet in a frame, off with SOF 
+      
 //    reg          packet_running; // may be discarded
 
     assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST);
@@ -162,6 +168,9 @@ module  vospi_segment_61#(
     assign dbg_running =        segment_running;
     assign dbg_vsync_rdy[1:0] = vsync_rdy[1:0];
     assign dbg_segment_stb =    segment_stb;
+    assign dbg_frame_start =    dbg_frame_start_r;
+    assign dbg_tel_sync =       d8208;
+    assign dbg_tel_sync_out =   h8208;
     
     // To Buffer
     always @ (posedge clk) begin
@@ -228,6 +237,9 @@ module  vospi_segment_61#(
         if      (!segment_busy_r || start)                           segment_running <= 0;
         else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST))  segment_running <= 1;
         
+        if      (rst || sof_w)                                                            dbg_frame_start_r <= 0;
+        else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST) && is_first_segment_w) dbg_frame_start_r <= 1;
+        
 ///        packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
         packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start && vsync_rdy[1];
         
@@ -262,6 +274,8 @@ module  vospi_segment_61#(
     reg    [2:0] hact_r;
     reg          pend_eof_r;
     reg   [10:0] raddr;
+    reg  d6110, d8208;
+    reg  h6110, h8208; // output with hact
 //    wire         sync_end;
     wire         will_sync;
 //    wire  [ 4:0] dbg_state;
@@ -286,6 +300,23 @@ module  vospi_segment_61#(
     assign dbg_will_sync = will_sync;
     
     always @ (posedge clk) begin
+    
+//        .dout           (packet_dout),     // output[15:0] 
+//        .dv             (packet_dv),       // output
+        if (packet_dv) begin
+            d6110 <= packet_dout == 16'h6110; //
+            d8208 <= (packet_dout == 16'h8208) && d6110; //;
+        end
+
+        if (hact_r[2]) begin
+            h6110 <= dout == 16'h6110; //
+            h8208 <= (dout == 16'h8208) && h6110; //;
+        end
+        
+        //h6110, h8208
+        
+        
+        
         if (rst) hact_r <= 0;
         else     hact_r  <= {hact_r[1:0], hact_start_w | (hact_r[0] & ~hact_end_w)};
     

simulation_modules/simul_lwir160x120_telemetry.v

@@ -68,7 +68,8 @@ module  simul_lwir160x120_telemetry(
             telemetry_rev             [15:0],  // word   0
             telemetry_time            [31:0],  // words  1.. 2
             telemetry_status          [31:0],  // words  3.. 4
-            {8{16'b0}},                        // words  5..12
+//            {8{16'b0}},                        // words  5..12
+            {16'h6110, 16'h8208, 16'h29a6, 16'h96a2, 16'h1045, 16'h076c, 16'h2400, 16'h0000 }, // words  5..12
             telemetry_srev            [63:0],  // words 13..16
             {3{16'b0}},                        // words 17..19
             telemetry_frame           [31:0],  // words 20..21

x393.v

@@ -1879,7 +1879,7 @@ assign axi_grst = axi_rst_pre;
         .VOSPI_PACKET_FIRST         (VOSPI_PACKET_FIRST), //       0,
         .VOSPI_PACKET_LAST          (VOSPI_PACKET_LAST), //       60,
         .VOSPI_PACKET_TTT           (VOSPI_PACKET_TTT), //        20,
-        .VOSPI_SOF_TO_HACT          (VOSPI_SOF_TO_HACT), //        2,
+        .VOSPI_SOF_TO_HACT          (VOSPI_SOF_TO_HACT), //      100,
         .VOSPI_HACT_TO_HACT_EOF     (VOSPI_HACT_TO_HACT_EOF), //   2,
         .VOSPI_MCLK_HALFDIV         (VOSPI_MCLK_HALFDIV), //       4
         

x393_vospi_utilization.report

 Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
-| Date         : Fri Apr 26 13:14:46 2019
+| Date         : Tue Apr 30 13:08:01 2019
 | Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
 | Command      : report_utilization -file vivado_build/x393_vospi_utilization.report
 | Design       : x393
@@ -31,13 +31,13 @@ Table of Contents
 +----------------------------+-------+-------+-----------+-------+
 |          Site Type         |  Used | Fixed | Available | Util% |
 +----------------------------+-------+-------+-----------+-------+
-| Slice LUTs                 | 42027 |     0 |     78600 | 53.47 |
-|   LUT as Logic             | 38670 |     0 |     78600 | 49.20 |
-|   LUT as Memory            |  3357 |     0 |     26600 | 12.62 |
+| Slice LUTs                 | 41899 |     0 |     78600 | 53.31 |
+|   LUT as Logic             | 38547 |     0 |     78600 | 49.04 |
+|   LUT as Memory            |  3352 |     0 |     26600 | 12.60 |
 |     LUT as Distributed RAM |  2802 |     0 |           |       |
-|     LUT as Shift Register  |   555 |     0 |           |       |
-| Slice Registers            | 54031 |     0 |    157200 | 34.37 |
-|   Register as Flip Flop    | 54031 |     0 |    157200 | 34.37 |
+|     LUT as Shift Register  |   550 |     0 |           |       |
+| Slice Registers            | 54053 |     0 |    157200 | 34.38 |
+|   Register as Flip Flop    | 54053 |     0 |    157200 | 34.38 |
 |   Register as Latch        |     0 |     0 |    157200 |  0.00 |
 | F7 Muxes                   |    34 |     0 |     39300 |  0.09 |
 | F8 Muxes                   |     0 |     0 |     19650 |  0.00 |
@@ -58,8 +58,8 @@ Table of Contents
 | 0     |          Yes |           - |            - |
 | 8     |          Yes |           - |          Set |
 | 672   |          Yes |           - |        Reset |
-| 1025  |          Yes |         Set |            - |
-| 52326 |          Yes |       Reset |            - |
+| 1026  |          Yes |         Set |            - |
+| 52347 |          Yes |       Reset |            - |
 +-------+--------------+-------------+--------------+
 
 
@@ -69,27 +69,27 @@ Table of Contents
 +-------------------------------------------+-------+-------+-----------+-------+
 |                 Site Type                 |  Used | Fixed | Available | Util% |
 +-------------------------------------------+-------+-------+-----------+-------+
-| Slice                                     | 16731 |     0 |     19650 | 85.15 |
-|   SLICEL                                  | 11080 |     0 |           |       |
-|   SLICEM                                  |  5651 |     0 |           |       |
-| LUT as Logic                              | 38670 |     0 |     78600 | 49.20 |
-|   using O5 output only                    |     3 |       |           |       |
-|   using O6 output only                    | 30067 |       |           |       |
-|   using O5 and O6                         |  8600 |       |           |       |
-| LUT as Memory                             |  3357 |     0 |     26600 | 12.62 |
+| Slice                                     | 16499 |     0 |     19650 | 83.96 |
+|   SLICEL                                  | 10887 |     0 |           |       |
+|   SLICEM                                  |  5612 |     0 |           |       |
+| LUT as Logic                              | 38547 |     0 |     78600 | 49.04 |
+|   using O5 output only                    |     5 |       |           |       |
+|   using O6 output only                    | 29897 |       |           |       |
+|   using O5 and O6                         |  8645 |       |           |       |
+| LUT as Memory                             |  3352 |     0 |     26600 | 12.60 |
 |   LUT as Distributed RAM                  |  2802 |     0 |           |       |
 |     using O5 output only                  |     2 |       |           |       |
 |     using O6 output only                  |    84 |       |           |       |
 |     using O5 and O6                       |  2716 |       |           |       |
-|   LUT as Shift Register                   |   555 |     0 |           |       |
-|     using O5 output only                  |   292 |       |           |       |
-|     using O6 output only                  |   214 |       |           |       |
-|     using O5 and O6                       |    49 |       |           |       |
-| LUT Flip Flop Pairs                       | 24382 |     0 |     78600 | 31.02 |
-|   fully used LUT-FF pairs                 |  4517 |       |           |       |
-|   LUT-FF pairs with one unused LUT output | 17666 |       |           |       |
-|   LUT-FF pairs with one unused Flip Flop  | 17598 |       |           |       |
-| Unique Control Sets                       |  4737 |       |           |       |
+|   LUT as Shift Register                   |   550 |     0 |           |       |
+|     using O5 output only                  |   275 |       |           |       |
+|     using O6 output only                  |   221 |       |           |       |
+|     using O5 and O6                       |    54 |       |           |       |
+| LUT Flip Flop Pairs                       | 24341 |     0 |     78600 | 30.97 |
+|   fully used LUT-FF pairs                 |  4497 |       |           |       |
+|   LUT-FF pairs with one unused LUT output | 17618 |       |           |       |
+|   LUT-FF pairs with one unused Flip Flop  | 17682 |       |           |       |
+| Unique Control Sets                       |  4761 |       |           |       |
 +-------------------------------------------+-------+-------+-----------+-------+
 * Note: Review the Control Sets Report for more information regarding control sets.
 
@@ -196,17 +196,17 @@ Table of Contents
 +------------------------+-------+----------------------+
 |        Ref Name        |  Used |  Functional Category |
 +------------------------+-------+----------------------+
-| FDRE                   | 52326 |         Flop & Latch |
-| LUT3                   | 11339 |                  LUT |
-| LUT6                   | 10220 |                  LUT |
-| LUT2                   |  8365 |                  LUT |
-| LUT4                   |  7941 |                  LUT |
-| LUT5                   |  7821 |                  LUT |
+| FDRE                   | 52347 |         Flop & Latch |
+| LUT3                   | 11357 |                  LUT |
+| LUT6                   | 10054 |                  LUT |
+| LUT2                   |  8436 |                  LUT |
+| LUT4                   |  7995 |                  LUT |
+| LUT5                   |  7765 |                  LUT |
 | RAMD32                 |  4126 |   Distributed Memory |
 | CARRY4                 |  2733 |           CarryLogic |
-| LUT1                   |  1584 |                  LUT |
+| LUT1                   |  1585 |                  LUT |
 | RAMS32                 |  1392 |   Distributed Memory |
-| FDSE                   |  1025 |         Flop & Latch |
+| FDSE                   |  1026 |         Flop & Latch |
 | FDCE                   |   672 |         Flop & Latch |
 | SRL16E                 |   496 |   Distributed Memory |
 | SRLC32E                |   108 |   Distributed Memory |