debugging qith hardware (9b16ac66) · Commits · Elphel / x393

py393/x393_axi_control_status.py

+6 −7

Original line number	Original line	Diff line number	Diff line
	@@ -32,7 +32,6 @@ __status__ = "Development"
	#import x393_mem		#import x393_mem
	#from import_verilog_parameters import VerilogParameters		#from import_verilog_parameters import VerilogParameters
	from x393_mem import X393Mem		from x393_mem import X393Mem
	#from verilog_utils import hx,concat, bits
	from verilog_utils import hx		from verilog_utils import hx
	from time import time		from time import time
	import vrlg		import vrlg
	@@ -356,7 +355,7 @@ class X393AxiControlStatus(object):
	"""		"""
	global mcntrl_en		global mcntrl_en
	en=(0,1)[en]		en=(0,1)[en]
	if self.verbose>0:		if self.verbose > -10: # 0:
	print ("ENABLE MEMCTRL %s"%str(en))		print ("ENABLE MEMCTRL %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);		self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
	mcntrl_en=en		mcntrl_en=en
	@@ -369,8 +368,8 @@ class X393AxiControlStatus(object):
	global enabled_channels		global enabled_channels
	enabled_channels = chnen # currently enabled memory channels		enabled_channels = chnen # currently enabled memory channels
	self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});		self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
	if self.verbose>0:		if self.verbose > -10: # 0:
	print ("ENABLED MEMCTRL CHANNELS 0x%x (word)"%enabled_channels)		print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))

	def enable_memcntrl_en_dis(self,		def enable_memcntrl_en_dis(self,
	chn, # input [3:0] chn;		chn, # input [3:0] chn;
	@@ -385,8 +384,8 @@ class X393AxiControlStatus(object):
	enabled_channels \|= 1<<chn;		enabled_channels \|= 1<<chn;
	else:		else:
	enabled_channels &= ~(1<<chn);		enabled_channels &= ~(1<<chn);
	self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});		self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
	if self.verbose>0:		if self.verbose > -10: #0:
	print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)		print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)

	def configure_channel_priority(self,		def configure_channel_priority(self,
	@@ -399,7 +398,7 @@ class X393AxiControlStatus(object):
	"""		"""
	global channel_priority		global channel_priority
	self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});		self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
	if self.verbose>0:		if self.verbose > -1: # 0:
	print ("SET CHANNEL %d priority=0x%x"%(chn,priority))		print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
	channel_priority[chn]=priority		channel_priority[chn]=priority

py393/x393_mcntrl_adjust.py

+10 −3

Original line number	Original line	Diff line number	Diff line
	@@ -4996,7 +4996,7 @@ write_settings= {


	def measure_all(self,		def measure_all(self,
	tasks="*ICWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",		tasks="*DCWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",
	prim_steps=1,		prim_steps=1,
	primary_set_in=2,		primary_set_in=2,
	primary_set_out=2,		primary_set_out=2,
	@@ -5007,7 +5007,8 @@ write_settings= {
	quiet=3):		quiet=3):
	"""		"""
	@param tasks - "*" - load bitfile		@param tasks - "*" - load bitfile
	"I" - initialize memory, set defaults		"D" - set defaults
			"I" - initialize memory, set refresh
	"C" cmda, "W' - write levelling, "R" - read levelling (DQI-DQSI), "P" - dqs input phase (DQSI-PHASE),		"C" cmda, "W' - write levelling, "R" - read levelling (DQI-DQSI), "P" - dqs input phase (DQSI-PHASE),
	"O" - output timing (DQ odelay vs DQS odelay), "A" - address/bank lines output delays, "Z" - print results,		"O" - output timing (DQ odelay vs DQS odelay), "A" - address/bank lines output delays, "Z" - print results,
	"B" - select R/W brances and get the optimal phase		"B" - select R/W brances and get the optimal phase
	@@ -5056,11 +5057,17 @@ write_settings= {
	'comment':'Load bitfile, initialize FPGA',		'comment':'Load bitfile, initialize FPGA',
	'params':{'bitfile':bitfile_path,		'params':{'bitfile':bitfile_path,
	'quiet':quiet+1}},		'quiet':quiet+1}},
	{'key':'I',		{'key':'D',
	'func':self.x393_pio_sequences.task_set_up,		'func':self.x393_pio_sequences.task_set_up,
	'comment':'Initial setup - memory controller, sequences',		'comment':'Initial setup - memory controller, sequences',
	'params':{'dqs_pattern':dqs_pattern,		'params':{'dqs_pattern':dqs_pattern,
	'quiet':quiet+1}},		'quiet':quiet+1}},
			{'key':'I', # Used when no calibration is needed - "*DI"
			'func':self.x393_pio_sequences.init_ddr3,
			'comment':'Initialize memory, turn on refresh (used when no calibration is needed)',
			'params':{'refresh':True,
			'wait_complete':True,
			'quiet':quiet+1}},
	{'key':'C',		{'key':'C',
	'func':self.adjust_cmda_odelay,		'func':self.adjust_cmda_odelay,
	'comment':'Measuring CMDA output delay for each clock phase',		'comment':'Measuring CMDA output delay for each clock phase',

py393/x393_mcntrl_buffers.py

+0 −4

Original line number	Original line	Diff line number	Diff line
	@@ -35,10 +35,6 @@ __status__ = "Development"
	from x393_mem import X393Mem		from x393_mem import X393Mem
	#from x393_axi_control_status import X393AxiControlStatus		#from x393_axi_control_status import X393AxiControlStatus
	import x393_axi_control_status		import x393_axi_control_status
	#from verilog_utils import * # concat, bits
	#from verilog_utils import hx, concat, bits, getParWidth
	#from verilog_utils import concat, getParWidth
	#from x393_axi_control_status import concat, bits
	from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32		from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32

	import vrlg		import vrlg

py393/x393_mcntrl_membridge.py

+69 −29

Original line number	Original line	Diff line number	Diff line
	@@ -43,8 +43,13 @@ BUFFER_ASSRESS_NAME='buffer_address'
	BUFFER_PAGES_NAME='buffer_pages'		BUFFER_PAGES_NAME='buffer_pages'
	BUFFER_ADDRESS=None		BUFFER_ADDRESS=None
	BUFFER_LEN=None		BUFFER_LEN=None

			#BUFFER_ADDRESS=0x27900000
			#BUFFER_LEN= 0x6400000

	PAGE_SIZE=4096		PAGE_SIZE=4096
	AFI_BASE_ADDR= 0xf8008000		AFI_BASE_ADDR= 0xf8008000

	'''		'''
	root@elphel393:/sys/devices/elphel393-mem.2# cat buffer_address		root@elphel393:/sys/devices/elphel393-mem.2# cat buffer_address
	0x27900000		0x27900000
	@@ -70,10 +75,10 @@ def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number
	<chn_reset>): immediately reset all the internal circuitry		<chn_reset>): immediately reset all the internal circuitry

	"""		"""
	return verilog_utils.concat ((extra_pages, 2), # extra_pages,		return verilog_utils.concat (((extra_pages, 2), # extra_pages,
	((0,1)[write_mem],1), # write_mem,		((0,1)[write_mem],1), # write_mem,
	((0,1)[enable], 1), #enable,		((0,1)[enable], 1), #enable,
	((1,0)[chn_reset],1)) # ~chn_reset};		((1,0)[chn_reset],1)))[0] # ~chn_reset};

	class X393McntrlMembridge(object):		class X393McntrlMembridge(object):
	DRY_MODE= True # True		DRY_MODE= True # True
	@@ -87,6 +92,7 @@ class X393McntrlMembridge(object):
	verbose=1		verbose=1
	adjustment_state={}		adjustment_state={}
	def __init__(self, debug_mode=1,dry_mode=True): #, saveFileName=None):		def __init__(self, debug_mode=1,dry_mode=True): #, saveFileName=None):
			global BUFFER_ADDRESS, BUFFER_LEN
	self.DEBUG_MODE= debug_mode		self.DEBUG_MODE= debug_mode
	self.DRY_MODE= dry_mode		self.DRY_MODE= dry_mode
	self.x393_mem= x393_mem.X393Mem(debug_mode,dry_mode)		self.x393_mem= x393_mem.X393Mem(debug_mode,dry_mode)
	@@ -94,6 +100,7 @@ class X393McntrlMembridge(object):
	self.x393_pio_sequences= x393_pio_sequences.X393PIOSequences(debug_mode,dry_mode)		self.x393_pio_sequences= x393_pio_sequences.X393PIOSequences(debug_mode,dry_mode)
	self.x393_mcntrl_timing= x393_mcntrl_timing.X393McntrlTiming(debug_mode,dry_mode)		self.x393_mcntrl_timing= x393_mcntrl_timing.X393McntrlTiming(debug_mode,dry_mode)
	self.x393_mcntrl_buffers= x393_mcntrl_buffers.X393McntrlBuffers(debug_mode,dry_mode)		self.x393_mcntrl_buffers= x393_mcntrl_buffers.X393McntrlBuffers(debug_mode,dry_mode)

	# self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path		# self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
	try:		try:
	self.verbose=vrlg.VERBOSE		self.verbose=vrlg.VERBOSE
	@@ -116,6 +123,7 @@ class X393McntrlMembridge(object):
	return		return
	print('BUFFER_ADDRESS=0x%x'%(BUFFER_ADDRESS))		print('BUFFER_ADDRESS=0x%x'%(BUFFER_ADDRESS))
	print('BUFFER_LEN=0x%x'%(BUFFER_LEN))		print('BUFFER_LEN=0x%x'%(BUFFER_LEN))

	def afi_write_reg(self,		def afi_write_reg(self,
	port_num, # input [1:0] port_num;		port_num, # input [1:0] port_num;
	rel_baddr, # input integer rel_baddr; # relative byte address		rel_baddr, # input integer rel_baddr; # relative byte address
	@@ -133,7 +141,7 @@ class X393McntrlMembridge(object):
	quiet)		quiet)
	def afi_read_reg(self,		def afi_read_reg(self,
	port_num, # input [1:0] port_num;		port_num, # input [1:0] port_num;
	rel_baddr, # input integer rel_baddr; # relative byte address		rel_baddr=None, # input integer rel_baddr; # relative byte address
	quiet=1): #input verbose;		quiet=1): #input verbose;
	'''		'''
	Read data from the AXI_HP (AFI) register		Read data from the AXI_HP (AFI) register
	@@ -142,6 +150,13 @@ class X393McntrlMembridge(object):
	@param quiet - reduce output (>=1 - silent)		@param quiet - reduce output (>=1 - silent)
	@return register data		@return register data
	'''		'''

			if rel_baddr is None:
			rslt=[]
			for baddr in (0,4,8,0xc,0x10,0x14,0x18,0x1c,0x20,0x24):
			rslt.append(self.afi_read_reg(port_num,baddr,quiet-1))
			return rslt

	return self.x393_mem.read_mem(AFI_BASE_ADDR+ (port_num << 12) + (rel_baddr & 0xfffffffc),		return self.x393_mem.read_mem(AFI_BASE_ADDR+ (port_num << 12) + (rel_baddr & 0xfffffffc),
	quiet)		quiet)

	@@ -168,8 +183,8 @@ class X393McntrlMembridge(object):
	len64, # input [28:0] len64; # number of 64-bit words to transfer		len64, # input [28:0] len64; # number of 64-bit words to transfer
	width64, # input [28:0] width64; # frame width in 64-bit words		width64, # input [28:0] width64; # frame width in 64-bit words
	start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)		start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)
	lo_addr64=BUFFER_ADDRESS // 8, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words		lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
	size64=BUFFER_LEN // 8, # input [28:0] size64; # size of the system memory range in 64-bit words		size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
	quiet=1):		quiet=1):
	'''		'''
	Set up membridge parameters for data transfer		Set up membridge parameters for data transfer
	@@ -180,6 +195,11 @@ class X393McntrlMembridge(object):
	@param size64 size of the system memory range in 64-bit words		@param size64 size of the system memory range in 64-bit words
	@quiet - reduce output (>=1 - silent)		@quiet - reduce output (>=1 - silent)
	'''		'''
			if lo_addr64 is None:
			lo_addr64 = BUFFER_ADDRESS//8 # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
			if size64 is None:
			size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words

	if quiet <2:		if quiet <2:
	print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))		print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))
	self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);		self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
	@@ -213,16 +233,17 @@ class X393McntrlMembridge(object):
	def membridge_rw (self,		def membridge_rw (self,
	write_ddr3, # input write_ddr3;		write_ddr3, # input write_ddr3;
	# extra_pages, # input [1:0] extra_pages;		# extra_pages, # input [1:0] extra_pages;
	frame_start_addr, # input [21:0] frame_start_addr;		frame_start_addr = None, # input [21:0] frame_start_addr;
	window_full_width, # input [15:0] window_full_width; # 13 bit - in 8*16=128 bit bursts		window_full_width = None, # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
	window_width, # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts		window_width = None, # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts
	window_height, # input [15:0] window_height; # 16 bit (only 14 are used here)		window_height = None, # input [15:0] window_height; # 16 bit (only 14 are used here)
	window_left, # input [15:0] window_left;		window_left = None, # input [15:0] window_left;
	window_top, # input [15:0] window_top;		window_top = None, # input [15:0] window_top;
	start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)		start64 = 0, # input [28:0] start64; # relative start address of the transfer (set to 0 when writing lo_addr64)
	lo_addr64=BUFFER_ADDRESS//8, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words		lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
	size64=BUFFER_LEN//8, # input [28:0] size64; # size of the system memory range in 64-bit words		size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
	cont, # input continue; # 0 start from start64, 1 - continue from where it was		cont = False, # input continue; # 0 start from start64, 1 - continue from where it was
			wait_ready = False,
	quiet=1):		quiet=1):
	'''		'''
	Set up and run data transfer between the system and videobuffer memory		Set up and run data transfer between the system and videobuffer memory
	@@ -237,8 +258,26 @@ class X393McntrlMembridge(object):
	@param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits		@param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits
	@param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.		@param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
	@param cont True: continue from the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64		@param cont True: continue from the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
			@param wait_ready poll status to see if the command finished
	@param quiet Reduce output		@param quiet Reduce output
	'''		'''
			if frame_start_addr is None:
			frame_start_addr = vrlg.FRAME_START_ADDRESS # input [21:0] frame_start_addr;
			if window_full_width is None:
			window_full_width = vrlg.FRAME_FULL_WIDTH # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
			if window_width is None:
			window_width = vrlg.WINDOW_WIDTH # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts
			if window_height is None:
			window_height = vrlg.WINDOW_HEIGHT # input [15:0] window_height; # 16 bit (only 14 are used here)
			if window_left is None:
			window_left = vrlg.WINDOW_X0 # input [15:0] window_left;
			if window_top is None:
			window_top = vrlg.WINDOW_Y0 # input [15:0] window_top;
			if lo_addr64 is None:
			lo_addr64 = BUFFER_ADDRESS//8 # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
			if size64 is None:
			size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words

	window_height &= 0x3fff		window_height &= 0x3fff
	if window_height == 0:		if window_height == 0:
	window_height = 0x4000		window_height = 0x4000
	@@ -266,8 +305,8 @@ class X393McntrlMembridge(object):
	self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) \| window_left) # WINDOW_X0+ (WINDOW_Y0<<16));		self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) \| window_left) # WINDOW_X0+ (WINDOW_Y0<<16));
	self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)		self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
	self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)		self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
	self.x393_axi_control_status.configure_channel_priority(1,0); # lowest priority channel 1		self.x393_axi_tasks.configure_channel_priority(1,0); # lowest priority channel 1
	self.x393_axi_control_status.enable_memcntrl_en_dis(1,1);		self.x393_axi_tasks.enable_memcntrl_en_dis(1,1);
	# write_contol_register(test_mode_address, TEST01_START_FRAME);		# write_contol_register(test_mode_address, TEST01_START_FRAME);
	self.afi_setup(0)		self.afi_setup(0)
	self.membridge_setup(		self.membridge_setup(
	@@ -278,6 +317,7 @@ class X393McntrlMembridge(object):
	size64)		size64)
	self.membridge_start (cont)		self.membridge_start (cont)
	# just wait done (default timeout = 10 sec)		# just wait done (default timeout = 10 sec)
			if wait_ready:
	self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status		self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
	vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,		vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
	vrlg.MCNTRL_SCANLINE_CHN1_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,		vrlg.MCNTRL_SCANLINE_CHN1_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,

py393/x393_mcntrl_tests.py

+24 −92

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