synchromized molre frame parameter transitions

9a7406b4 · Andrey Filippov · 4bb4f227 · 9a7406b4 · 9a7406b4 · 9a7406b4
Commit 9a7406b4 authored Sep 07, 2016 by Andrey Filippov
19 changed files
--- a/cocotb/x393_cocotb_02.sav
+++ b/cocotb/x393_cocotb_02.sav
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Tue Sep  6 05:52:12 2016
+[*] Wed Sep  7 07:20:21 2016
 [*]
-[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160905230400021.fst"
-[dumpfile_mtime] "Tue Sep  6 05:45:49 2016"
-[dumpfile_size] 211215977
+[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160906212704383.fst"
+[dumpfile_mtime] "Wed Sep  7 07:20:01 2016"
+[dumpfile_size] 411501315
 [savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
 [timestart] 0
 [size] 1836 1171
-[pos] 1920 23
-*-25.560389 111820833 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] 1928 23
+*-26.595917 254087388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_dut.
 [treeopen] x393_dut.ddr3_i.ddr3_i.
 [treeopen] x393_dut.simul_axi_master_wdata_i.
@@ -24,6 +24,7 @@
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.
+[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_pixel_buf_iface_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
 [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.
@@ -46,6 +47,7 @@
 [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
 [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
 [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_linear_wr_sensor_i.
+[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.
 [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].
 [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
 [treeopen] x393_dut.x393_i.sensors393_i.
@@ -57,8 +59,8 @@
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
 [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
 [treeopen] x393_dut.x393_i.timing393_i.
-[sst_width] 272
-[signals_width] 287
+[sst_width] 278
+[signals_width] 428
 [sst_expanded] 1
 [sst_vpaned_height] 641
 @820
@@ -538,11 +540,19 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]
 @800200
 -compressor_0
 -linear
-@28
-x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.set_mode_w
 @22
-x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.mode_reg[12:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.mode_reg[14:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_height[16:0]
 @28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_too_late
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.abort_en
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.aborting_r
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pre_want
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.want_r
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_grant
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_done
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.set_mode_w
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_late
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending
 @c00022
@@ -578,8 +588,31 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout_r[15:
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout_valid
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_want
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_grant
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_wr
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_done
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_done_d
+@c00028
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
+@28
+(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
+(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_finished
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_done
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_done_d
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
 @22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_number[15:0]
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_range_addr[21:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run
+@22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_number_cntr[15:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_r[4:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
 @200
 -other channels below
 @22
@@ -605,6 +638,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_rd
 @22
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
 @200
+-
+@1000200
+-membuf
+-linear
+@c00200
+-other_channels
+@200
 -channels 3-2-1 below
 @28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_membuf_i.buf_rd
@@ -618,21 +658,94 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_membuf_i.buf_dout[63
 x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_rd
 @22
 x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_dout[63:0]
-@200
-channel1 below
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_we
+@c00022
+x393_dut.x393_i.mcntrl393_i.cmprs_frame_start_dst[3:0]
+@28
+(0)x393_dut.x393_i.mcntrl393_i.cmprs_frame_start_dst[3:0]
+(1)x393_dut.x393_i.mcntrl393_i.cmprs_frame_start_dst[3:0]
+(2)x393_dut.x393_i.mcntrl393_i.cmprs_frame_start_dst[3:0]
+(3)x393_dut.x393_i.mcntrl393_i.cmprs_frame_start_dst[3:0]
+@1401200
+-group_end
+@c00022
+x393_dut.x393_i.compressor393_i.frame_start_dst[3:0]
+@28
+(0)x393_dut.x393_i.compressor393_i.frame_start_dst[3:0]
+(1)x393_dut.x393_i.compressor393_i.frame_start_dst[3:0]
+(2)x393_dut.x393_i.compressor393_i.frame_start_dst[3:0]
+(3)x393_dut.x393_i.compressor393_i.frame_start_dst[3:0]
+@1401200
+-group_end
+@200
+-channel1 below
 @22
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_din[63:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.frame_start_dst
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst
+@c00022
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@28
+(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.cmprs_run
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.vsync_late
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.reading_frame_r
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_pend_r
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_done
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_number_src[15:0]
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_number[15:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.suspend_end
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frames_numbers_differ
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frames_in_sync
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_conf
+@c00022
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@28
+(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@1401200
+-group_end
+@800200
+-tile_chn1
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.frame_start
 @200
 -
 @1000200
-membuf
-linear
-@200
-
+-tile_chn1
+@1401200
+-other_channels
 @800200
 -tile
+@22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.abort_en
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.aborting_r
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_conf
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_mod
+@8022
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
 @28
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.set_mode_w
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en
@@ -643,14 +756,50 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.fram
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
 @28
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_finished
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.last_row_w
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.last_in_row_w
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.last_block
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done
 @22
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_start_addr[21:0]
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.next_frame_start_addr[21:0]
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_range_addr[21:0]
+@28
+(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+@22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.next_frame_start_addr[21:0]
+@28
+(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+@22
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_addr[21:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_addr_r[21:0]
 @28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.rst_frame_num_w
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.buf_reset_pend
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.is_last_frame
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_mod
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_rst_rd
+@29
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_rst_pos
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.calc_valid
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want
+(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_not_partial
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.next_page
+@22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.need_r
+@22
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.cmd_extra_pages[1:0]
+@8022
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.disable_need
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_grant
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_start32_rd
@@ -660,6 +809,8 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.rowcol_inc[13:0]
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_cols_m1[5:0]
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.num_rows_m1[5:0]
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.suspend
 @1000200
 -tile
 @c00200
@@ -685,9 +836,54 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_en_mcl
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk
 @200
 -
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.reading_frame
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_done
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst
+@c08022
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@28
+(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst_r[5:0]
+@1401200
+-group_end
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_pre_start
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.last_mb
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_pre2_first_out
+@800200
+-cmprs_pixel_buffer_ifacde
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.mb_release_buf
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.period_cntr[8:0]
+@200
+-
+@1000200
+-cmprs_pixel_buffer_ifacde
 @800200
 -cmprs_macroblock
 @28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.buf_ready_w
+@8022
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.buf_diff[2:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.reset_page_rd
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.needed_page[2:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.page_ready
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.next_valid[2:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.next_page_chn
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.xfer_reset_page_rd
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.cmprs_run_xclk
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_en_r
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.first_mb
@@ -697,12 +893,12 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macrob
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_que_cntr[2:0]
-@800028
+@c08028
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_finish_r[1:0]
 @28
 (0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_finish_r[1:0]
 (1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_finish_r[1:0]
-@1001200
+@1401200
 -group_end
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_finish_w
@@ -720,7 +916,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macrob
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_rows_left[12:0]
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_last_row
-@800022
+@c00022
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
 @28
 (0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
@@ -732,17 +928,38 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macrob
 (6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
 (7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
 (8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
-@1001200
+@1401200
 -group_end
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.first_mb
 @22
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
+@28
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.page_ready_chn
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.page_ready
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.next_page_chn
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.multipulse_cross_clock_i.we
+@22
+x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.multipulse_cross_clock_i.num_pulses[2:0]
 @200
 -
 @1000200
 -cmprs_macroblock
-@c00023
+@28
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_mod
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en
+@c08022
+x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+@28
+(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
+@1401200
+-group_end
+@c00022
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mbl_x_last_r[7:3]
 @28
 (0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mbl_x_last_r[7:3]
@@ -750,7 +967,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macrob
 (2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mbl_x_last_r[7:3]
 (3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mbl_x_last_r[7:3]
 (4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mbl_x_last_r[7:3]
-@1401201
+@1401200
 -group_end
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.reset_page_rd
@@ -962,7 +1179,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_n
 -
 @1401200
 -scanline_linear
-@800200
+@c00200
 -mcntrl_tiled
 @28
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
@@ -997,24 +1214,6 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.fram
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_finished
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_rst_r
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst
-@c00022
-x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-@28
-(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(5)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(6)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(7)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(8)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(9)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(10)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-(11)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[11:0]
-@1401200
-group_end
-@28
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.master_set
@@ -1026,8 +1225,9 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.susp
 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
 @200
 -
-@1000200
+@1401200
 -mcntrl_tiled
+@1000200
 -follow_master
 @c00200
 -compressors_all
@@ -1993,9 +2193,9 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk
 @1401200
 -compressor_channel0
-@c00200
+@800200
 -interrupts
-@800022
+@c00022
 x393_dut.irq_r[8:0]
 @28
 (0)x393_dut.irq_r[8:0]
@@ -2007,7 +2207,7 @@ x393_dut.irq_r[8:0]
 (6)x393_dut.irq_r[8:0]
 (7)x393_dut.irq_r[8:0]
 (8)x393_dut.irq_r[8:0]
-@1001200
+@1401200
 -group_end
 @28
 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.is_r
@@ -2031,7 +2231,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status
 -group_end
 @200
 -
-@1401200
+@1000200
 -interrupts
 @c00200
 -afi0_mux

--- a/compressor_jp/cmprs_frame_sync.v
+++ b/compressor_jp/cmprs_frame_sync.v
@@ -68,6 +68,9 @@ module  cmprs_frame_sync#(
    output                        frame_start_dst,    // @mclk - trigger receive (tiled) memory channel (it will take care of single/repetitive
                                                      // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                      // (compress from memory)
+    input                         frame_start_conf,   // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
+                                                      // or more if there were outstanding memory transactions.                                                           
+                                                      
    input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
    input   [LAST_FRAME_BITS-1:0] frame_number_src,   // current frame number (for multi-frame ranges) in the source (sensor) channel
    input                         frame_done_src,     // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
@@ -77,7 +80,8 @@ module  cmprs_frame_sync#(
    input [FRAME_HEIGHT_BITS-1:0] line_unfinished,    // number of the current (unfinished ) line in this (compressor) channel
    input   [LAST_FRAME_BITS-1:0] frame_number,       // current frame number (for multi-frame ranges) in this (compressor channel
    input                         frames_in_sync,     // frame number in destination memory channel is valid for bonded mode
-    input                         frame_done,         // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
+    input                         frame_done,         // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory\
+    input                         last_mb_started,    // @ xclk - last mb started running, safe to assume memory channel is done 
    output reg                    suspend,            // suspend reading data for this channel - waiting for the source data

    input                         stuffer_running,    // @xclk2x stuffer is running/flushing
@@ -115,6 +119,7 @@ module  cmprs_frame_sync#(
    reg        cmprs_en_d;
    reg        suspend_end; // suspend at the end of the current frame until frame number changes
 //    reg    cmprs_en_xclk;
+    wire      last_mb_started_mclk;
    assign frame_start_dst = frame_start_dst_r[0];
    assign cmprs_en_extend = cmprs_en_extend_r;
    
@@ -128,6 +133,7 @@ module  cmprs_frame_sync#(
        if       (mrst)                                       cmprs_en_extend_r <= 0;
        else if  (cmprs_en)                                   cmprs_en_extend_r <= 1;
        else if  ((timeout == 0) || !stuffer_running_mclk_r)  cmprs_en_extend_r <= 0;
+        
    end
    
    always @ (posedge mclk) begin
@@ -139,21 +145,21 @@ module  cmprs_frame_sync#(
        
        cmprs_en_d <= cmprs_en;

-///     broken_frame <=  cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
+//     broken_frame <=  cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
        aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
        
        if      (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
-///     else if (broken_frame || aborted_frame)                force_flush_long <= 1;
+//     else if (broken_frame || aborted_frame)                force_flush_long <= 1;
        else if (aborted_frame)                                force_flush_long <= 1;

-    
-///     if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
-        if (!cmprs_en || frame_done )                             reading_frame_r <= 0;
+//     if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
+//     last_mb_start[2] is used as emergency turn off reading_frame if memory channel did not generate frame_done (i.e. wrong frame height)
+// TODO: Consider the opposite - frame_done, but not got the last MB?
+        if (!cmprs_en || frame_done || last_mb_started_mclk)      reading_frame_r <= 0;
        else if (frame_started_mclk)                              reading_frame_r <= 1;

-//        if      (!cmprs_en || frame_start_dst_r[0])                              frame_start_pend_r <= 0;
-        if      (!cmprs_run || frame_start_dst_r[0])                             frame_start_pend_r <= 0;
-//        else if (cmprs_run && vsync_late && reading_frame_r)  frame_start_pend_r <= 1;
+//        if      (!cmprs_run || frame_start_dst_r[0])                             frame_start_pend_r <= 0;
+        if      (!cmprs_run || frame_start_conf)                                  frame_start_pend_r <= 0;
        else if ((cmprs_run && vsync_late && reading_frame_r) ||
                 (frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
  //      else if (frame_start_dst_r[0])                        frame_start_pend_r <= 0;
@@ -168,8 +174,10 @@ module  cmprs_frame_sync#(
        frame_start_dst_r[0] <= cmprs_en && (cmprs_run ? 
                                            ((vsync_late && !reading_frame_r) || (frame_start_pend_r  && frame_done)):
                                             cmprs_standalone);
+        // modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed                                             
        if      (!cmprs_en)   frame_start_dst_r[5:1] <=0;
-        else                  frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];                                             
+//        else                  frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];                                             
+        else                  frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf};                                             
        
        if      (!cmprs_en)        bonded_mode <= 0;
        else if (cmprs_run)        bonded_mode <= 1;
@@ -188,6 +196,8 @@ module  cmprs_frame_sync#(
    
 //    pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
    pulse_cross_clock frame_started_i   (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
+    pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy());
+

 endmodule

--- a/compressor_jp/compressor393.v
+++ b/compressor_jp/compressor393.v
@@ -169,6 +169,8 @@ module  compressor393 # (
    output                    [3:0] frame_start_dst,    // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
                                                        // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                        // (compress from memory)
+    input                     [3:0] frame_start_conf,   // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
+                                                        // or more if there were outstanding memory transactions.                                                           
    input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
    input   [4*LAST_FRAME_BITS-1:0] frame_number_src,   // current frame number (for multi-frame ranges) in the source (sensor) channel
    input                     [3:0] frame_done_src,     // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
@@ -438,6 +440,7 @@ module  compressor393 # (
                .next_page_chn                        (next_page[i]),              // output
                
                .frame_start_dst                      (frame_start_dst[i]),        // output
+                .frame_start_conf                     (frame_start_conf[i]),          // input
                .line_unfinished_src                  (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0] 
                .frame_number_src                     (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0] 
                .frame_done_src                       (frame_done_src[i]),         // input

--- a/compressor_jp/jp_channel.v
+++ b/compressor_jp/jp_channel.v
@@ -155,6 +155,9 @@ module  jp_channel#(
    output                        frame_start_dst,    // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
                                                      // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                      // (compress from memory)
+    input                         frame_start_conf,   // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
+                                                        // or more if there were outstanding memory transactions.                                                           
+                                                      
    input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
    input   [LAST_FRAME_BITS-1:0] frame_number_src,   // current frame number (for multi-frame ranges) in the source (sensor) channel
    input                         frame_done_src,     // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
@@ -582,7 +585,8 @@ module  jp_channel#(
        .rst       (!cmprs_en_mclk),
        .src_clk   (mclk),
        .dst_clk   (hclk),
-        .in_pulse  (frame_start_dst),
+//        .in_pulse  (frame_start_dst),
+        .in_pulse  (frame_start_conf),
        .out_pulse (dbg_frame_start_hclk),
        .busy      ());
    
@@ -725,7 +729,8 @@ module  jp_channel#(
        .color_sat_we       (set_color_saturation_w), // input - write color saturation values
        .coring_we          (set_coring_w),        // input - write color saturation values
        .di                 (cmd_data),            // input[31:0] - 32-bit data to write to control register (24LSB are used)
-        .frame_start        (frame_start_dst),     // input @mclk
+//        .frame_start        (frame_start_dst),     // input @mclk
+        .frame_start        (frame_start_conf),     // input @mclk
        .frame_start_xclk   (frame_start_xclk),    // output re-clocked, parameters are copied during this pulse
        .cmprs_en_mclk      (cmprs_en_mclk),       // output
        .cmprs_en_extend    (cmprs_en_extend),     // input
@@ -796,6 +801,8 @@ module  jp_channel#(
        .frame_start_dst    (frame_start_dst),     // output reg @mclk - trigger receive (tiled) memory channel (it will take care of
                                                   // single/repetitive modes itself this output either follows vsync_late (reclocks it)
                                                   // or generated in non-bonded mode (compress from memory once)
+        .frame_start_conf   (frame_start_conf),    // input: memory controller confirmed cmprs_frame_start_dst - normally delayed by 1 clock,
+                                                   // or more if there were outstanding memory transactions.                                                           
        .line_unfinished_src(line_unfinished_src), // input[15:0] - number of the current (unfinished ) line, in the source (sensor) channel
        .frame_number_src   (frame_number_src),    // input[15:0] - current frame number (for multi-frame ranges) in the source (sensor) channel
        .frame_done_src     (frame_done_src),      // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
@@ -805,6 +812,7 @@ module  jp_channel#(
        .frame_number       (frame_number_dst),    // input[15:0] - current frame number (for multi-frame ranges) in this (compressor channel
        .frames_in_sync     (frames_in_sync),      // frame number in destination memory channel is valid for bonded mode
        .frame_done         (frame_done_dst),      // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
+        .last_mb_started    (last_mb && mb_pre2_first_out), // input 
        .suspend            (suspend),             // output reg - suspend reading data for this channel - waiting for the source data
        .stuffer_running    (stuffer_running), // input
        .force_flush_long   (force_flush_long),         // output reg - @ mclk tried to start frame compression before the previous one was finished

--- a/fpga_version.vh
+++ b/fpga_version.vh
@@ -35,7 +35,7 @@
 * contains all the components and scripts required to completely simulate it
 * with at least one of the Free Software programs.
 */
-          parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits
+          parameter FPGA_VERSION =          32'h039300ae;      // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%
 //        parameter FPGA_VERSION =          32'h039300ad;      // parallel, resetting frame_pre_run. All met, 79.97%
 //        parameter FPGA_VERSION =          32'h039300ac;      // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%
 //        parameter FPGA_VERSION =          32'h039300ab;      // parallel, more on frame sync in compressor All met, 79.04%

--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -298,6 +298,7 @@
    parameter MCONTR_LINTILE_DIS_NEED =           11,   // disable 'need' request
    parameter MCONTR_LINTILE_SKIP_LATE =          12,  // skip actual R/W operation when it is too late, advance pointers
    parameter MCONTR_LINTILE_COPY_FRAME =         13,  // copy frame number from the master channel (single event, not a persistent mode)
+    parameter MCONTR_LINTILE_ABORT_LATE =         14,  // abort frame if not finished by the new frame sync (wait pending memory)
    
    parameter MCNTRL_SCANLINE_DLY_WIDTH =         12,  // delay start pulse by 1..64 mclk
    parameter MCNTRL_SCANLINE_DLY_DEFAULT =       63,  // initial delay value for start pulse

--- a/memctrl/mcntrl393.v
+++ b/memctrl/mcntrl393.v
@@ -262,6 +262,7 @@ module  mcntrl393 #(
    parameter MCONTR_LINTILE_DIS_NEED =     11,   // disable 'need' request 
    parameter MCONTR_LINTILE_SKIP_LATE =    12,  // skip actual R/W operation when it is too late, advance pointers
    parameter MCONTR_LINTILE_COPY_FRAME =   13,  // copy frame number from the master channel (single event, not a persistent mode)
+    parameter MCONTR_LINTILE_ABORT_LATE =   14,  // abort frame if not finished by the new frame sync (wait pending memory)
    parameter MCNTRL_SCANLINE_DLY_WIDTH =   12,  // delay start pulse by 1..64 mclk
    parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63  // initial delay value for start pulse
    
@@ -343,6 +344,7 @@ module  mcntrl393 #(
    input                      [3:0] cmprs_frame_start_dst,    // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
                                                               // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                               // (compress from memory)
+    output                     [3:0] cmprs_frame_start_conf,   // @mclk lags by 1 from cmprs_frame_start_dst, more if there are outstanding memory transactions
    output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
    output   [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src,   // current frame number (for multi-frame ranges) in the source (sensor) channel
    output                     [3:0] cmprs_frame_done_src,     // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory 
@@ -1116,6 +1118,7 @@ module  mcntrl393 #(
                .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),
                .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),
                .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE),
+                .MCONTR_LINTILE_ABORT_LATE         (MCONTR_LINTILE_ABORT_LATE),
                .MCNTRL_SCANLINE_DLY_WIDTH         (MCNTRL_SCANLINE_DLY_WIDTH),
                .MCNTRL_SCANLINE_DLY_DEFAULT       (MCNTRL_SCANLINE_DLY_DEFAULT)
            ) mcntrl_linear_wr_sensor_i (
@@ -1191,7 +1194,9 @@ module  mcntrl393 #(
                .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
                .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT),
                .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED),
-                .MCONTR_LINTILE_COPY_FRAME     (MCONTR_LINTILE_COPY_FRAME)
+                .MCONTR_LINTILE_COPY_FRAME     (MCONTR_LINTILE_COPY_FRAME),
+                .MCONTR_LINTILE_ABORT_LATE     (MCONTR_LINTILE_ABORT_LATE)
+                
            ) mcntrl_tiled_rd_compressor_i ( 
                .mrst                 (mrst),                         // input
                .mclk                 (mclk),                        // input
@@ -1201,6 +1206,7 @@ module  mcntrl393 #(
                .status_rq            (status_cmprs_rq[i]),          // output
                .status_start         (status_cmprs_start[i]),       // input
                .frame_start          (cmprs_frame_start_dst[i]),    // input
+                .frame_start_conf     (cmprs_frame_start_conf[i]),   // output
                .next_page            (cmprs_next_page[i]),          // input compressor consumed page cmprs_buf_wpage_nxt?
                .frame_done           (cmprs_frame_done_dst[i]),     // output
                .frame_finished       (),                            // output
@@ -1270,6 +1276,7 @@ module  mcntrl393 #(
        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),
        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),
        .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE),
+        .MCONTR_LINTILE_ABORT_LATE         (MCONTR_LINTILE_ABORT_LATE),
        .MCNTRL_SCANLINE_DLY_WIDTH         (MCNTRL_SCANLINE_DLY_WIDTH),
        .MCNTRL_SCANLINE_DLY_DEFAULT       (MCNTRL_SCANLINE_DLY_DEFAULT)
         
@@ -1345,6 +1352,7 @@ module  mcntrl393 #(
        .MCONTR_LINTILE_REPEAT             (MCONTR_LINTILE_REPEAT),
        .MCONTR_LINTILE_DIS_NEED           (MCONTR_LINTILE_DIS_NEED),
        .MCONTR_LINTILE_SKIP_LATE          (MCONTR_LINTILE_SKIP_LATE),
+        .MCONTR_LINTILE_ABORT_LATE         (MCONTR_LINTILE_ABORT_LATE),
        .MCNTRL_SCANLINE_DLY_WIDTH         (MCNTRL_SCANLINE_DLY_WIDTH),
        .MCNTRL_SCANLINE_DLY_DEFAULT       (MCNTRL_SCANLINE_DLY_DEFAULT)
    ) mcntrl_linear_rw_chn3_i (
@@ -1418,7 +1426,8 @@ module  mcntrl393 #(
        .MCONTR_LINTILE_RST_FRAME      (MCONTR_LINTILE_RST_FRAME),
        .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
        .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT),
-        .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED) 
+        .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED),
+        .MCONTR_LINTILE_ABORT_LATE     (MCONTR_LINTILE_ABORT_LATE)
    ) mcntrl_tiled_rw_chn2_i ( 
        .mrst                 (mrst),                       // input
        .mclk                 (mclk),                       // input
@@ -1428,6 +1437,7 @@ module  mcntrl393 #(
        .status_rq            (status_tiled_chn2_rq),       // output
        .status_start         (status_tiled_chn2_start),    // input
        .frame_start          (frame_start_chn2),           // input
+        .frame_start_conf     (),                           // output
        .next_page            (next_page_chn2),             // input
        .frame_done           (frame_done_chn2),            // output
        .frame_finished       (),                           // output
@@ -1490,7 +1500,8 @@ module  mcntrl393 #(
        .MCONTR_LINTILE_RST_FRAME      (MCONTR_LINTILE_RST_FRAME),
        .MCONTR_LINTILE_SINGLE         (MCONTR_LINTILE_SINGLE),
        .MCONTR_LINTILE_REPEAT         (MCONTR_LINTILE_REPEAT),
-        .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED)
+        .MCONTR_LINTILE_DIS_NEED       (MCONTR_LINTILE_DIS_NEED),
+        .MCONTR_LINTILE_ABORT_LATE     (MCONTR_LINTILE_ABORT_LATE)
    ) mcntrl_tiled_rw_chn4_i ( 
        .mrst                 (mrst),                       // input
        .mclk                 (mclk),                       // input
@@ -1500,6 +1511,7 @@ module  mcntrl393 #(
        .status_rq            (status_tiled_chn4_rq),       // output
        .status_start         (status_tiled_chn4_start),    // input
        .frame_start          (frame_start_chn4),           // input
+        .frame_start_conf     (),                           // output
        .next_page            (next_page_chn4),             // input
        .frame_done           (frame_done_chn4),            // output
        .frame_finished       (),                           // output

--- a/memctrl/mcntrl_linear_rw.v
+++ b/memctrl/mcntrl_linear_rw.v
@@ -78,6 +78,7 @@ module  mcntrl_linear_rw #(
    parameter MCONTR_LINTILE_REPEAT =          10, // read/write pages until disabled 
    parameter MCONTR_LINTILE_DIS_NEED =        11, // disable 'need' request 
    parameter MCONTR_LINTILE_SKIP_LATE =       12, // skip actual R/W operation when it is too late, advance pointers
+    parameter MCONTR_LINTILE_ABORT_LATE =      14,  // abort frame if not finished by the new frame sync (wait pending memory)
    
 // TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
 // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - 
@@ -179,6 +180,8 @@ module  mcntrl_linear_rw #(
    wire                          chn_en;       // enable requests by channel (continue ones in progress), enable frame_start_late inputs
    wire                          chn_rst;      // resets command, including fifo;
    reg                           chn_rst_d;    // delayed by 1 cycle do detect turning off
+    wire                          abort_en;     // enable frame abort (mode register bit)
+    reg                           aborting_r;   // waiting pending memory transactions at if the frame was not finished at frame sync
 //    reg                           xfer_reset_page_r;
    reg                           xfer_page_rst_r=1;
    reg                           xfer_page_rst_pos=1;  
@@ -199,6 +202,7 @@ module  mcntrl_linear_rw #(
    
    reg                           busy_r;
    reg                           want_r;
+    reg                           want_d; // want_r delayed (no gap to pending_xfers)
    reg                           need_r;
    reg                           frame_done_r;
    reg                           frame_finished_r;    
@@ -232,7 +236,7 @@ module  mcntrl_linear_rw #(
    wire                          msw_zero=  !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
      
    
-    reg                    [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
+    reg                    [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
    
    reg   [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
    reg   [NUM_RC_BURST_BITS-1:0] frame_size;       // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
@@ -263,6 +267,8 @@ module  mcntrl_linear_rw #(
    reg                           buf_reset_pend;  // reset buffer page at next (late)frame sync (compressor should be disabled
                                                   // if total  number of pages in a frame is not multiple of 4 
                                                   
+//    wire                                                
+    
    assign frame_number =       frame_number_current;
    
    assign set_mode_w =         cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
@@ -284,7 +290,7 @@ module  mcntrl_linear_rw #(
    // Set parameter registers
    always @(posedge mclk) begin
        if      (mrst)               mode_reg <= 0;
-        else if (set_mode_w)         mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0];
+        else if (set_mode_w)         mode_reg <= cmd_data[14:0]; // 4:0]; // [4:0];

        if (mrst) single_frame_r <= 0;
        else      single_frame_r <= single_frame_w;
@@ -393,7 +399,7 @@ module  mcntrl_linear_rw #(
    // accelerating pre_want:
 //    assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
    // last_block was too late to inclusde in pre_want_r1, moving it here
-    assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend  && !last_block;
+    assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend  && !last_block && !aborting_r;

    assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
    assign last_row_w=  next_y==window_height;
@@ -410,6 +416,8 @@ module  mcntrl_linear_rw #(
    assign repeat_frames=    mode_reg[MCONTR_LINTILE_REPEAT];
    assign disable_need =    mode_reg[MCONTR_LINTILE_DIS_NEED];
    assign skip_too_late =   mode_reg[MCONTR_LINTILE_SKIP_LATE];
+    assign abort_en =        mode_reg[MCONTR_LINTILE_ABORT_LATE];
+    
    assign status_data= {frame_finished_r, busy_r};     // TODO: Add second bit?
    assign pgm_param_w=      cmd_we;
    localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
@@ -440,7 +448,6 @@ module  mcntrl_linear_rw #(
        if (mrst) xfer_reject_r <= 0;
        else      xfer_reject_r <= xfer_grant && !chn_rst && skip_run;

-
        if (mrst) xfer_start_r <= 0;
        else      xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};

@@ -478,6 +485,7 @@ module  mcntrl_linear_rw #(
        if (mrst)                                                  want_r <= 0;
        else if (chn_rst || xfer_grant || start_skip_r)            want_r <= 0;
        else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1;
+        want_d <= want_r;        
        
    end    
    
@@ -571,9 +579,14 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
        else if (frame_start_r[0])  continued_xfer <= 1'b0;
        else if (xfer_start_r[0])   continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change

-        // single cycle (sent out)
+        // single cycle (sent out), will alos reset busy, set frame_finished, ...
        if (mrst)         frame_done_r <= 0;
-        else              frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
+//        else              frame_done_r <= busy_r && (last_block || aborting_r) && xfer_done_d && (pending_xfers==0);
+        else              frame_done_r <= busy_r && (pending_xfers==0) &&
+                                         ((last_block && xfer_done_d) || (aborting_r && !want_r && !want_d));
+        
+        if      (!busy_r)                           aborting_r <= 0;
+        else if (abort_en && busy_r && frame_start) aborting_r <= 1; // Early frame start, not delayed
        
        // turns and stays on (used in status)
        if (mrst)                             frame_finished_r <= 0;

--- a/memctrl/mcntrl_tiled_rw.v
+++ b/memctrl/mcntrl_tiled_rw.v
@@ -83,7 +83,9 @@ module  mcntrl_tiled_rw#(
    parameter MCONTR_LINTILE_SINGLE =        9, // read/write a single page 
    parameter MCONTR_LINTILE_REPEAT =       10, // read/write pages until disabled
    parameter MCONTR_LINTILE_DIS_NEED =     11, // disable 'need' request
-    parameter MCONTR_LINTILE_COPY_FRAME =   13  // copy frame number from the master channel (single event, not a persistent mode)
+    parameter MCONTR_LINTILE_COPY_FRAME =   13, // copy frame number from the master channel (single event, not a persistent mode)
+    parameter MCONTR_LINTILE_ABORT_LATE =   14  // abort frame if not finished by the new frame sync (wait pending memory)
+    
 )(
    input                          mrst,
    input                          mclk,
@@ -96,6 +98,8 @@ module  mcntrl_tiled_rw#(
    input                          status_start,   // acknowledge of address (first byte) from downsteram   

    input                          frame_start,   // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
+    output                         frame_start_conf, // frame start modified by memory controller. Normally delayed by 1 cycle,
+                                                     // or more if memory transactions are to be finished 
    input                          next_page,     // page was read/written from/to 4*1kB on-chip buffer
 //    output                         page_ready,    // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
    output                         frame_done,    // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
@@ -176,6 +180,10 @@ module  mcntrl_tiled_rw#(
    wire                          chn_en;   // enable requests by channel (continue ones in progress), enable frame_start inputs
    wire                          chn_rst; // resets command, including fifo;
    reg                           chn_rst_d; // delayed by 1 cycle do detect turning off
+    wire                          abort_en;     // enable frame abort (mode register bit)
+    reg                           aborting_r;   // waiting pending memory transactions at if the frame was not finished at frame sync
+    reg                           aborting_d;   // aborting_r delayed by 1 cycle
+    reg                           frame_start_mod; // either original frame start pulse or delayed during abort (delayed by 1 cycle)
    reg                           xfer_page_rst_r=1;
    reg                           xfer_page_rst_pos=1;  
    reg                           xfer_page_rst_neg=1;  
@@ -196,6 +204,7 @@ module  mcntrl_tiled_rw#(
    
    reg                           busy_r;
    reg                           want_r;
+    reg                           want_d; // want_r delayed (no gap to pending_xfers)
    reg                           need_r;
    reg                           frame_done_r;
    reg                           frame_finished_r;    
@@ -236,7 +245,7 @@ module  mcntrl_tiled_rw#(
    
 //    reg                     [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
 //    reg                     [6:0] mode_reg;//mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
-    reg                    [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
+    reg                    [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
    reg   [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
    reg   [NUM_RC_BURST_BITS-1:0] frame_size;       // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
    reg     [LAST_FRAME_BITS-1:0] last_frame_number; 
@@ -291,13 +300,15 @@ module  mcntrl_tiled_rw#(
    
    assign single_frame_w =       cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
    assign rst_frame_num_w =      cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
-    assign set_copy_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_COPY_FRAME];
+    assign set_copy_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_COPY_FRAME]; // self-clearing bit
    
+    assign frame_start_conf = frame_start_r[3]; // frame_number valid
+//    assign frame_start_mod = (!busy_r && frame_start) || (aborting_d && !aborting_r);    
    //
    // Set parameter registers
    always @(posedge mclk) begin
        if      (mrst)               mode_reg <= 0;
-        else if (set_mode_w)         mode_reg <= cmd_data[11:0]; // [5:0];
+        else if (set_mode_w)         mode_reg <= cmd_data[14:0]; // [5:0];
        
        if (mrst) single_frame_r <= 0;
        else      single_frame_r <= single_frame_w;
@@ -326,12 +337,12 @@ module  mcntrl_tiled_rw#(
        else     is_last_frame <= frame_number_cntr == last_frame_number;
        
        if (mrst) frame_start_r <= 0;
-        else     frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
+        else      frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start

 //        if      (mrst)                            frame_en <= 0;
        if      (!chn_en)                         frame_en <= 0;
        else if (single_frame_r || repeat_frames) frame_en <= 1;
-        else if (frame_start)                     frame_en <= 0;
+        else if (frame_start_mod)                 frame_en <= 0;
        
        if      (mrst ||master_set)     frame_master_pend <= 0;
        else if (set_copy_frame_num_w)  frame_master_pend <= 1;
@@ -409,7 +420,7 @@ module  mcntrl_tiled_rw#(
    assign calc_valid=  par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
    assign frame_done=      frame_done_r;
    assign frame_finished=  frame_finished_r;
-    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
+    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r) && !aborting_r;
    assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
 // tiles must completely fit window
 // all window should be covered (tiles may extend):    
@@ -431,6 +442,7 @@ module  mcntrl_tiled_rw#(
    assign byte32=           mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte) 
    assign repeat_frames=    mode_reg[MCONTR_LINTILE_REPEAT];
    assign disable_need =    mode_reg[MCONTR_LINTILE_DIS_NEED];
+    assign abort_en =        mode_reg[MCONTR_LINTILE_ABORT_LATE];
    assign status_data=      {frame_finished_r, busy_r}; 
    assign pgm_param_w=      cmd_we;
    assign rowcol_inc=       frame_full_width;
@@ -450,6 +462,7 @@ module  mcntrl_tiled_rw#(
    wire xfer_limited_by_mem_page;
    reg  xfer_limited_by_mem_page_r;
    assign xfer_limited_by_mem_page= keep_open && (mem_page_left < {EXTRA_BITS,lim_by_tile_width}); // if not keep_open - no need to break
+    
    always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
    // cycle 1
        if (recalc_r[0]) begin
@@ -547,9 +560,10 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
        if (mrst)                                                want_r <= 0;
        else if (chn_rst || xfer_grant)                          want_r <= 0;
        else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
-        
+        want_d <= want_r;        
        if (mrst)                                  page_cntr <= 0;
-        else if (frame_start_r[0])                 page_cntr <= cmd_wrmem?0:4;
+//        else if (frame_start_r[0])                 page_cntr <= cmd_wrmem?0:4; // reset here, but compressor is not
+        else if (xfer_page_rst_pos)                page_cntr <= cmd_wrmem?0:4; // reset here, but compressor is not
        else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;     
        else if (!start_not_partial &&  next_page) page_cntr <= page_cntr + 1;
        
@@ -580,8 +594,22 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
        else if (!xfer_start_r[0] &&  xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages
        
        // single cycle (sent out)
+//        if (mrst)          frame_done_r <= 0;
+//        else              frame_done_r <= busy_r && last_block && xfer_page_done_d && (pending_xfers==0);
+
        if (mrst)         frame_done_r <= 0;
-        else              frame_done_r <= busy_r && last_block && xfer_page_done_d && (pending_xfers==0);
+//        else              frame_done_r <= busy_r && (last_block || aborting_r) && xfer_page_done_d && (pending_xfers==0);
+        else              frame_done_r <= busy_r && (pending_xfers==0) &&
+                                          ((last_block && xfer_page_done_d) || (aborting_r && !want_r && !want_d));
+        
+
+        aborting_d <= aborting_r;
+
+        if      (!busy_r)                           aborting_r <= 0;
+        else if (abort_en && busy_r && frame_start) aborting_r <= 1;
+
+
+        frame_start_mod <= (frame_start && !busy_r) || (aborting_d && !aborting_r);    

        // turns and stays on (used in status)
        if (mrst)                             frame_finished_r <= 0;
@@ -612,7 +640,7 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
 */
        if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: tile_rows);
        
-        if (mrst || (frame_start || !chn_en))  line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
+        if (mrst || (frame_start_mod || !chn_en))  line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
        else if (recalc_r[2])                      line_unfinished_r <= line_unfinished_relw_r + window_y0;
        
    end

--- a/py393/vrlg.py
+++ b/py393/vrlg.py
@@ -1040,6 +1040,7 @@ MULT_SAXI_IRQLEN_ADDR__RAW = str
 SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
 MCNTRL_SCANLINE_FRAME_LAST = int
 MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
+SENS_GAMMA_BUFFER = int
 GPIO_SET_PINS__RAW = str
 SENS_CTRL_RST_MMCM__TYPE = str
 AFI_MUX_BUF_LATENCY__RAW = str
@@ -1505,6 +1506,7 @@ CMPRS_AFIMUX_STATUS_CNTRL = int
 CMPRS_CBIT_FRAMES__RAW = str
 SLEW_DQS = str
 MCONTR_WR_MASK = int
+MCONTR_LINTILE_ABORT_LATE = int
 CMPRS_FRMT_MBCM1 = int
 MEMBRIDGE_STATUS_CNTRL__TYPE = str
 GPIO_IOSTANDARD__TYPE = str
@@ -1540,7 +1542,6 @@ LOGGER_PAGE_MSG = int
 SENS_HIGH_PERFORMANCE_MODE = str
 WINDOW_X0 = int
 INITIALIZE_OFFSET__TYPE = str
-SENSOR_FIFO_DELAY__TYPE = str
 LOGGER_CONF_IMU_BITS__TYPE = str
 IDELAY_VALUE__TYPE = str
 SENSOR_IMAGE_TYPE2__RAW = str
@@ -1584,6 +1585,7 @@ QUADRANTS_PXD_HACT_VACT__RAW = str
 MCONTR_CMPRS_STATUS_INC__RAW = str
 CMPRS_CBIT_CMODE_JP4DIFFHDR = int
 TABLE_CORING_INDEX__RAW = str
+MCONTR_LINTILE_ABORT_LATE__TYPE = str
 SENSI2C_CMD_RESET__TYPE = str
 MCONTR_ARBIT_ADDR__TYPE = str
 CAMSYNC_TRIG_DELAY1__RAW = str
@@ -2103,6 +2105,7 @@ HIST_SAXI_EN = int
 RTC_SET_SEC = int
 MCONTR_LINTILE_SINGLE__TYPE = str
 DLY_DQ_IDELAY__RAW = str
+MCONTR_LINTILE_ABORT_LATE__RAW = str
 SENSOR_CTRL_RADDR__RAW = str
 CMPRS_MONO16 = int
 REF_JITTER1 = float
@@ -2131,7 +2134,7 @@ HISPI_CAPACITANCE__RAW = str
 CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
 HISPI_DIFF_TERM__RAW = str
 BUF_IPCLK_SENS2__TYPE = str
-SENS_GAMMA_BUFFER = int
+SENSOR_FIFO_DELAY__TYPE = str
 CMDFRAMESEQ_ABS__TYPE = str
 NUM_CYCLES_06__RAW = str
 SENS_JTAG_TDI = int

--- a/py393/x393_cmprs.py
+++ b/py393/x393_cmprs.py
@@ -351,6 +351,7 @@ class X393Cmprs(object):
                              command,
                              reset_frame = False,
                              copy_frame = False,
+                              abort_late = False,
                              verbose = 1):
        """
        Control memory access (write) of a sensor channel
@@ -361,7 +362,8 @@ class X393Cmprs(object):
               single      - acquire single frame ,
               repetitive  - repetitive mode
        @param reset_frame - reset frame number
-        @param copy_frame  copy frame number from the master channel (non-persistent)
+        @param copy_frame  - copy frame number from the master channel (non-persistent)
+        @param abort_late  -  abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
        @param vebose -      verbose level       
        """
        try:
@@ -372,6 +374,7 @@ class X393Cmprs(object):
                                                   command =    command,
                                                   reset_frame = reset_frame,
                                                   copy_frame = copy_frame,
+                                                   abort_late = abort_late,
                                                   verbose =    verbose)
                return
        except:
@@ -410,7 +413,8 @@ class X393Cmprs(object):
                                   write_mem =    False,
                                   enable =       en,
                                   chn_reset =    rst,
-                                   copy_frame = copy_frame)
+                                   copy_frame = copy_frame,
+                                   abort_late =   abort_late)
        
        self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE,  mode) 
        if verbose > 0 :
@@ -434,7 +438,8 @@ class X393Cmprs(object):
                                 tile_vstep, # = 16
                                 tile_height, #= 18
                                 extra_pages,
-                                 disable_need):
+                                 disable_need,
+                                 abort_late = False):
        """
        Setup memory controller for a compressor channel
        @param num_sensor -       sensor port number (0..3)
@@ -452,6 +457,7 @@ class X393Cmprs(object):
        @param tile_height        tile height: 18 for color JPEG, 16 fore JP$ flavors,
        @param extra_pages        extra pages needed (1)
        @param disable_need       disable need (preference to sensor channels - they can not wait
+        @param abort_late         abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
        """
 #        tile_vstep = 16
 #        tile_height= 18
@@ -467,7 +473,8 @@ class X393Cmprs(object):
                                   extra_pages =  extra_pages,
                                   write_mem =    False,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   abort_late)
        self.x393_axi_tasks.write_control_register(
                                    base_addr + vrlg.MCNTRL_TILED_STARTADDR,
                                    frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)

--- a/py393/x393_export_c.py
+++ b/py393/x393_export_c.py
@@ -1660,6 +1660,7 @@ class X393ExportC(object):
        dw.append(("disable_need", vrlg.MCONTR_LINTILE_DIS_NEED,1,0,  "disable 'need' generation, only 'want' (compressor channels)"))
        dw.append(("skip_too_late",vrlg.MCONTR_LINTILE_SKIP_LATE,1,0, "Skip over missed blocks to preserve frame structure (increment pointers)"))
        dw.append(("copy_frame",   vrlg.MCONTR_LINTILE_COPY_FRAME,1,0, "Copy frame number from the master (sensor) channel. Combine with reset_frame to reset bjuffer"))
+        dw.append(("abort_late",   vrlg.MCONTR_LINTILE_ABORT_LATE,1,0, "abort frame if not finished by the new frame sync (wait pending memory transfers)"))
        return dw
    """
        self.x393_axi_tasks.write_control_register(

--- a/py393/x393_jpeg.py
+++ b/py393/x393_jpeg.py
@@ -1581,6 +1581,72 @@ jpeg_sim_multi 8
 jpeg_sim_multi 8
 jpeg_sim_multi 4

+################## Simulate Parallel 6 ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+#just testing
+set_gpio_ports  1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+#sequencer test
+#ctrl_cmd_frame_sequencer  <num_sensor>  <reset=False>  <start=False>  <stop=False>
+ctrl_cmd_frame_sequencer   0  0  1  0
+write_cmd_frame_sequencer  0  1  1  0x700  0x6
+write_cmd_frame_sequencer  0  1  1  0x700  0x9
+write_cmd_frame_sequencer  0  1  1  0x700  0xa0
+write_cmd_frame_sequencer  0  1  1  0x700  0x50
+write_cmd_frame_sequencer  0  0  3  0x700  0xa000
+write_cmd_frame_sequencer  0  1  0  0x700  0x90
+write_cmd_frame_sequencer  0  0  2  0x700  0xe00
+write_cmd_frame_sequencer  0  0  3  0x700  0xa
+write_cmd_frame_sequencer  0  0  2  0x700  0x6
+write_cmd_frame_sequencer  0  0  2  0x700  0x9
+write_cmd_frame_sequencer  0  0  2  0x700  0x60
+write_cmd_frame_sequencer  0  0  2  0x700  0x90
+write_cmd_frame_sequencer  0  0  2  0x700  0x600
+write_cmd_frame_sequencer  0  0  2  0x700  0x900
+
+
+
+
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+jpeg_sim_multi 4
+jpeg_sim_multi 8
+jpeg_sim_multi 4
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+jpeg_sim_multi 12
+




--- a/py393/x393_mcntrl.py
+++ b/py393/x393_mcntrl.py
@@ -51,7 +51,8 @@ def func_encode_mode_scan_tiled   (skip_too_late = False,
                                   write_mem =    False,
                                   enable =       True,
                                   chn_reset =    False,
-                                   copy_frame =   False):
+                                   copy_frame =   False,
+                                   abort_late =   False):
    """
    Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
    @param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
@@ -67,7 +68,7 @@ def func_encode_mode_scan_tiled   (skip_too_late = False,
    @param enable,       enable requests from this channel ( 0 will let current to finish, but not raise want/need)
    @param chn_reset   immediately reset all the internal circuitry
    @param copy_frame  copy frame number from the master channel (non-persistent)
-    
+    @param abort_late  abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
    """
    rslt = 0;
    rslt |= (1,0)[chn_reset] <<     vrlg.MCONTR_LINTILE_EN # inverted
@@ -83,6 +84,7 @@ def func_encode_mode_scan_tiled   (skip_too_late = False,
    rslt |= (0,1)[disable_need] <<  vrlg.MCONTR_LINTILE_DIS_NEED
    rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
    rslt |= (0,1)[copy_frame] <<    vrlg.MCONTR_LINTILE_COPY_FRAME
+    rslt |= (0,1)[copy_frame] <<    vrlg.MCONTR_LINTILE_ABORT_LATE
    return rslt

 '''

--- a/py393/x393_mcntrl_membridge.py
+++ b/py393/x393_mcntrl_membridge.py
@@ -313,7 +313,8 @@ class X393McntrlMembridge(object):
                                   extra_pages =  0,
                                   write_mem =    write_ddr3,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)

 #        self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);    
 #        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE,             0); # reset channel, including page address

--- a/py393/x393_mcntrl_tests.py
+++ b/py393/x393_mcntrl_tests.py
@@ -298,7 +298,8 @@ class X393McntrlTests(object):
                                   extra_pages =  extra_pages,
                                   write_mem =    True,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)
            
                                
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
@@ -451,7 +452,8 @@ class X393McntrlTests(object):
                                   extra_pages =  extra_pages,
                                   write_mem =    False,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)
            
 # program to the
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
@@ -568,7 +570,8 @@ class X393McntrlTests(object):
                                   extra_pages =  extra_pages,
                                   write_mem =    True,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)
                                                        
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
@@ -711,7 +714,8 @@ class X393McntrlTests(object):
                                   extra_pages =  extra_pages,
                                   write_mem =    False,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)
            
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
        self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,

--- a/py393/x393_sens_cmprs.py
+++ b/py393/x393_sens_cmprs.py
@@ -615,6 +615,7 @@ class X393SensCmprs(object):
            print ("tile_height =     18")
            print ("extra_pages =      1")
            print ("disable_need =     1")
+            print ("abort_late =       0")

        self.x393Cmprs.setup_compressor_memory (
            num_sensor =       num_sensor,
@@ -631,7 +632,8 @@ class X393SensCmprs(object):
            tile_vstep =      16,
            tile_height =     18,
            extra_pages =      1,
-            disable_need =     1)
+            disable_need =     1,
+            abort_late =       False)

        if exit_step == 15: return False
    
@@ -1207,6 +1209,7 @@ class X393SensCmprs(object):
            print ("tile_height =      0x%x"%(tile_height))
            print ("extra_pages =      0x%x"%(extra_pages))
            print ("disable_need =     1")
+            print ("abort_late =       0")

        self.x393Cmprs.setup_compressor_memory (
            num_sensor =       num_sensor,
@@ -1223,7 +1226,9 @@ class X393SensCmprs(object):
            tile_vstep =       tile_vstep,
            tile_height =      tile_height,
            extra_pages =      extra_pages,
-            disable_need =     1)
+            disable_need =     1,
+            abort_late =       False)
+
    def reset_channels(self,
                       sensor_mask = 0x1,
                       reset_mask =  0xf):
@@ -1852,7 +1857,8 @@ class X393SensCmprs(object):
                                   extra_pages =  0,
                                   write_mem =    write_mem,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False)

        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR,        frame_start_address) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) 
        self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, frame_full_width)

--- a/py393/x393_sensor.py
+++ b/py393/x393_sensor.py
@@ -1919,6 +1919,7 @@ input               mem                 mtd4                ram1
                              num_sensor,
                              command,
                              reset_frame = False,
+                              abort_late =   False,
                              verbose = 1):
        """
        Control memory access (write) of a sensor channel
@@ -1929,6 +1930,8 @@ input               mem                 mtd4                ram1
               single      - acquire single frame ,
               repetitive  - repetitive mode
        @param reset_frame - reset frame number. Needed after changing frame start address (i.e. initial set-up) !
+        @param abort_late    abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
+
        @param vebose -      verbose level       
        """
        try:
@@ -1938,6 +1941,7 @@ input               mem                 mtd4                ram1
                    self.control_sensor_memory(num_sensor =  num_sensor,
                                               command =     command,
                                               reset_frame = reset_frame,
+                                               abort_late =  abort_late, 
                                               verbose =     verbose)
                return
        except:
@@ -1972,7 +1976,8 @@ input               mem                 mtd4                ram1
                                   extra_pages =  0,
                                   write_mem =    True,
                                   enable =       en,
-                                   chn_reset =    rst)
+                                   chn_reset =    rst,
+                                   abort_late =   abort_late)
        self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_MODE,  mode) 
        if verbose > 0 :
            print ("write_control_register(0x%08x, 0x%08x)"%(base_addr + vrlg.MCNTRL_SCANLINE_MODE,  mode))
@@ -2009,7 +2014,8 @@ input               mem                 mtd4                ram1
                                   extra_pages =  0,
                                   write_mem =    True,
                                   enable =       True,
-                                   chn_reset =    False)
+                                   chn_reset =    False,
+                                   abort_late =   False) # default, change with  control_sensor_memory()
                    
        self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_STARTADDR,
                                                  frame_sa); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)

--- a/x393.v
+++ b/x393.v
@@ -521,6 +521,8 @@ module  x393 #(
    wire                     [3:0] cmprs_frame_start_dst; // output - trigger receive (tiledc) memory channel (it will take care of single/repetitive
                                                          // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                          // (compress from memory)
+    wire                     [3:0] cmprs_frame_start_conf; // memory controller confirmed cmprs_frame_start_dst - normally delayed by 1 clock,
+                                                           // or more if there were outstanding memory transactions.                                                           
    wire [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src; // input[15:0] number of the current (unfinished ) line, in the source (sensor)
                                                          //  channel (RELATIVE TO FRAME, NOT WINDOW?)
    wire   [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src;// input[15:0] current frame number (for multi-frame ranges) in the source (sensor) channel
@@ -1350,6 +1352,7 @@ assign axi_grst = axi_rst_pre;
        .cmprs_next_page           (cmprs_next_page),            // input[3:0] 
        .cmprs_first_rd_in_frame   (),                           // output[3:0] reg 
        .cmprs_frame_start_dst     (cmprs_frame_start_dst),      // input[3:0]
+        .cmprs_frame_start_conf    (cmprs_frame_start_conf),     // output[3:0] 
        .cmprs_line_unfinished_src (cmprs_line_unfinished_src),  // output[63:0] 
        .cmprs_frame_number_src    (cmprs_frame_number_src),     // output[63:0] 
        .cmprs_frame_done_src      (cmprs_frame_done_src),       // output[3:0] 
@@ -2088,6 +2091,8 @@ assign axi_grst = axi_rst_pre;
        .next_page                 (cmprs_next_page),            // output[3:0]
        
        .frame_start_dst           (cmprs_frame_start_dst),      // output[3:0]
+        .frame_start_conf          (cmprs_frame_start_conf),     // input[3:0] 
+
        .line_unfinished_src       (cmprs_line_unfinished_src),  // input[63:0] 
        .frame_number_src          (cmprs_frame_number_src),     // input[63:0] 
        .frame_done_src            (cmprs_frame_done_src),       // input[3:0]