Commit 988095ef authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Fixed handling AXI write responce channel - both in work and simulation... 

Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
parent 0fda102e

.project

+15 −15
Original line number Diff line number Diff line
@@ -62,77 +62,77 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150504180215142.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150505101739146.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150504180215142.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150505101739146.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150504180408074.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150505101930202.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150504180215142.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150505101739146.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150504180408074.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150505101930202.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-place.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150504180408074.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150505101930202.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-route.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150504180408074.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150505101930202.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150504180215142.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150505101739146.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

axi/axibram_write.v

+6 −4
Original line number Diff line number Diff line
@@ -135,9 +135,11 @@ module axibram_write #( 
        (wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));

        

    assign      bram_we_w=         w_nempty_ready &&  write_in_progress;

    assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));

//    assign write_in_progress_w=                  aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

    assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

//    assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));

//    assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); 

    // adding wlast_out to take precedence over (write_left[3:0]==4'b0), maybe wlast_out itself is sufficient

    assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));

    assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out))); 

    

    always @ (posedge  aclk or posedge  rst) begin

      if   (rst)                    wburst[1:0] <= 0;
@@ -249,7 +251,7 @@ fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4)) 
        .rst(rst),

        .clk(aclk),

        .sync_rst  (1'b0),

        .we(bram_we_w),

        .we(bram_we_w &&((write_left[3:0]==4'b0) || wlast_out)), // added ((write_left[3:0]==4'b0) || wlast_out) - only last wrtite -> bresp

//        .re(bready && bvalid),

        .re(bresp_re), // not allowing RE next cycle after bvalid

        .data_in({wid_out[11:0],bresp_in[1:0]}),

axi/membridge.v

+19 −8
Original line number Diff line number Diff line
@@ -355,6 +355,7 @@ module membridge#( 
    wire       rw_in_progress;

    reg        busy;

    reg        done;

    reg        pre_done;



    assign rw_in_progress = read_started || write_busy;
@@ -393,13 +394,15 @@ module membridge#( 
    // DDR3 read - AFI write

    //rdwr_en    

    reg  [7:0] axi_arw_requested;     // 64-bit words to be read/written over axi queued to AR/AW channels

    reg  [7:0] axi_bursts_requested;  // number of bursts requested

    reg  [7:0] wresp_conf;         // number of 64-bit words confirmed through axi b channel

    wire [7:0] axi_wr_pending;     // Number of words qued to AW but not yet confirmed through B-channel;

    wire [7:0] axi_rd_pending;



    reg  [7:0] axi_rd_received;

    assign axi_rd_pending= axi_arw_requested - axi_rd_received;

    assign axi_wr_pending= axi_arw_requested - wresp_conf;

//    assign axi_wr_pending= axi_arw_requested - wresp_conf;

    assign axi_wr_pending= axi_bursts_requested - wresp_conf;

    

    reg        read_busy;

    reg        read_over;
@@ -480,9 +483,12 @@ module membridge#( 
        if (rst) busy <= 0;

        else     busy <=  read_busy || write_busy;

        

        if (rst) pre_done <= 0; // delay done to turn on same time busy is off

        else     pre_done <= (write_busy && frame_done) || (read_busy && read_over);

        

        if      (rst)            done <= 0;

        else if (!rdwr_en)       done <= 0; // disabling when idle will reset done

        else if ((write_busy && frame_done) || (read_busy && read_over)) done <= 1;

        else if (pre_done)       done <= 1;

        else if (rdwr_start)     done <= 0;

        

    end
@@ -574,6 +580,10 @@ module membridge#( 
        else if (!write_busy && !read_started)  axi_arw_requested <= 0;

        else if (advance_rel_addr)              axi_arw_requested <= axi_arw_requested + afi_len_plus1;

        

        if      (rst)                           axi_bursts_requested <= 0;

        else if (!write_busy && !read_started)  axi_bursts_requested <= 0;

        else if (advance_rel_addr)              axi_bursts_requested <= axi_bursts_requested + 1;



        if      (rst)              axi_rd_received <= 0;

        else if (!write_busy)      axi_rd_received <= 0;

        else if (bufwr_we[0])      axi_rd_received <= axi_rd_received + 1;
@@ -630,7 +640,7 @@ module membridge#( 
`ifdef MEMBRIDGE_DEBUG_READ

        .PAYLOAD_BITS     (18) // 2) // With debug

`else

        .PAYLOAD_BITS     (2)

        .PAYLOAD_BITS     (18) //2)

`endif        

    ) status_generate_i (

        .rst              (rst), // input
@@ -640,7 +650,8 @@ module membridge#( 
`ifdef MEMBRIDGE_DEBUG_READ

        .status           ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]

`else

        .status           ({done,busy}), // input[25:0] 

//        .status           ({done,busy}), // input[25:0] 

        .status           ({axi_arw_requested, wresp_conf, done, busy}), // input[25:0] 

`endif

        .ad               (status_ad), // output[7:0] 

        .rq               (status_rq), // output

includes/x393_tasks_mcntrl_buffers.vh

+2 −2
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ task write_block_incremtal; 
                    i,        // id

                    start_value+i+j,

                    4'hf, // wstrb

                    (1 == 15) ? 1 : 0 // last

                    (j == 15) ? 1 : 0 // last

                    );

                $display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);

            end
@@ -122,7 +122,7 @@ task write_block_buf; 
                    i,        // id

                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),

                    4'hf, // wstrb

                    (1 == 15) ? 1 : 0 // last

                    (j == 15) ? 1 : 0 // last

                    );

                $display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),

                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);

py393/x393_mcntrl_membridge.py

+3 −3
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ class X393McntrlMembridge(object): 
                    1, # enable

                    0)  # chn_reset

#        self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);    

                    

#        self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE,             0); # reset channel, including page address

        self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR,        frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) 

        self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);

        self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH,        (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
@@ -320,10 +320,10 @@ class X393McntrlMembridge(object): 
        if wait_ready:

            self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status

                vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,

                vrlg.MCNTRL_SCANLINE_CHN1_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,

                vrlg.MEMBRIDGE_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,

                vrlg.DEFAULT_STATUS_MODE,

                2 << vrlg.STATUS_2LSB_SHFT, # bit 24 - busy, bit 25 - frame done

                2 << vrlg.STATUS_2LSB_SHFT,  # mask for the 4-bit page number

                0, # equal to

                0); # no need to synchronize sequence number

                1); # synchronize sequence number