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x393
Commit 952b1c1a authored by Andrey Filippov's avatar Andrey Filippov
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Updating to what was changed fro x393_sata

parent 9024d1d4
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axi/axibram_write.v
View file @ 952b1c1a
...@@ -71,7 +71,8 @@ module axibram_write #( ...@@ -71,7 +71,8 @@ module axibram_write #(
output bram_wclk, output bram_wclk,
output [ADDRESS_BITS-1:0] bram_waddr, output [ADDRESS_BITS-1:0] bram_waddr,
output bram_wen, // external memory wreite enable, (internally combined with registered dev_ready output pre_bram_wen,// 1 ahead of bram_wen, not masked by dev_ready
output bram_wen, // external memory write enable, (internally combined with registered dev_ready
output [3:0] bram_wstb, output [3:0] bram_wstb,
output [31:0] bram_wdata output [31:0] bram_wdata
`ifdef DEBUG_FIFO `ifdef DEBUG_FIFO
...@@ -151,6 +152,7 @@ module axibram_write #( ...@@ -151,6 +152,7 @@ module axibram_write #(
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out))); assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out))); assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && ((write_left[3:0]==4'b0) || wlast_out)));
assign pre_bram_wen = write_in_progress_w;
always @ (posedge aclk) begin always @ (posedge aclk) begin
if (arst) wburst[1:0] <= 0; if (arst) wburst[1:0] <= 0;
else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0]; else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];
......
wrap/ram_var_w_var_r.v
View file @ 952b1c1a
...@@ -76,6 +76,11 @@ module ram_var_w_var_r ...@@ -76,6 +76,11 @@ module ram_var_w_var_r
parameter integer LOG2WIDTH_WR = 6, // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_WR = 6, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 6, // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_RD = 6, // WIDTH= 1 << LOG2WIDTH
parameter DUMMY = 0 parameter DUMMY = 0
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
) )
( (
input rclk, // clock for read port input rclk, // clock for read port
...@@ -101,6 +106,9 @@ module ram_var_w_var_r ...@@ -101,6 +106,9 @@ module ram_var_w_var_r
else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6)) else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))
ram_64w_64r #( ram_64w_64r #(
.REGISTERS (REGISTERS) .REGISTERS (REGISTERS)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i ( ) ram_i (
.rclk (rclk), // input .rclk (rclk), // input
.raddr (raddr), // input[8:0] .raddr (raddr), // input[8:0]
...@@ -117,6 +125,9 @@ module ram_var_w_var_r ...@@ -117,6 +125,9 @@ module ram_var_w_var_r
ram_64w_lt64r #( ram_64w_lt64r #(
.REGISTERS (REGISTERS), .REGISTERS (REGISTERS),
.LOG2WIDTH_RD (LOG2WIDTH_RD) .LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i ( ) ram_i (
.rclk (rclk), // input .rclk (rclk), // input
.raddr (raddr), // input[(>8):0] .raddr (raddr), // input[(>8):0]
...@@ -133,6 +144,9 @@ module ram_var_w_var_r ...@@ -133,6 +144,9 @@ module ram_var_w_var_r
ram_lt64w_64r #( ram_lt64w_64r #(
.REGISTERS (REGISTERS), .REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR) .LOG2WIDTH_WR (LOG2WIDTH_WR)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i ( ) ram_i (
.rclk (rclk), // input .rclk (rclk), // input
.raddr (raddr), // input[8:0] .raddr (raddr), // input[8:0]
...@@ -150,6 +164,9 @@ module ram_var_w_var_r ...@@ -150,6 +164,9 @@ module ram_var_w_var_r
.REGISTERS (REGISTERS), .REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR), .LOG2WIDTH_WR (LOG2WIDTH_WR),
.LOG2WIDTH_RD (LOG2WIDTH_RD) .LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) ram_i ( ) ram_i (
.rclk (rclk), // input .rclk (rclk), // input
.raddr (raddr), // input[(>8):0] .raddr (raddr), // input[(>8):0]
...@@ -169,6 +186,10 @@ endmodule ...@@ -169,6 +186,10 @@ endmodule
module ram_64w_64r module ram_64w_64r
#( #(
parameter integer REGISTERS = 0 // 1 - registered output parameter integer REGISTERS = 0 // 1 - registered output
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
) )
( (
input rclk, // clock for read port input rclk, // clock for read port
...@@ -207,6 +228,9 @@ module ram_64w_64r ...@@ -207,6 +228,9 @@ module ram_64w_64r
.SIM_DEVICE ("7SERIES"), // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES" .SIM_DEVICE ("7SERIES"), // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i ) RAMB36E1_i
( (
// Port A (Read port in SDP mode): // Port A (Read port in SDP mode):
...@@ -255,6 +279,10 @@ module ram_lt64w_lt64r ...@@ -255,6 +279,10 @@ module ram_lt64w_lt64r
parameter integer REGISTERS = 0, // 1 - registered output parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
) )
( (
input rclk, // clock for read port input rclk, // clock for read port
...@@ -314,6 +342,9 @@ module ram_lt64w_lt64r ...@@ -314,6 +342,9 @@ module ram_lt64w_lt64r
parameter IS_RSTREGARSTREG_INVERTED = 1'b0; parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0; parameter IS_RSTREGB_INVERTED = 1'b0;
*/ */
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i ) RAMB36E1_i
( (
...@@ -362,6 +393,10 @@ module ram_lt64w_64r ...@@ -362,6 +393,10 @@ module ram_lt64w_64r
#( #(
parameter integer REGISTERS = 0, // 1 - registered output parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 5 // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_WR = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
) )
( (
input rclk, // clock for read port input rclk, // clock for read port
...@@ -405,6 +440,9 @@ module ram_lt64w_64r ...@@ -405,6 +440,9 @@ module ram_lt64w_64r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i ) RAMB36E1_i
( (
// Port A (Read port in SDP mode): // Port A (Read port in SDP mode):
...@@ -453,6 +491,10 @@ module ram_64w_lt64r ...@@ -453,6 +491,10 @@ module ram_64w_lt64r
parameter integer REGISTERS = 0, // 1 - registered output parameter integer REGISTERS = 0, // 1 - registered output
// parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH // parameter integer LOG2WIDTH_WR = 5, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH parameter integer LOG2WIDTH_RD = 5 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
) )
( (
input rclk, // clock for read port input rclk, // clock for read port
...@@ -495,6 +537,9 @@ module ram_64w_lt64r ...@@ -495,6 +537,9 @@ module ram_64w_lt64r
.EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_READ ("FALSE"), // Valid:"FALSE","TRUE" (ECC decoder circuitry)
.EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry) .EN_ECC_WRITE ("FALSE") // Valid:"FALSE","TRUE" (ECC decoder circuitry)
`ifdef PRELOAD_BRAMS
`include "includes/ram36_pass_init.vh"
`endif
) RAMB36E1_i ) RAMB36E1_i
( (
// Port A (Read port in SDP mode): // Port A (Read port in SDP mode):
......
x393.v
View file @ 952b1c1a
...@@ -2378,6 +2378,7 @@ assign axi_grst = axi_rst_pre; ...@@ -2378,6 +2378,7 @@ assign axi_grst = axi_rst_pre;
.dev_ready (axiwr_dev_ready), // input .dev_ready (axiwr_dev_ready), // input
.bram_wclk (axiwr_wclk), // output .bram_wclk (axiwr_wclk), // output
.bram_waddr (axiwr_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0] .bram_waddr (axiwr_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.pre_bram_wen(), // 1 ahead of bram_wen, not masked by dev_ready
.bram_wen (axiwr_wen), // output .bram_wen (axiwr_wen), // output
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used .bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used
.bram_wdata (axiwr_wdata[31:0]) // output[31:0] .bram_wdata (axiwr_wdata[31:0]) // output[31:0]
......
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