(('Write-only addresses to program memory channels for sensors (chn = 0..3), memory channels 8..11',)),
(("X393_SENS_MCNTRL_SCANLINE_MODE",c,vrlg.MCNTRL_SCANLINE_MODE+ba,ia,z3,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,ia,z3,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_SENS_MCNTRL_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,ia,z3,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_SENS_MCNTRL_SCANLINE_FRAME_LAST",c,vrlg.MCNTRL_SCANLINE_FRAME_LAST+ba,ia,z3,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
...
...
@@ -537,7 +616,7 @@ class X393ExportC(object):
sdefines+=[
(('Write-only addresses to program memory channels for compressors (chn = 0..3), memory channels 12..15',)),
(("X393_SENS_MCNTRL_TILED_MODE",c,vrlg.MCNTRL_TILED_MODE+ba,ia,z3,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_SENS_MCNTRL_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,ia,z3,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_SENS_MCNTRL_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,ia,z3,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_SENS_MCNTRL_TILED_FRAME_LAST",c,vrlg.MCNTRL_TILED_FRAME_LAST+ba,ia,z3,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
...
...
@@ -553,7 +632,7 @@ class X393ExportC(object):
sdefines+=[
(('Write-only addresses to program memory channel for membridge, memory channel 1',)),
(("X393_MEMBRIDGE_SCANLINE_MODE",c,vrlg.MCNTRL_SCANLINE_MODE+ba,0,None,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_MEMBRIDGE_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MEMBRIDGE_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MEMBRIDGE_SCANLINE_FRAME_LAST",c,vrlg.MCNTRL_SCANLINE_FRAME_LAST+ba,0,None,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
(("X393_MEMBRIDGE_STATUS_CNTRL",c,vrlg.MEMBRIDGE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set membridge status control register")),
(("X393_MEMBRIDGE_STATUS_CNTRL",c,vrlg.MEMBRIDGE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set membridge status control register")),
(("X393_MEMBRIDGE_LO_ADDR64",c,vrlg.MEMBRIDGE_LO_ADDR64+ba,0,None,"u29","wo","start address of the system memory range in QWORDs (4 LSBs==0)")),
(("X393_MEMBRIDGE_SIZE64",c,vrlg.MEMBRIDGE_SIZE64+ba,0,None,"u29","wo","size of the system memory range in QWORDs (4 LSBs==0), rolls over")),
(("X393_MEMBRIDGE_START64",c,vrlg.MEMBRIDGE_START64+ba,0,None,"u29","wo","start of transfer offset to system memory range in QWORDs (4 LSBs==0)")),
...
...
@@ -582,7 +661,7 @@ class X393ExportC(object):
(('Write-only addresses to PS PIO (Software generated DDR3 memory access sequences)',)),
(("X393_MCNTRL_PS_EN_RST",c,vrlg.MCNTRL_PS_EN_RST+ba,0,None,"x393_ps_pio_en_rst","wo","Set PS PIO enable and reset")),
(("X393_MCNTRL_PS_CMD",c,vrlg.MCNTRL_PS_CMD+ba,0,None,"x393_ps_pio_cmd","wo","Set PS PIO commands")),
(("X393_MCNTRL_PS_STATUS_CNTRL",c,vrlg.MCNTRL_PS_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set PS PIO status control register (status update mode)"))]
(("X393_MCNTRL_PS_STATUS_CNTRL",c,vrlg.MCNTRL_PS_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set PS PIO status control register (status update mode)"))]
#other program status (move to other places?)
ba=vrlg.MCONTR_PHY_16BIT_ADDR
...
...
@@ -590,17 +669,17 @@ class X393ExportC(object):
c=""
sdefines+=[
(('Write-only addresses to to program status report mode for memory controller',)),
(("X393_MCONTR_PHY_STATUS_CNTRL",c,vrlg.MCONTR_PHY_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCONTR_TOP_16BIT_STATUS_CNTRL",c,vrlg.MCONTR_TOP_16BIT_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCONTR_PHY_STATUS_CNTRL",c,vrlg.MCONTR_PHY_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCONTR_TOP_16BIT_STATUS_CNTRL",c,vrlg.MCONTR_TOP_16BIT_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
]
ba=vrlg.MCNTRL_TEST01_ADDR
ia=0
c=""
sdefines+=[
(('Write-only addresses to to program status report mode for test channels',)),
(("X393_MCNTRL_TEST01_CHN2_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_TEST01_CHN3_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_TEST01_CHN4_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_TEST01_CHN2_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCNTRL_TEST01_CHN3_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCNTRL_TEST01_CHN4_STATUS_CNTRL",c,vrlg.MCNTRL_TEST01_CHN4_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(('Write-only addresses for test channels commands',)),
(("X393_MCNTRL_TEST01_CHN2_MODE",c,vrlg.MCNTRL_TEST01_CHN2_MODE+ba,0,None,"x393_test01_mode","wo","Set command for test01 channel 2")),
(("X393_MCNTRL_TEST01_CHN3_MODE",c,vrlg.MCNTRL_TEST01_CHN3_MODE+ba,0,None,"x393_test01_mode","wo","Set command for test01 channel 3")),
(("X393_SENSIO_STATUS_CNTRL",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_STATUS+ba,ia,z3,"x393_status_ctrl","wo","Set status control for SENSIO module")),
(("X393_SENSIO_JTAG",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_JTAG+ba,ia,z3,"x393_sensio_jpag","wo","Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
(("X393_SENSIO_WIDTH",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_WIDTH+ba,ia,z3,"x393_sensio_width","rw","Set sensor line in pixels (0 - use line sync from the sensor)")),
(("X393_SENSIO_DELAYS",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_DELAYS+ba,ia,z3,"x393_sensio_dly","rw","Sensor port input delays (uses 4 DWORDs)")),
(("X393_SENSI2C_STATUS",c,vrlg.SENSI2C_CTRL_RADDR+vrlg.SENSI2C_STATUS+ba,ia,z3,"x393_status_ctrl","rw","Setup sensor i2c status report mode")),
(("X393_SENSIO_STATUS_CNTRL",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_STATUS+ba,ia,z3,"x393_status_ctrl","rw","Set status control for SENSIO module")),
(("X393_SENSIO_JTAG",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_JTAG+ba,ia,z3,"x393_sensio_jpag","wo","Programming interface for multiplexer FPGA (with X393_SENSIO_STATUS)")),
(("X393_SENSIO_WIDTH",c,vrlg.SENSIO_RADDR+vrlg.SENSIO_WIDTH+ba,ia,z3,"x393_sensio_width","rw","Set sensor line in pixels (0 - use line sync from the sensor)")),
(("X393_AFIMUX1_STATUS_CONTROL",c,vrlg.CMPRS_AFIMUX_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","AFI MUX 1 status report mode")),
(("X393_AFIMUX1_SA",c,vrlg.CMPRS_AFIMUX_SA_LEN+ba,1,z3,"x393_afimux_sa","rw","AFI MUX 1 DMA buffer start address in 32-byte blocks")),
(("X393_AFIMUX1_LEN",c,vrlg.CMPRS_AFIMUX_SA_LEN+4+ba,1,z3,"x393_afimux_len","rw","AFI MUX 1 DMA buffer length in 32-byte blocks"))]
#compressor DMA status
ba=vrlg.STATUS_ADDR
ia=1
c="afi_port"
sdefines+=[
(('Read-only sensors status information (pointer offset and last sequence number)',)),
(("X393_AFIMUX0_STATUS",c,vrlg.CMPRS_AFIMUX_REG_ADDR0+ba,ia,z3,"x393_afimux_status","ro","Status of the AFI MUX 0 (including image pointer)")),
(("X393_AFIMUX1_STATUS",c,vrlg.CMPRS_AFIMUX_REG_ADDR1+ba,ia,z3,"x393_afimux_status","ro","Status of the AFI MUX 1 (including image pointer)")),
]
"""
#GPIO control
ba=vrlg.GPIO_ADDR
ia=0
c=""
sdefines+=[
(('_',)),
(('_GPIO contol. Each of the 10 pins can be controlled by the software - individually or simultaneously or from any of the 3 masters (other FPGA modules)',)),
(('_Currently these modules are;',)),
(('_ A - camsync (intercamera synchronization), uses up to 4 pins ',)),
(('_ B - reserved (not yet used) and ',)),
(('_ C - logger (IMU, GPS, images), uses 6 pins, including separate i2c available on extension boards',)),
(('_If several enabled ports try to contol the same bit, highest priority has port C, lowest - software controlled',)),
(("X393_GPIO_SET_PINS","",vrlg.GPIO_SET_PINS+ba,0,None,"x393_gpio_set_pins","wo","State of the GPIO pins and seq. number")),
(("X393_GPIO_STATUS_CONTROL","",vrlg.GPIO_SET_STATUS+ba,0,None,"x393_status_ctrl","rw","GPIO status control mode"))]
ba=vrlg.STATUS_ADDR
sdefines+=[
(('Read-only GPIO pins state',)),
(("X393_GPIO_STATUS","",vrlg.GPIO_STATUS_REG_ADDR+ba,0,None,"x393_gpio_status","ro","State of the GPIO pins and seq. number"))]
(('Write-only addresses to program memory channel 3 (test channel)',)),
(("X393_MCNTRL_CHN3_SCANLINE_MODE",c,vrlg.MCNTRL_SCANLINE_MODE+ba,0,None,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_MCNTRL_CHN3_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN3_SCANLINE_STATUS_CNTRL",c,vrlg.MCNTRL_SCANLINE_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN3_SCANLINE_FRAME_LAST",c,vrlg.MCNTRL_SCANLINE_FRAME_LAST+ba,0,None,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
...
...
@@ -825,7 +994,7 @@ class X393ExportC(object):
sdefines+=[
(('Write-only addresses to program memory channel 2 (test channel)',)),
(("X393_MCNTRL_CHN2_TILED_MODE",c,vrlg.MCNTRL_TILED_MODE+ba,0,None,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_MCNTRL_CHN2_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN2_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN2_TILED_FRAME_LAST",c,vrlg.MCNTRL_TILED_FRAME_LAST+ba,0,None,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
...
...
@@ -839,7 +1008,7 @@ class X393ExportC(object):
sdefines+=[
(('Write-only addresses to program memory channel 4 (test channel)',)),
(("X393_MCNTRL_CHN4_TILED_MODE",c,vrlg.MCNTRL_TILED_MODE+ba,0,None,"x393_mcntrl_mode_scan","wo","Set mode register (write last after other channel registers are set)")),
(("X393_MCNTRL_CHN4_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","wo","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN4_TILED_STATUS_CNTRL",c,vrlg.MCNTRL_TILED_STATUS_CNTRL+ba,0,None,"x393_status_ctrl","rw","Set status control register (status update mode)")),
(("X393_MCNTRL_CHN4_TILED_FRAME_LAST",c,vrlg.MCNTRL_TILED_FRAME_LAST+ba,0,None,"x393_mcntrl_window_last_frame_num","wo","Set last frame number (number of frames in buffer minus 1)")),
...
...
@@ -1448,7 +1617,7 @@ class X393ExportC(object):
def_enc_gamma_tbl_data(self):
dw=[]
dw.append(("base",0,10,0,"Knee point value (to be interpolated between)"))
dw.append(("diff",10,7,0,"Difference to next (signed, -64..+63)"))
dw.append((("diff","char"),10,7,0,"Difference to next (signed, -64..+63)"))