Commit 9024d1d4 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Fixed typos

parent 944ff196

.settings/com.elphel.vdt.VivadoBitstream.prefs

+1 −2
Original line number Diff line number Diff line
@@ -3,6 +3,5 @@ VivadoBitstream_105_force=true 
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_124_force=true

VivadoBitstream_125_force=true

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+2 −1
Original line number Diff line number Diff line
@@ -6,9 +6,10 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x 
VivadoSynthesis_122_SkipSnapshotSynth=true

VivadoSynthesis_123_ResetProject=true

VivadoSynthesis_123_SkipSnapshotSynth=true

VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->

VivadoSynthesis_127_verbose=true

VivadoSynthesis_81_parser_mode=1

VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->

VivadoSynthesis_95_ShowInfo=true

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

+6 −1
Original line number Diff line number Diff line 
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->

com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->

eclipse.preferences.version=1

iverilog_100_TopModulesOther=glbl<-@\#\#@->

iverilog_101_TopModulesOther=glbl<-@\#\#@->
@@ -6,15 +6,20 @@ iverilog_102_ExtraFiles=glbl.v<-@\#\#@-> 
iverilog_102_TopModulesOther=glbl<-@\#\#@->

iverilog_103_ExtraFiles=glbl.v<-@\#\#@->

iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->

iverilog_103_TopModulesOther=glbl<-@\#\#@->

iverilog_104_ExtraFiles=glbl.v<-@\#\#@->

iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->

iverilog_105_ExtraFiles=glbl.v<-@\#\#@->

iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->

iverilog_106_IncludeDir=${verilog_project_loc}_sata/x393/includes<-@\#\#@->${verilog_project_loc}_sata/x393/ddr3<-@\#\#@->

iverilog_109_ShowNoProblem=true

iverilog_110_ShowNoProblem=true

iverilog_110_ShowWarnings=false

iverilog_111_ShowNoProblem=true

iverilog_113_SaveLogsPreprocessor=false

iverilog_113_SaveLogsSimulator=true

iverilog_114_SaveLogsSimulator=true

iverilog_115_SaveLogsSimulator=true

iverilog_121_GrepFindErrWarn=error|warning|sorry

iverilog_77_Param_Exe=/usr/local/bin/iverilog

iverilog_78_VVP_Exe=/usr/local/bin/vvp

axi/axibram_write.v

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ module axibram_write #( 
   input  [11:0] wid,     // WID[11:0], input

   input         wlast,   // WLAST, input

   input  [ 3:0] wstb,    // WSTRB[3:0], input

// AXI PS Master GP0: Write Responce

// AXI PS Master GP0: Write response

   output        bvalid,  // BVALID, output

   input         bready,  // BREADY, input

   output [11:0] bid,     // BID[11:0], output

axi/cmprs_afi_mux.v

+1 −1
Original line number Diff line number Diff line
@@ -542,7 +542,7 @@ items_left 
        .we         (cmd_we)    // output

    );

    

    wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write responce one

    wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write response one



    cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (

        .hclk                (hclk),                // input