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Commit 8f79e6f7 authored by Andrey Filippov's avatar Andrey Filippov
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debugging scanline read memory access

parent cbbd4ed1
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includes/x393_parameters.vh
View file @ 8f79e6f7
......@@ -183,11 +183,11 @@
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......@@ -208,7 +208,7 @@
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......
memctrl/cmd_encod_linear_wr.v
View file @ 8f79e6f7
......@@ -25,6 +25,7 @@ module cmd_encod_linear_wr #(
// parameter BASEADDR = 0,
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
) (
......@@ -36,13 +37,13 @@ module cmd_encod_linear_wr #(
input [2:0] bank_in, // bank address
input [ADDRESS_NUMBER-1:0] row_in, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column (3 LSBs should be 0?)
input [5:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full burst of 8
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
localparam ROM_WIDTH=12;
localparam ROM_WIDTH=13;
localparam ROM_DEPTH=4;
localparam ENC_NOP= 0;
......@@ -52,9 +53,10 @@ module cmd_encod_linear_wr #(
localparam ENC_SEL= 4;
localparam ENC_ODT= 5;
localparam ENC_CMD_SHIFT= 6; // [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE
localparam ENC_PAUSE_SHIFT=8; // [9:8] - 2- bit pause (for NOP commandes)
localparam ENC_PAUSE_SHIFT= 8; // [9:8] - 2- bit pause (for NOP commandes)
localparam ENC_PRE_DONE= 10;
localparam ENC_BUF_PGNEXT= 11;
localparam ENC_DUAL_CYC= 12; // 2-cycle command (with nop or skip) to count number of buffer reads (longer pauses are not used with buffer reads)
localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
localparam ENC_CMD_WRITE= 1;
......@@ -70,7 +72,7 @@ module cmd_encod_linear_wr #(
reg [ADDRESS_NUMBER-1:0] row; // memory row
reg [COLADDR_NUMBER-4:0] col; // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
reg [2:0] bank; // memory bank;
reg [5:0] num128; // number of 128-bit words to transfer
reg [NUM_XFER_BITS:0] num128; // number of 128-bit words to transfer
reg gen_run;
reg gen_run_d;
......@@ -82,13 +84,30 @@ module cmd_encod_linear_wr #(
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg buf_rd_23; // read buffer at steps 2&3 (0 if only 1 read is required)
reg start_d;
// reg [ROM_DEPTH-1:0] gen_addr_jump; // next conditonal address
reg [NUM_XFER_BITS:0] num_bufrd_left; //counts number of buffer reads left
wire [NUM_XFER_BITS:0] num_bufrd_left_next_w; //next clock value of the counter
wire next_zero_w=(num_bufrd_left_next_w==0);
reg cut_buf_rd;
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_WRITE:CMD_NOP);
assign num_bufrd_left_next_w= num_bufrd_left - (rom_r[ENC_DUAL_CYC]?2:1);
// prepare jump address? and bufrd during 2,3
// make num128 7-bits to accommodate 64!
always @ (posedge clk) begin
start_d <= start;
if (start_d) num_bufrd_left <= {num128[NUM_XFER_BITS-1:0],1'b0};
else if (rom_r[ENC_BUF_RD]) num_bufrd_left <= num_bufrd_left_next_w;
cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd || next_zero_w);
end
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
......@@ -98,14 +117,14 @@ module cmd_encod_linear_wr #(
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[5:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=REPEAT_ADDR) || (num128[5:1]==0)) gen_addr <= gen_addr+1; // not in a loop
else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops
if (rst) num128 <= 0;
else if (start) num128 <= num128_in;
else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
else if (!gen_run) num128 <= 0; //
else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1;
else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
end
always @ (posedge clk) if (start) begin
......@@ -119,11 +138,12 @@ module cmd_encod_linear_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h2: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) |(1 << ENC_SEL) | (1 << ENC_ODT);
4'h3: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) |(1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // will repeet
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DUAL_CYC); // dual cycle
4'h2: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT); // single cycle
4'h3: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
// next may loop
4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DUAL_CYC); // dual cycle
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT);
......@@ -140,7 +160,8 @@ module cmd_encod_linear_wr #(
else enc_wr <= gen_run || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr || !gen_run_d;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
......@@ -155,7 +176,7 @@ module cmd_encod_linear_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
......@@ -171,7 +192,7 @@ module cmd_encod_linear_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
end
......
memctrl/mcntrl393.v
View file @ 8f79e6f7
......@@ -166,11 +166,11 @@ module mcntrl393 #(
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......@@ -193,7 +193,7 @@ module mcntrl393 #(
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......
memctrl/mcntrl_linear_rw.v
View file @ 8f79e6f7
......@@ -29,11 +29,11 @@ module mcntrl_linear_rw #(
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_ADDR= 'h120,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......@@ -97,6 +97,7 @@ module mcntrl_linear_rw #(
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
......@@ -137,7 +138,7 @@ module mcntrl_linear_rw #(
// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}
reg [3:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}
reg [3:0] mode_reg;//mode register: {extra_pages[1:0],enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
// reg [FRAME_WIDTH_BITS:0] frame_width; // (programmed) 0- max
......@@ -196,6 +197,7 @@ module mcntrl_linear_rw #(
end
end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
// assign xfer_num128= xfer_num128_m1_r[NUM_XFER_BITS-1:0];
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
assign xfer_start= xfer_start_r[0];
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
......@@ -221,6 +223,7 @@ module mcntrl_linear_rw #(
integer i;
// localparam EXTRA_BITS={ADDRESS_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
// localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
......@@ -228,7 +231,8 @@ module mcntrl_linear_rw #(
row_left <= window_width - curr_x; // 14 bits - 13 bits
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?(1<<NUM_XFER_BITS):row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
xfer_num128_r<= (mem_page_left < {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// xfer_num128_m1_r <= xfer_num128_r[NUM_XFER_BITS-1:0]-1;
// xfer_num128_r<= (mem_page_left> {EXTRA_BITS, lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
......
memctrl/mcntrl_tiled_rw.v
View file @ 8f79e6f7
......@@ -34,7 +34,7 @@ module mcntrl_tiled_rw#(
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......
memctrl/memctrl16.v
View file @ 8f79e6f7
......@@ -778,11 +778,14 @@ always @ (posedge rst or posedge mclk) begin
// else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_fill <= 0;
// else if (grant) cmd_seq_fill <= 1;
//TODO: Modify,cmd_seq_fill was initially used to see if any sequaence data was written (or PS is used), now it is cmd_seq_set
if (rst) cmd_seq_fill <= 0;
// else if (!mcontr_enabled || seq_wr ) cmd_seq_fill <= 0;
// else if (grant) cmd_seq_fill <= 1;
else if (!mcontr_enabled || grant ) cmd_seq_fill <= 0;
else if (seq_wr) cmd_seq_fill <= 1;
// else if (!mcontr_enabled || grant ) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full ) cmd_seq_fill <= 0;
// else if (seq_wr) cmd_seq_fill <= 1;
else if (grant) cmd_seq_fill <= 1;
if (rst) cmd_seq_full <= 0;
else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_full <= 0;
......
memctrl/phy/mcontr_sequencer.v
View file @ 8f79e6f7
......@@ -214,7 +214,7 @@ module mcontr_sequencer #(
// wire [35:0] phy_cmd; // input[35:0]
wire [31:0] phy_cmd_word; // selected output from eithe cmd0 buffer or cmd1 buffer
wire [31:0] phy_cmd_word; // selected output from either cmd0 buffer or cmd1 buffer
wire [31:0] phy_cmd0_word; // cmd0 buffer output
wire [31:0] phy_cmd1_word; // cmd1 buffer output
wire buf_raddr_reset;
......@@ -274,7 +274,10 @@ module mcontr_sequencer #(
assign run_busy=cmd_busy[0]; //earliest
assign pause=cmd_fetch? (phy_cmd_add_pause || (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
/// debugging
assign phy_cmd_word = cmd_sel?phy_cmd1_word:phy_cmd0_word; // TODO: hangs even with 0-s in phy_cmd
// assign phy_cmd_word = cmd_sel?phy_cmd1_word:phy_cmd0_word; // TODO: hangs even with 0-s in phy_cmd
assign phy_cmd_word = (cmd_sel?phy_cmd1_word:phy_cmd0_word) & {32{cmd_busy[2]}}; // TODO: hangs even with 0-s in phy_cmd
/// assign phy_cmd_word = phy_cmd_word?0:0;
// assign buf_rdata[63:0] = ({64{buf_sel_1hot[1]}} & buf1_rdata[63:0]); // ORed with other read channels terms
......
x393.v
View file @ 8f79e6f7
......@@ -188,11 +188,11 @@ module x393 #(
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......@@ -213,7 +213,7 @@ module x393 #(
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
......
x393_testbench01.sav
View file @ 8f79e6f7
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Fri Feb 13 20:24:18 2015
[*] Sat Feb 14 08:08:56 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150213113832125.lxt"
[dumpfile_mtime] "Fri Feb 13 18:43:22 2015"
[dumpfile_size] 233070602
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150213233756874.lxt"
[dumpfile_mtime] "Sat Feb 14 06:45:49 2015"
[dumpfile_size] 133654536
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 97060000
[size] 1823 1173
[pos] 1922 0
*-23.698502 146225000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 150882500
[size] 1823 1180
[pos] 1934 -3
*-14.698502 150936875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
......@@ -23,13 +24,12 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 328
[signals_width] 377
[signals_width] 445
[sst_expanded] 1
[sst_vpaned_height] 371
[sst_vpaned_height] 377
@800200
-top_simulation
@28
......@@ -885,6 +885,18 @@ x393_testbench01.x393_i.SDODT[0]
-DDR3
@c00200
-scheduler
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_wr_chn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.en_schedul[0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0]
@28
......@@ -1213,11 +1225,417 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
@1401200
-scheduler
@c00200
-mcntrl393_test01
@22
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_data[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_frame_start_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_next_page_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_suspend_w[0]
x393_testbench01.x393_i.mcntrl393_test01_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn4_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn2[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn3[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn4[15:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn2[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh2_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh2_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh3_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh3_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh4_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh4_status[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2_start[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3_start[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4[21:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn4_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn2_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn3_r[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
@1401200
-mcntrl393_test01
@c00200
-linear_ch3
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.chn_rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.cmd_wrmem[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.curr_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_done_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_full_width_r[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.i[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.lim_by_xfer[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.line_unfinished[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.mode_reg[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.msw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.next_y[16:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.page_cntr[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.par_mod_r[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pre_want[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.row_left[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.set_window_x0y0_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.start_addr_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.status_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.suspend[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_y0[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_num128_r[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_reset_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_reset_page_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_row[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_want[0]
@1401200
-linear_ch3
@800200
-cmd1_buf
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0]
@23
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause[0]
@800028
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(2)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@1001200
-group_end
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.ren[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0]
@22
x393_testbench01.axi_set_dqs_odelay.delay[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
@1000200
-cmd1_buf
@200
-
@800200
-encod_linear_wr
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_addr_start[10:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_addr_cur[9:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_addr[10:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.cut_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.done[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.full_cmd[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.gen_addr[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.gen_run_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.next_zero_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.num128[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.num128_in[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.num_bufrd_left[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.num_bufrd_left_next_w[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.rom_cmd[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.rom_r[12:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.rom_skip[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.row_in[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.start_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_wr_i.start_d[0]
@200
-
@1000200
-encod_linear_wr
@c00200
-encod_linear_mux
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.bank2[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.bank3[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.bank_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.bank_w[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.num128_2[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.num128_3[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.num128_r[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.num128_w[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.row2[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.row3[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.row_r[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.row_w[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start2[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start3[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_col2[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_col3[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_col_r[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_col_w[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_rd[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_rd_w[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_mux_i.start_wr_w[0]
@1401200
-encod_linear_mux
@200
-
@c00200
-phy_cmd
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.pause_len[9:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr[29:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_calm[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_prev[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_calm[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_prev[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_add_pause[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_nop[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_word[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_dis_dq[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_dis_dqs[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_en_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dci_ready[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dly_ready[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_en[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_locked_mmcm[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_locked_pll[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt[1:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_ps_out[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_ps_rdy[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_cur[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0]
@1401200
-phy_cmd
@c00200
-byte_lane_0
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
......@@ -1340,9 +1758,8 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.val
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.values[255:0]
@1401200
-index_max16
@800200
-PS_PIO
@c00200
-PS_PIO
-PS_PIO_STATUS
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0]
......@@ -1373,7 +1790,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.wd[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.we[0]
@1401200
-PS_PIO_STATUS
@800200
@c00200
-PS_PIO_CHN0
@200
-
......@@ -1418,11 +1835,11 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
@1000200
@1401200
-PS_PIO_CHN0
@200
-
@800200
@c00200
-PS_PIO_CHN1
@200
-
......@@ -1453,9 +1870,9 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000200
@1401200
-PS_PIO_CHN1
@c00201
@c00200
-other_modules
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrun[0]
......@@ -1492,7 +1909,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
@1001200
-group_end
@1401201
@1401200
-other_modules
@200
-
......@@ -1608,7 +2025,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
@1000200
@1401200
-PS_PIO
@800200
-memcntrl16_0
......
x393_testbench01.tf
View file @ 8f79e6f7
......@@ -27,7 +27,8 @@
`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
`define PS_PIO_WAIT_COMPLETE 0
`define TEST_SCANLINE_WRITE 1
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
......@@ -182,6 +183,18 @@ module x393_testbench01 #(
integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
localparam SCANLINE_X0Y0= 'h00050003; // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TEST01_START_FRAME= 1;
localparam TEST01_NEXT_PAGE= 2;
localparam TEST01_SUSPEND= 4;
// integer ii;
always #(CLKIN_PERIOD/2) CLK <= ~CLK;
initial begin
......@@ -334,7 +347,29 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
`endif
#20000;
`ifdef TEST_SCANLINE_WRITE
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH, SCANLINE_WINDOW_WH);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, SCANLINE_X0Y0);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTXY);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(3,0); // lowest priority channel 1
enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
// localparam TEST01_START_FRAME= 1;
// localparam TEST01_NEXT_PAGE= 2;
// localparam TEST01_SUSPEND= 4;
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_START_FRAME);
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
// now need to repeat - test ready, then next page
`endif
#40000;
$finish;
end
// protect from never end
......
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